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-rw-r--r--toolchain/gcc/patches/4.8-linaro/200-musl.patch31
-rw-r--r--toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch11
-rw-r--r--toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch2
-rw-r--r--toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch2
-rw-r--r--toolchain/gcc/patches/4.8-linaro/880-no_java_section.patch11
-rw-r--r--toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch4
-rw-r--r--toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch2
-rw-r--r--toolchain/gcc/patches/4.8-linaro/999_realtek.patch47
-rw-r--r--toolchain/gcc/patches/4.8.0/200-musl.patch13
-rw-r--r--toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch11
-rw-r--r--toolchain/gcc/patches/4.8.0/880-no_java_section.patch11
-rw-r--r--toolchain/gcc/patches/4.8.0/999_realtek.patch203
12 files changed, 310 insertions, 38 deletions
diff --git a/toolchain/gcc/patches/4.8-linaro/200-musl.patch b/toolchain/gcc/patches/4.8-linaro/200-musl.patch
index 8cf45eb61..3fe5a7eba 100644
--- a/toolchain/gcc/patches/4.8-linaro/200-musl.patch
+++ b/toolchain/gcc/patches/4.8-linaro/200-musl.patch
@@ -1,6 +1,6 @@
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
-@@ -549,7 +549,7 @@ case ${target} in
+@@ -550,7 +550,7 @@ case ${target} in
esac
# Common C libraries.
@@ -9,7 +9,7 @@
# Common parts for widely ported systems.
case ${target} in
-@@ -652,6 +652,9 @@ case ${target} in
+@@ -653,6 +653,9 @@ case ${target} in
*-*-*uclibc*)
tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC"
;;
@@ -34,7 +34,7 @@
#undef LINK_SPEC
--- a/gcc/config/i386/linux.h
+++ b/gcc/config/i386/linux.h
-@@ -21,3 +21,4 @@ along with GCC; see the file COPYING3.
+@@ -21,3 +21,4 @@ along with GCC; see the file COPYING3.
#define GNU_USER_LINK_EMULATION "elf_i386"
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
@@ -127,7 +127,7 @@
+Use musl C library
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
-@@ -18,3 +18,5 @@ along with GCC; see the file COPYING3.
+@@ -18,3 +18,5 @@ along with GCC; see the file COPYING3.
<http://www.gnu.org/licenses/>. */
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
@@ -135,7 +135,7 @@
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-mips.so.1"
--- a/gcc/config/rs6000/linux64.h
+++ b/gcc/config/rs6000/linux64.h
-@@ -364,17 +364,21 @@ extern int dot_symbols;
+@@ -354,17 +354,21 @@ extern int dot_symbols;
#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1"
#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
@@ -159,11 +159,11 @@
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64)
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
-
- #define LINK_OS_LINUX_SPEC32 "-m elf32ppclinux %{!shared: %{!static: \
+ #undef DEFAULT_ASM_ENDIAN
+ #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
-@@ -789,15 +789,18 @@ extern int fixuplabelno;
+@@ -778,15 +778,18 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
@@ -295,7 +295,7 @@
;;
--- a/gcc/config/mips/linux64.h
+++ b/gcc/config/mips/linux64.h
-@@ -27,6 +27,9 @@ along with GCC; see the file COPYING3.
+@@ -27,6 +27,9 @@ along with GCC; see the file COPYING3.
#define GLIBC_DYNAMIC_LINKERN32 "/lib32/ld.so.1"
#define UCLIBC_DYNAMIC_LINKERN32 "/lib32/ld-uClibc.so.0"
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
@@ -306,3 +306,16 @@
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \
- BIONIC_DYNAMIC_LINKERN32)
+ BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32)
+--- a/gcc/config/sparc/linux64.h 2013-09-10 10:02:45.663973856 +0100
++++ b/gcc/config/sparc/linux64.h 2013-09-10 10:03:17.871972435 +0100
+@@ -104,6 +104,9 @@
+ #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+ #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
+
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-sparc.so.1"
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-sparc.so.1"
++
+ #ifdef SPARC_BI_ARCH
+
+ #undef SUBTARGET_EXTRA_SPECS
+
diff --git a/toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch
index a3816a17f..33cf8add3 100644
--- a/toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch
+++ b/toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch
@@ -12,3 +12,14 @@
# Just for these, we omit the frame pointer since it makes such a big
# difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -55,8 +55,6 @@
+ %{shared:-lc} \
+ %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #define LINUX_TARGET_LINK_SPEC "%{h*} \
diff --git a/toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch b/toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch
index 4a77b86c1..ee3f60273 100644
--- a/toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch
+++ b/toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch
@@ -1,6 +1,6 @@
--- a/gcc/config/arm/linux-eabi.h
+++ b/gcc/config/arm/linux-eabi.h
-@@ -114,10 +114,6 @@
+@@ -118,10 +118,6 @@
#define ENDFILE_SPEC \
LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)
diff --git a/toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch b/toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch
index d8c460a92..14e4fbdce 100644
--- a/toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch
+++ b/toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch
@@ -1,6 +1,6 @@
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
-@@ -17653,7 +17653,7 @@ rs6000_savres_strategy (rs6000_stack_t *
+@@ -17664,7 +17664,7 @@ rs6000_savres_strategy (rs6000_stack_t *
/* Define cutoff for using out-of-line functions to save registers. */
if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
{
diff --git a/toolchain/gcc/patches/4.8-linaro/880-no_java_section.patch b/toolchain/gcc/patches/4.8-linaro/880-no_java_section.patch
new file mode 100644
index 000000000..def6c9f4a
--- /dev/null
+++ b/toolchain/gcc/patches/4.8-linaro/880-no_java_section.patch
@@ -0,0 +1,11 @@
+--- a/gcc/defaults.h
++++ b/gcc/defaults.h
+@@ -380,7 +380,7 @@ see the files COPYING3 and COPYING.RUNTI
+ /* If we have named section and we support weak symbols, then use the
+ .jcr section for recording java classes which need to be registered
+ at program start-up time. */
+-#if defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK
++#if 0 && defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK
+ #ifndef JCR_SECTION_NAME
+ #define JCR_SECTION_NAME ".jcr"
+ #endif
diff --git a/toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch b/toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch
index 3b37a3f8f..eb9a7c6c7 100644
--- a/toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch
+++ b/toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch
@@ -209,7 +209,7 @@
-Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol
-Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol
-Wformat-security -Wformat-y2k @gol
-@@ -4808,6 +4808,22 @@ This option is only supported for C and
+@@ -4809,6 +4809,22 @@ This option is only supported for C and
@option{-Wall} and by @option{-Wpedantic}, which can be disabled with
@option{-Wno-pointer-sign}.
@@ -232,7 +232,7 @@
@item -Wstack-protector
@opindex Wstack-protector
@opindex Wno-stack-protector
-@@ -6919,7 +6935,7 @@ so, the first branch is redirected to ei
+@@ -6920,7 +6936,7 @@ so, the first branch is redirected to ei
second branch or a point immediately following it, depending on whether
the condition is known to be true or false.
diff --git a/toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch
index 4baa96693..8698eda5f 100644
--- a/toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch
+++ b/toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch
@@ -1,6 +1,6 @@
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
-@@ -8003,7 +8003,10 @@ getenv_spec_function (int argc, const ch
+@@ -8004,7 +8004,10 @@ getenv_spec_function (int argc, const ch
value = getenv (argv[0]);
if (!value)
diff --git a/toolchain/gcc/patches/4.8-linaro/999_realtek.patch b/toolchain/gcc/patches/4.8-linaro/999_realtek.patch
index c5a0998a7..5f7e01660 100644
--- a/toolchain/gcc/patches/4.8-linaro/999_realtek.patch
+++ b/toolchain/gcc/patches/4.8-linaro/999_realtek.patch
@@ -85,7 +85,7 @@ diff -rupN ./gcc.orig/gcc/common.opt ./gcc.new/gcc/common.opt
diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
--- a/gcc/config/mips/mips.c 2013-02-19 02:04:49.000000000 +0200
-+++ b/gcc/config/mips/mips.c 2013-10-14 20:23:06.143036336 +0300
++++ b/gcc/config/mips/mips.c 2013-11-09 06:12:14.396962114 +0200
@@ -56,6 +56,9 @@ along with GCC; see the file COPYING3.
#include "target-globals.h"
#include "opts.h"
@@ -96,10 +96,10 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
#define UNSPEC_ADDRESS_P(X) \
(GET_CODE (X) == UNSPEC \
-@@ -925,6 +928,27 @@ static const struct mips_rtx_cost_data
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
+@@ -731,6 +734,27 @@ static const struct mips_rtx_cost_data m
+ /* Costs to use when optimizing for speed, indexed by processor. */
+ static const struct mips_rtx_cost_data
+ mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
+ { /* RLX */
+ DEFAULT_COSTS
+ },
@@ -121,9 +121,9 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
+ { /* RLX */
+ DEFAULT_COSTS
+ },
- { /* R6000 */
- COSTS_N_INSNS (3), /* fp_add */
- COSTS_N_INSNS (5), /* fp_mult_sf */
+ { /* R3000 */
+ COSTS_N_INSNS (2), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
@@ -1212,13 +1236,62 @@ mips_far_type_p (const_tree type)
static bool
mips_mips16_decl_p (const_tree decl)
@@ -501,11 +501,11 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
bool
diff -rupN ./gcc.orig/gcc/config/mips/mips-cpus.def ./gcc.new/gcc/config/mips/mips-cpus.def
--- a/gcc/config/mips/mips-cpus.def 2013-01-10 22:38:27.000000000 +0200
-+++ b/gcc/config/mips/mips-cpus.def 2013-10-14 19:45:36.929578308 +0300
-@@ -53,6 +53,14 @@ MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0
- MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
- MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
++++ b/gcc/config/mips/mips-cpus.def 2013-10-19 16:36:32.376188609 +0300
+@@ -49,6 +49,13 @@ MIPS_CPU ("mips64", PROCESSOR_5KC, 64, P
+ MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY)
+ /* MIPS I processors. */
+MIPS_CPU ("rlx4081", PROCESSOR_RLX4081, 1, 0)
+MIPS_CPU ("rlx4180", PROCESSOR_RLX4180, 1, 0)
+MIPS_CPU ("rlx4181", PROCESSOR_RLX4181, 1, 0)
@@ -513,10 +513,9 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips-cpus.def ./gcc.new/gcc/config/mips/mi
+MIPS_CPU ("rlx5181", PROCESSOR_RLX5181, 1, 0)
+MIPS_CPU ("rlx5280", PROCESSOR_RLX5280, 1, 0)
+MIPS_CPU ("rlx5281", PROCESSOR_RLX5281, 1, 0)
-+
- /* MIPS II processors. */
- MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
-
+ MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
+ MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
+ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h
--- a/gcc/config/mips/mips.h 2013-01-10 22:38:27.000000000 +0200
+++ b/gcc/config/mips/mips.h 2013-10-14 19:57:12.512949903 +0300
@@ -732,11 +731,11 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h
diff -rupN ./gcc.orig/gcc/config/mips/mips.md ./gcc.new/gcc/config/mips/mips.md
--- a/gcc/config/mips/mips.md 2013-01-24 19:46:41.000000000 +0200
-+++ b/gcc/config/mips/mips.md 2013-10-14 19:46:13.179580218 +0300
-@@ -59,6 +59,13 @@
- r8000
- r9000
- r10000
++++ b/gcc/config/mips/mips.md 2013-10-19 16:36:20.482855340 +0300
+@@ -22,6 +22,13 @@
+ ;; <http://www.gnu.org/licenses/>.
+
+ (define_enum "processor" [
+ rlx4081
+ rlx4180
+ rlx4181
@@ -744,9 +743,9 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.md ./gcc.new/gcc/config/mips/mips.md
+ rlx5181
+ rlx5280
+ rlx5281
- sb1
- sb1a
- sr71000
+ r3000
+ 4kc
+ 4kp
@@ -679,11 +686,17 @@
;; Can the instruction be put into a delay slot?
diff --git a/toolchain/gcc/patches/4.8.0/200-musl.patch b/toolchain/gcc/patches/4.8.0/200-musl.patch
index 94a45e217..2e6df47e4 100644
--- a/toolchain/gcc/patches/4.8.0/200-musl.patch
+++ b/toolchain/gcc/patches/4.8.0/200-musl.patch
@@ -306,3 +306,16 @@
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \
- BIONIC_DYNAMIC_LINKERN32)
+ BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32)
+--- a/gcc/config/sparc/linux64.h 2013-09-10 10:02:45.663973856 +0100
++++ b/gcc/config/sparc/linux64.h 2013-09-10 10:03:17.871972435 +0100
+@@ -104,6 +104,9 @@
+ #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+ #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
+
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-sparc.so.1"
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-sparc.so.1"
++
+ #ifdef SPARC_BI_ARCH
+
+ #undef SUBTARGET_EXTRA_SPECS
+
diff --git a/toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch
index a3816a17f..33cf8add3 100644
--- a/toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch
+++ b/toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch
@@ -12,3 +12,14 @@
# Just for these, we omit the frame pointer since it makes such a big
# difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -55,8 +55,6 @@
+ %{shared:-lc} \
+ %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #define LINUX_TARGET_LINK_SPEC "%{h*} \
diff --git a/toolchain/gcc/patches/4.8.0/880-no_java_section.patch b/toolchain/gcc/patches/4.8.0/880-no_java_section.patch
new file mode 100644
index 000000000..def6c9f4a
--- /dev/null
+++ b/toolchain/gcc/patches/4.8.0/880-no_java_section.patch
@@ -0,0 +1,11 @@
+--- a/gcc/defaults.h
++++ b/gcc/defaults.h
+@@ -380,7 +380,7 @@ see the files COPYING3 and COPYING.RUNTI
+ /* If we have named section and we support weak symbols, then use the
+ .jcr section for recording java classes which need to be registered
+ at program start-up time. */
+-#if defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK
++#if 0 && defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK
+ #ifndef JCR_SECTION_NAME
+ #define JCR_SECTION_NAME ".jcr"
+ #endif
diff --git a/toolchain/gcc/patches/4.8.0/999_realtek.patch b/toolchain/gcc/patches/4.8.0/999_realtek.patch
new file mode 100644
index 000000000..e0f5bc237
--- /dev/null
+++ b/toolchain/gcc/patches/4.8.0/999_realtek.patch
@@ -0,0 +1,203 @@
+diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
+--- a/gcc/config/mips/mips.c 2013-02-19 02:04:49.000000000 +0200
++++ b/gcc/config/mips/mips.c 2013-09-17 15:56:40.036229582 +0300
+@@ -1121,6 +1121,27 @@ static const struct mips_rtx_cost_data
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
+ }
+ };
+
+@@ -12794,6 +12815,9 @@ mips_issue_rate (void)
+ case PROCESSOR_R9000:
+ case PROCESSOR_OCTEON:
+ case PROCESSOR_OCTEON2:
++ case PROCESSOR_RLX5280:
++ case PROCESSOR_RLX5281:
++ case PROCESSOR_RLX4281:
+ return 2;
+
+ case PROCESSOR_SB1:
+diff -rupN ./gcc.orig/gcc/config/mips/mips-cpus.def ./gcc.new/gcc/config/mips/mips-cpus.def
+--- a/gcc/config/mips/mips-cpus.def 2013-01-10 22:38:27.000000000 +0200
++++ b/gcc/config/mips/mips-cpus.def 2013-09-17 17:10:08.249807200 +0300
+@@ -52,6 +52,14 @@ MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65,
+ MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
+ MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
+ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
++MIPS_CPU ("rlx4081", PROCESSOR_RLX4081, 1, 0)
++MIPS_CPU ("rlx4180", PROCESSOR_RLX4180, 1, 0)
++MIPS_CPU ("rlx4181", PROCESSOR_RLX4181, 1, 0)
++MIPS_CPU ("rlx4281", PROCESSOR_RLX4281, 1, 0)
++MIPS_CPU ("rlx5181", PROCESSOR_RLX5181, 1, 0)
++MIPS_CPU ("rlx5280", PROCESSOR_RLX5280, 1, 0)
++MIPS_CPU ("rlx5281", PROCESSOR_RLX5281, 1, 0)
++
+
+ /* MIPS II processors. */
+ MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
+diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h
+--- a/gcc/config/mips/mips.h 2013-01-10 22:38:27.000000000 +0200
++++ b/gcc/config/mips/mips.h 2013-09-17 16:38:07.036367401 +0300
+@@ -222,6 +222,32 @@ struct mips_cpu_info {
+ #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
+ #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
+
++#define TARGET_RLX4081 (mips_arch == PROCESSOR_RLX4081)
++#define TARGET_RLX4180 (mips_arch == PROCESSOR_RLX4180)
++#define TARGET_RLX4181 (mips_arch == PROCESSOR_RLX4181)
++#define TARGET_RLX4281 (mips_arch == PROCESSOR_RLX4281)
++#define TARGET_RLX5181 (mips_arch == PROCESSOR_RLX5181)
++#define TARGET_RLX5280 (mips_arch == PROCESSOR_RLX5280)
++#define TARGET_RLX5281 (mips_arch == PROCESSOR_RLX5281)
++
++/* All RLX processor */
++#define TARGET_RLX (TARGET_RLX4081 || TARGET_RLX4180 \
++ || TARGET_RLX4181 || TARGET_RLX4281 || TARGET_RLX5181 \
++ || TARGET_RLX5280 || TARGET_RLX5281)
++
++/* RLX processor which supports Radiax instructions */
++#define TARGET_RLX_RAD (TARGET_RLX5181 || TARGET_RLX5280 || TARGET_RLX5281)
++#define TARGET_RLX_NORAD (TARGET_RLX && !TARGET_RLX_RAD)
++
++/* RLX processor which supprts gpr-interlocks */
++#define TARGET_RLX_INTERLOCK (TARGET_RLX4281 || TARGET_RLX5280 || TARGET_RLX5281)
++#define TARGET_RLX_NO_INTERLOCK (TARGET_RLX && !TARGET_RLX_INTERLOCK)
++
++#define TARGET_RLX1 (TARGET_RLX4181 || TARGET_RLX4281 || TARGET_RLX5181 \
++ || TARGET_RLX5280 || TARGET_RLX5281)
++
++#define TARGET_TAROKO (TARGET_RLX4281 || TARGET_RLX5281)
++
+ /* Scheduling target defines. */
+ #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
+ #define TUNE_24K (mips_tune == PROCESSOR_24KC \
+@@ -695,7 +721,7 @@ struct mips_cpu_info {
+
+ #define MIPS_ISA_LEVEL_SPEC \
+ "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
+- %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
++ %{march=mips1|march=r2000|march=r3000|march=r3900|march=rlx4081|march=rlx4180|march=rlx4181|march=rlx5181|march=rlx5280|march=rlx5281:-mips1} \
+ %{march=mips2|march=r6000:-mips2} \
+ %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
+ %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
+@@ -838,7 +864,14 @@ struct mips_cpu_info {
+
+ /* ISA has the integer conditional move instructions introduced in mips4 and
+ ST Loongson 2E/2F. */
+-#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
++#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
++ || TARGET_LOONGSON_2EF \
++ || ((TARGET_RLX5280 \
++ || TARGET_RLX5181 \
++ || TARGET_RLX5281 \
++ || TARGET_RLX4181 \
++ || TARGET_RLX4281) \
++ && !TARGET_MIPS16))
+
+ /* ISA has LDC1 and SDC1. */
+ #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
+@@ -1012,7 +1045,8 @@ struct mips_cpu_info {
+ and "addiu $4,$4,1". */
+ #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
+ && !TARGET_MIPS3900 \
+- && !TARGET_MIPS16)
++ && !TARGET_MIPS16 \
++ && !TARGET_RLX_INTERLOCK)
+
+ /* Likewise mtc1 and mfc1. */
+ #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
+@@ -1039,7 +1073,8 @@ struct mips_cpu_info {
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2 \
+ || TARGET_MIPS5500 \
+- || TARGET_LOONGSON_2EF)
++ || TARGET_LOONGSON_2EF \
++ || TARGET_RLX)
+
+ /* ISA includes synci, jr.hb and jalr.hb. */
+ #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
+@@ -1047,7 +1082,8 @@ struct mips_cpu_info {
+ && !TARGET_MIPS16)
+
+ /* ISA includes sync. */
+-#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
++#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900 || TARGET_TAROKO) \
++ && !TARGET_MIPS16)
+ #define GENERATE_SYNC \
+ (target_flags_explicit & MASK_LLSC \
+ ? TARGET_LLSC && !TARGET_MIPS16 \
+@@ -1056,7 +1092,7 @@ struct mips_cpu_info {
+ /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
+ because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
+ instructions. */
+-#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
++#define ISA_HAS_LL_SC ((mips_isa >= 2 || TARGET_TAROKO) && !TARGET_MIPS16)
+ #define GENERATE_LL_SC \
+ (target_flags_explicit & MASK_LLSC \
+ ? TARGET_LLSC && !TARGET_MIPS16 \
+diff -rupN ./gcc.orig/gcc/config/mips/mips.md ./gcc.new/gcc/config/mips/mips.md
+--- a/gcc/config/mips/mips.md 2013-01-24 19:46:41.000000000 +0200
++++ b/gcc/config/mips/mips.md 2013-09-17 12:41:06.048912668 +0300
+@@ -64,6 +64,13 @@
+ sr71000
+ xlr
+ xlp
++ rlx4081
++ rlx4180
++ rlx4181
++ rlx4281
++ rlx5181
++ rlx5280
++ rlx5281
+ ])
+
+ (define_c_enum "unspec" [
+diff -rupN ./gcc.orig/gcc/config/mips/mips-tables.opt ./gcc.new/gcc/config/mips/mips-tables.opt
+--- a/gcc/config/mips/mips-tables.opt 2013-01-10 22:38:27.000000000 +0200
++++ b/gcc/config/mips/mips-tables.opt 2013-09-17 17:12:22.506481307 +0300
+@@ -624,3 +624,23 @@ Enum(mips_arch_opt_value) String(octeon2
+ EnumValue
+ Enum(mips_arch_opt_value) String(xlp) Value(85) Canonical
+
++EnumValue
++Enum(mips_arch_opt_value) String(rlx4081) Value(86) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx4180) Value(87) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx4181) Value(88) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx4281) Value(89) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx5181) Value(90) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx5280) Value(91) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx5281) Value(92) Canonical