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-rw-r--r--toolchain/binutils/patches/2.22/600-mips_no_dynamic_linking_sym.patch18
-rw-r--r--toolchain/binutils/patches/2.22/999_realtek_2_22.patch340
-rw-r--r--toolchain/gcc/patches/4.8-linaro/200-musl.patch31
-rw-r--r--toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch11
-rw-r--r--toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch2
-rw-r--r--toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch2
-rw-r--r--toolchain/gcc/patches/4.8-linaro/880-no_java_section.patch11
-rw-r--r--toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch4
-rw-r--r--toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch2
-rw-r--r--toolchain/gcc/patches/4.8-linaro/999_realtek.patch47
-rw-r--r--toolchain/gcc/patches/4.8.0/200-musl.patch13
-rw-r--r--toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch11
-rw-r--r--toolchain/gcc/patches/4.8.0/880-no_java_section.patch11
-rw-r--r--toolchain/gcc/patches/4.8.0/999_realtek.patch203
14 files changed, 436 insertions, 270 deletions
diff --git a/toolchain/binutils/patches/2.22/600-mips_no_dynamic_linking_sym.patch b/toolchain/binutils/patches/2.22/600-mips_no_dynamic_linking_sym.patch
new file mode 100644
index 000000000..29d769104
--- /dev/null
+++ b/toolchain/binutils/patches/2.22/600-mips_no_dynamic_linking_sym.patch
@@ -0,0 +1,18 @@
+--- a/bfd/elfxx-mips.c
++++ b/bfd/elfxx-mips.c
+@@ -7230,6 +7230,7 @@ _bfd_mips_elf_create_dynamic_sections (b
+
+ name = SGI_COMPAT (abfd) ? "_DYNAMIC_LINK" : "_DYNAMIC_LINKING";
+ bh = NULL;
++ if (0) {
+ if (!(_bfd_generic_link_add_one_symbol
+ (info, abfd, name, BSF_GLOBAL, bfd_abs_section_ptr, 0,
+ NULL, FALSE, get_elf_backend_data (abfd)->collect, &bh)))
+@@ -7242,6 +7243,7 @@ _bfd_mips_elf_create_dynamic_sections (b
+
+ if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
++ }
+
+ if (! mips_elf_hash_table (info)->use_rld_obj_head)
+ {
diff --git a/toolchain/binutils/patches/2.22/999_realtek_2_22.patch b/toolchain/binutils/patches/2.22/999_realtek_2_22.patch
index 0845b84d7..6f8e1a4bf 100644
--- a/toolchain/binutils/patches/2.22/999_realtek_2_22.patch
+++ b/toolchain/binutils/patches/2.22/999_realtek_2_22.patch
@@ -1,6 +1,25 @@
+diff -rupN ./bu.orig/bfd/archures.c ./bu.new/bfd/archures.c
+--- a/bfd/archures.c 2011-08-02 02:04:19.000000000 +0300
++++ b/bfd/archures.c 2013-10-19 16:23:46.289505726 +0300
+@@ -182,7 +182,14 @@ DESCRIPTION
+ .#define bfd_mach_mipsisa64 64
+ .#define bfd_mach_mipsisa64r2 65
+ .#define bfd_mach_mips_micromips 96
+-. bfd_arch_i386, {* Intel 386 *}
++.#define bfd_mach_mips_rlx4081 4081
++.#define bfd_mach_mips_rlx4180 4180
++.#define bfd_mach_mips_rlx4181 4181
++.#define bfd_mach_mips_rlx4281 4281
++.#define bfd_mach_mips_rlx5181 5181
++.#define bfd_mach_mips_rlx5280 5280
++.#define bfd_mach_mips_rlx5281 5281
++.#bfd_arch_i386, {* Intel 386 *}
+ .#define bfd_mach_i386_intel_syntax (1 << 0)
+ .#define bfd_mach_i386_i8086 (1 << 1)
+ .#define bfd_mach_i386_i386 (1 << 2)
diff -rupN ./bu.orig/bfd/bfd-in2.h ./bu.new/bfd/bfd-in2.h
--- a/bfd/bfd-in2.h 2011-09-16 04:15:18.000000000 +0300
-+++ b/bfd/bfd-in2.h 2013-09-26 20:51:04.437639632 +0300
++++ b/bfd/bfd-in2.h 2013-11-30 09:41:21.611855847 +0200
@@ -1889,6 +1889,13 @@ enum bfd_architecture
#define bfd_mach_mipsisa64 64
#define bfd_mach_mipsisa64r2 65
@@ -25,11 +44,12 @@ diff -rupN ./bu.orig/bfd/bfd-in2.h ./bu.new/bfd/bfd-in2.h
}
bfd_reloc_status_type;
-@@ -2780,6 +2788,16 @@ to compensate for the borrow when the lo
+@@ -2780,6 +2788,18 @@ to compensate for the borrow when the lo
/* MIPS16 low 16 bits. */
BFD_RELOC_MIPS16_LO16,
+/* MIPS16 TLS relocations */
++/*
+ BFD_RELOC_MIPS16_TLS_GD,
+ BFD_RELOC_MIPS16_TLS_LDM,
+ BFD_RELOC_MIPS16_TLS_DTPREL_HI16,
@@ -38,17 +58,18 @@ diff -rupN ./bu.orig/bfd/bfd-in2.h ./bu.new/bfd/bfd-in2.h
+ BFD_RELOC_MIPS16_TLS_TPREL_HI16,
+ BFD_RELOC_MIPS16_TLS_TPREL_LO16,
+ BFD_RELOC_RLX_OFF6A,
++*/
+
/* Relocation against a MIPS literal section. */
BFD_RELOC_MIPS_LITERAL,
BFD_RELOC_MICROMIPS_LITERAL,
diff -rupN ./bu.orig/bfd/cpu-mips.c ./bu.new/bfd/cpu-mips.c
--- a/bfd/cpu-mips.c 2011-07-24 17:20:05.000000000 +0300
-+++ b/bfd/cpu-mips.c 2013-10-14 20:42:12.869766152 +0300
-@@ -62,6 +62,13 @@ enum
++++ b/bfd/cpu-mips.c 2013-10-19 16:14:04.172826491 +0300
+@@ -60,6 +60,13 @@ mips_compatible (const bfd_arch_info_typ
+
+ enum
{
- I_mips3000,
- I_mips3900,
+ I_mips_rlx4081,
+ I_mips_rlx4180,
+ I_mips_rlx4181,
@@ -56,10 +77,10 @@ diff -rupN ./bu.orig/bfd/cpu-mips.c ./bu.new/bfd/cpu-mips.c
+ I_mips_rlx5181,
+ I_mips_rlx5280,
+ I_mips_rlx5281,
+ I_mips3000,
+ I_mips3900,
I_mips4000,
- I_mips4010,
- I_mips4100,
-@@ -94,7 +101,7 @@ enum
+@@ -94,13 +101,20 @@ enum
I_loongson_3a,
I_mipsocteon,
I_xlr,
@@ -68,10 +89,9 @@ diff -rupN ./bu.orig/bfd/cpu-mips.c ./bu.new/bfd/cpu-mips.c
};
#define NN(index) (&arch_info_struct[(index) + 1])
-@@ -103,6 +110,13 @@ static const bfd_arch_info_type arch_inf
+
+ static const bfd_arch_info_type arch_info_struct[] =
{
- N (32, 32, bfd_mach_mips3000, "mips:3000", FALSE, NN(I_mips3000)),
- N (32, 32, bfd_mach_mips3900, "mips:3900", FALSE, NN(I_mips3900)),
+ N (32, 32, bfd_mach_mips_rlx4081,"mips:rlx4081",FALSE, NN(I_mips_rlx4081)),
+ N (32, 32, bfd_mach_mips_rlx4180,"mips:rlx4180",FALSE, NN(I_mips_rlx4180)),
+ N (32, 32, bfd_mach_mips_rlx4181,"mips:rlx4181",FALSE, NN(I_mips_rlx4181)),
@@ -79,9 +99,9 @@ diff -rupN ./bu.orig/bfd/cpu-mips.c ./bu.new/bfd/cpu-mips.c
+ N (32, 32, bfd_mach_mips_rlx5181,"mips:rlx5181",FALSE, NN(I_mips_rlx5181)),
+ N (32, 32, bfd_mach_mips_rlx5280,"mips:rlx5280",FALSE, NN(I_mips_rlx5280)),
+ N (32, 32, bfd_mach_mips_rlx5281,"mips:rlx5281",FALSE, NN(I_mips_rlx5281)),
+ N (32, 32, bfd_mach_mips3000, "mips:3000", FALSE, NN(I_mips3000)),
+ N (32, 32, bfd_mach_mips3900, "mips:3900", FALSE, NN(I_mips3900)),
N (64, 64, bfd_mach_mips4000, "mips:4000", FALSE, NN(I_mips4000)),
- N (64, 64, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)),
- N (64, 64, bfd_mach_mips4100, "mips:4100", FALSE, NN(I_mips4100)),
@@ -135,7 +149,7 @@ static const bfd_arch_info_type arch_inf
N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
@@ -114,166 +134,44 @@ diff -rupN ./bu.orig/bfd/doc/bfd.texinfo ./bu.new/bfd/doc/bfd.texinfo
@bye
diff -rupN ./bu.orig/bfd/elf32-mips.c ./bu.new/bfd/elf32-mips.c
--- a/bfd/elf32-mips.c 2011-07-24 17:20:05.000000000 +0300
-+++ b/bfd/elf32-mips.c 2013-09-26 19:52:44.694112357 +0300
-@@ -717,6 +717,21 @@ static reloc_howto_type elf_mips_howto_t
++++ b/bfd/elf32-mips.c 2013-11-30 09:51:35.548540648 +0200
+@@ -717,6 +717,8 @@ static reloc_howto_type elf_mips_howto_t
0x0, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
+
-+ /* relocation added by dbb */
-+ HOWTO (R_RELOC_RLX_OFF6A, /* type */
-+ 3, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 10, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 6, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ NULL, /* special_function */
-+ "R_RELOC_RLX_OFF6A", /* name */
-+ TRUE, /* partial_inplace */
-+ 0x0000FFC0, /* src_mask */
-+ 0x0000FFC0, /* dst_mask */
-+ FALSE), /* pcrel_offset */
++
};
/* The reloc used for BFD_RELOC_CTOR when doing a 64 bit link. This
-@@ -830,6 +845,112 @@ static reloc_howto_type elf_mips16_howto
+@@ -830,6 +832,7 @@ static reloc_howto_type elf_mips16_howto
0x0000ffff, /* src_mask */
0x0000ffff, /* dst_mask */
FALSE), /* pcrel_offset */
+
-+ /* MIPS16 TLS general dynamic variable reference. */
-+ HOWTO (R_MIPS16_TLS_GD, /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ _bfd_mips_elf_generic_reloc, /* special_function */
-+ "R_MIPS16_TLS_GD", /* name */
-+ TRUE, /* partial_inplace */
-+ 0x0000ffff, /* src_mask */
-+ 0x0000ffff, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* MIPS16 TLS local dynamic variable reference. */
-+ HOWTO (R_MIPS16_TLS_LDM, /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ _bfd_mips_elf_generic_reloc, /* special_function */
-+ "R_MIPS16_TLS_LDM", /* name */
-+ TRUE, /* partial_inplace */
-+ 0x0000ffff, /* src_mask */
-+ 0x0000ffff, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* MIPS16 TLS local dynamic offset. */
-+ HOWTO (R_MIPS16_TLS_DTPREL_HI16, /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ _bfd_mips_elf_generic_reloc, /* special_function */
-+ "R_MIPS16_TLS_DTPREL_HI16", /* name */
-+ TRUE, /* partial_inplace */
-+ 0x0000ffff, /* src_mask */
-+ 0x0000ffff, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* MIPS16 TLS local dynamic offset. */
-+ HOWTO (R_MIPS16_TLS_DTPREL_LO16, /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ _bfd_mips_elf_generic_reloc, /* special_function */
-+ "R_MIPS16_TLS_DTPREL_LO16", /* name */
-+ TRUE, /* partial_inplace */
-+ 0x0000ffff, /* src_mask */
-+ 0x0000ffff, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* MIPS16 TLS thread pointer offset. */
-+ HOWTO (R_MIPS16_TLS_GOTTPREL, /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ _bfd_mips_elf_generic_reloc, /* special_function */
-+ "R_MIPS16_TLS_GOTTPREL", /* name */
-+ TRUE, /* partial_inplace */
-+ 0x0000ffff, /* src_mask */
-+ 0x0000ffff, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* MIPS16 TLS thread pointer offset. */
-+ HOWTO (R_MIPS16_TLS_TPREL_HI16, /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ _bfd_mips_elf_generic_reloc, /* special_function */
-+ "R_MIPS16_TLS_TPREL_HI16", /* name */
-+ TRUE, /* partial_inplace */
-+ 0x0000ffff, /* src_mask */
-+ 0x0000ffff, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* MIPS16 TLS thread pointer offset. */
-+ HOWTO (R_MIPS16_TLS_TPREL_LO16, /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ _bfd_mips_elf_generic_reloc, /* special_function */
-+ "R_MIPS16_TLS_TPREL_LO16", /* name */
-+ TRUE, /* partial_inplace */
-+ 0x0000ffff, /* src_mask */
-+ 0x0000ffff, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
};
static reloc_howto_type elf_micromips_howto_table_rel[] =
-@@ -1785,7 +1906,9 @@ static const struct elf_reloc_map mips_r
- { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 },
- { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 },
- { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 },
+@@ -1777,15 +1780,6 @@ static const struct elf_reloc_map mips_r
+ { BFD_RELOC_MIPS_TLS_DTPREL32, R_MIPS_TLS_DTPREL32 },
+ { BFD_RELOC_MIPS_TLS_DTPMOD64, R_MIPS_TLS_DTPMOD64 },
+ { BFD_RELOC_MIPS_TLS_DTPREL64, R_MIPS_TLS_DTPREL64 },
+- { BFD_RELOC_MIPS_TLS_GD, R_MIPS_TLS_GD },
+- { BFD_RELOC_MIPS_TLS_LDM, R_MIPS_TLS_LDM },
+- { BFD_RELOC_MIPS_TLS_DTPREL_HI16, R_MIPS_TLS_DTPREL_HI16 },
+- { BFD_RELOC_MIPS_TLS_DTPREL_LO16, R_MIPS_TLS_DTPREL_LO16 },
+- { BFD_RELOC_MIPS_TLS_GOTTPREL, R_MIPS_TLS_GOTTPREL },
+- { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 },
+- { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 },
+- { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 },
- { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }
-+ { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 },
-+ { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 },
-+ { BFD_RELOC_RLX_OFF6A, R_RELOC_RLX_OFF6A },
};
static const struct elf_reloc_map mips16_reloc_map[] =
-@@ -1796,6 +1919,16 @@ static const struct elf_reloc_map mips16
+@@ -1796,6 +1790,7 @@ static const struct elf_reloc_map mips16
{ BFD_RELOC_MIPS16_CALL16, R_MIPS16_CALL16 - R_MIPS16_min },
{ BFD_RELOC_MIPS16_HI16_S, R_MIPS16_HI16 - R_MIPS16_min },
{ BFD_RELOC_MIPS16_LO16, R_MIPS16_LO16 - R_MIPS16_min },
-+ { BFD_RELOC_MIPS16_TLS_GD, R_MIPS16_TLS_GD - R_MIPS16_min },
-+ { BFD_RELOC_MIPS16_TLS_LDM, R_MIPS16_TLS_LDM - R_MIPS16_min },
-+ { BFD_RELOC_MIPS16_TLS_DTPREL_HI16,
-+ R_MIPS16_TLS_DTPREL_HI16 - R_MIPS16_min },
-+ { BFD_RELOC_MIPS16_TLS_DTPREL_LO16,
-+ R_MIPS16_TLS_DTPREL_LO16 - R_MIPS16_min },
-+ { BFD_RELOC_MIPS16_TLS_GOTTPREL, R_MIPS16_TLS_GOTTPREL - R_MIPS16_min },
-+ { BFD_RELOC_MIPS16_TLS_TPREL_HI16, R_MIPS16_TLS_TPREL_HI16 - R_MIPS16_min },
-+ { BFD_RELOC_MIPS16_TLS_TPREL_LO16, R_MIPS16_TLS_TPREL_LO16 - R_MIPS16_min }
+
};
@@ -298,7 +196,7 @@ diff -rupN ./bu.orig/bfd/libbfd.h ./bu.new/bfd/libbfd.h
"BFD_RELOC_MICROMIPS_7_PCREL_S1",
diff -rupN ./bu.orig/bfd/reloc.c ./bu.new/bfd/reloc.c
--- a/bfd/reloc.c 2011-07-24 17:20:06.000000000 +0300
-+++ b/bfd/reloc.c 2013-10-14 13:51:07.800130671 +0300
++++ b/bfd/reloc.c 2013-11-30 09:41:26.098522661 +0200
@@ -52,6 +52,7 @@ SECTION
#include "bfd.h"
#include "bfdlink.h"
@@ -322,34 +220,9 @@ diff -rupN ./bu.orig/bfd/reloc.c ./bu.new/bfd/reloc.c
relocation >>= (bfd_vma) howto->rightshift;
/* Shift everything up to where it's going to be used. */
-@@ -2246,6 +2255,24 @@ ENUM
- ENUMDOC
- MIPS16 low 16 bits.
-
-+ ENUM
-+ BFD_RELOC_MIPS16_TLS_GD
-+ENUMX
-+ BFD_RELOC_MIPS16_TLS_LDM
-+ENUMX
-+ BFD_RELOC_MIPS16_TLS_DTPREL_HI16
-+ENUMX
-+ BFD_RELOC_MIPS16_TLS_DTPREL_LO16
-+ENUMX
-+ BFD_RELOC_MIPS16_TLS_GOTTPREL
-+ENUMX
-+ BFD_RELOC_MIPS16_TLS_TPREL_HI16
-+ENUMX
-+ BFD_RELOC_MIPS16_TLS_TPREL_LO16
-+ENUMDOC
-+ MIPS16 TLS relocations
-+
-+
- ENUM
- BFD_RELOC_MIPS_LITERAL
- ENUMX
diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
--- a/gas/config/tc-mips.c 2011-11-21 11:29:32.000000000 +0200
-+++ b/gas/config/tc-mips.c 2013-10-14 20:47:24.949783533 +0300
++++ b/gas/config/tc-mips.c 2013-11-30 10:05:30.081898864 +0200
@@ -104,6 +104,35 @@ static char *mips_regmask_frag;
#define ILLEGAL_REG (32)
@@ -1199,8 +1072,8 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
+ << OP_SH_OFFSET6A);
+ imm_expr.X_op = O_absent;
+ }
-+ else
-+ *imm_reloc = BFD_RELOC_RLX_OFF6A;
++ //else
++ // *imm_reloc = BFD_RELOC_RLX_OFF6A;
+ s = expr_end;
+ continue;
+
@@ -1411,12 +1284,12 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
}
/* Branch offsets have an implicit 0 in the lowest bit. */
-@@ -14040,7 +14787,14 @@ static const struct percent_op_match mip
+@@ -14040,7 +14787,15 @@ static const struct percent_op_match mip
{"%gprel", BFD_RELOC_MIPS16_GPREL},
{"%got", BFD_RELOC_MIPS16_GOT16},
{"%call16", BFD_RELOC_MIPS16_CALL16},
- {"%hi", BFD_RELOC_MIPS16_HI16_S}
-+ {"%hi", BFD_RELOC_MIPS16_HI16_S},
++ {"%hi", BFD_RELOC_MIPS16_HI16_S}/*,
+ {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
+ {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
+ {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
@@ -1424,10 +1297,11 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
+ {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
+ {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
+ {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
++ */
};
-@@ -14209,6 +14963,7 @@ enum options
+@@ -14209,6 +14964,7 @@ enum options
OPTION_MIPS64,
OPTION_MIPS32R2,
OPTION_MIPS64R2,
@@ -1435,7 +1309,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
OPTION_MIPS16,
OPTION_NO_MIPS16,
OPTION_MIPS3D,
-@@ -14285,6 +15040,9 @@ enum options
+@@ -14285,6 +15041,9 @@ enum options
OPTION_NO_PDR,
OPTION_MVXWORKS_PIC,
#endif /* OBJ_ELF */
@@ -1445,7 +1319,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
OPTION_END_OF_ENUM
};
-@@ -14396,6 +15154,9 @@ struct option md_longopts[] =
+@@ -14396,6 +15155,9 @@ struct option md_longopts[] =
{"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
{"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
#endif /* OBJ_ELF */
@@ -1455,7 +1329,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
{NULL, no_argument, NULL, 0}
};
-@@ -14431,6 +15192,18 @@ md_parse_option (int c, char *arg)
+@@ -14431,6 +15193,18 @@ md_parse_option (int c, char *arg)
mips_disable_float_construction = 1;
break;
@@ -1474,7 +1348,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
case OPTION_TRAP:
mips_trap = 1;
break;
-@@ -14509,6 +15282,9 @@ md_parse_option (int c, char *arg)
+@@ -14509,6 +15283,9 @@ md_parse_option (int c, char *arg)
mips_set_option_string (&mips_arch_string, arg);
break;
@@ -1484,7 +1358,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
case OPTION_M4650:
mips_set_option_string (&mips_arch_string, "4650");
mips_set_option_string (&mips_tune_string, "4650");
-@@ -15036,7 +15812,7 @@ mips_after_parse_args (void)
+@@ -15036,7 +15813,7 @@ mips_after_parse_args (void)
|| mips_abi == O32_ABI))
mips_32bitmode = 1;
@@ -1493,7 +1367,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
as_bad (_("trap exception not supported at ISA 1"));
/* If the selected architecture includes support for ASEs, enable
-@@ -15113,6 +15889,9 @@ mips_after_parse_args (void)
+@@ -15113,6 +15890,9 @@ mips_after_parse_args (void)
}
}
@@ -1503,7 +1377,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
void
mips_init_after_args (void)
{
-@@ -15369,6 +16148,8 @@ md_apply_fix (fixS *fixP, valueT *valP,
+@@ -15369,6 +16149,8 @@ md_apply_fix (fixS *fixP, valueT *valP,
case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
case BFD_RELOC_MIPS_TLS_GOTTPREL:
@@ -1512,24 +1386,26 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
case BFD_RELOC_MIPS_TLS_TPREL_HI16:
case BFD_RELOC_MIPS_TLS_TPREL_LO16:
case BFD_RELOC_MICROMIPS_TLS_GD:
-@@ -15378,6 +16159,13 @@ md_apply_fix (fixS *fixP, valueT *valP,
+@@ -15378,6 +16160,14 @@ md_apply_fix (fixS *fixP, valueT *valP,
case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
-+ case BFD_RELOC_MIPS16_TLS_GD:
++ /*case BFD_RELOC_MIPS16_TLS_GD:
+ case BFD_RELOC_MIPS16_TLS_LDM:
+ case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
+ case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
+ case BFD_RELOC_MIPS16_TLS_GOTTPREL:
+ case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
+ case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
++ */
S_SET_THREAD_LOCAL (fixP->fx_addsy);
/* fall through */
-@@ -15570,6 +16358,35 @@ md_apply_fix (fixS *fixP, valueT *valP,
+@@ -15570,6 +16360,36 @@ md_apply_fix (fixS *fixP, valueT *valP,
fixP->fx_done = 0;
break;
++/*
+ case BFD_RELOC_RLX_OFF6A:
+ if (fixP->fx_done)
+ {
@@ -1557,12 +1433,12 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
+ md_number_to_chars ((char *) buf, tmp_value, 4);
+ }
+ break;
-+
++*/
+
default:
internalError ();
}
-@@ -16552,7 +17369,8 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED)
+@@ -16552,7 +17372,8 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED)
use in DWARF debug information. */
static void
@@ -1572,7 +1448,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
{
expressionS ex;
char *p;
-@@ -16561,19 +17379,13 @@ s_dtprel_internal (size_t bytes)
+@@ -16561,19 +17382,13 @@ s_dtprel_internal (size_t bytes)
if (ex.X_op != O_symbol)
{
@@ -1594,7 +1470,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
demand_empty_rest_of_line ();
}
-@@ -16582,7 +17394,7 @@ s_dtprel_internal (size_t bytes)
+@@ -16582,7 +17397,7 @@ s_dtprel_internal (size_t bytes)
static void
s_dtprelword (int ignore ATTRIBUTE_UNUSED)
{
@@ -1603,7 +1479,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
}
/* Handle .dtpreldword. */
-@@ -16590,9 +17402,26 @@ s_dtprelword (int ignore ATTRIBUTE_UNUSE
+@@ -16590,9 +17405,26 @@ s_dtprelword (int ignore ATTRIBUTE_UNUSE
static void
s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
{
@@ -1631,7 +1507,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
code. It sets the offset to use in gp_rel relocations. */
-@@ -16996,6 +17825,9 @@ mips16_extended_frag (fragS *fragp, asec
+@@ -16996,6 +17828,9 @@ mips16_extended_frag (fragS *fragp, asec
{
mintiny = - (1 << (op->nbits - 1));
maxtiny = (1 << (op->nbits - 1)) - 1;
@@ -1641,7 +1517,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
}
sym_frag = symbol_get_frag (fragp->fr_symbol);
-@@ -17203,7 +18035,7 @@ relaxed_branch_length (fragS *fragp, ase
+@@ -17203,7 +18038,7 @@ relaxed_branch_length (fragS *fragp, ase
{
/* Additional space for PIC loading of target address. */
length += 8;
@@ -1650,7 +1526,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
/* Additional space for $at-stabilizing nop. */
length += 4;
}
-@@ -17809,7 +18641,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNU
+@@ -17809,7 +18644,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNU
md_number_to_chars ((char *) buf, insn, 4);
buf += 4;
@@ -1659,24 +1535,25 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
{
/* nop */
md_number_to_chars ((char *) buf, 0, 4);
-@@ -18911,6 +19743,16 @@ static const struct mips_cpu_info mips_c
- { "r2000", 0, ISA_MIPS1, CPU_R3000 },
- { "r3900", 0, ISA_MIPS1, CPU_R3900 },
+@@ -18906,6 +19741,17 @@ static const struct mips_cpu_info mips_c
+ { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
+ { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
++
+ /* RLX */
+ // trying to set isa to mips1
-+ { "rlx4081", 0, ISA_MIPS1, CPU_RLX4081 },
-+ { "rlx4180", 0, ISA_MIPS1, CPU_RLX4180 },
-+ { "rlx4181", 0, ISA_MIPS1, CPU_RLX4181 },
-+ { "rlx4281", 0, ISA_MIPS1, CPU_RLX4281 },
-+ { "rlx5181", 0, ISA_MIPS1, CPU_RLX5181 },
-+ { "rlx5280", 0, ISA_MIPS1, CPU_RLX5280 },
-+ { "rlx5281", 0, ISA_MIPS1, CPU_RLX5281 },
-+
- /* MIPS II */
- { "r6000", 0, ISA_MIPS2, CPU_R6000 },
-
-@@ -19078,7 +19920,13 @@ mips_matching_cpu_name_p (const char *ca
++ { "rlx4081", 0, ISA_MIPS1, CPU_R3000 },
++ { "rlx4180", 0, ISA_MIPS1, CPU_R3000 },
++ { "rlx4181", 0, ISA_MIPS1, CPU_R3000 },
++ { "rlx4281", 0, ISA_MIPS1, CPU_R3000 },
++ { "rlx5181", 0, ISA_MIPS1, CPU_R3000 },
++ { "rlx5280", 0, ISA_MIPS1, CPU_R3000 },
++ { "rlx5281", 0, ISA_MIPS1, CPU_R3000 },
++
+ /* MIPS I */
+ { "r3000", 0, ISA_MIPS1, CPU_R3000 },
+ { "r2000", 0, ISA_MIPS1, CPU_R3000 },
+@@ -19078,7 +19924,13 @@ mips_matching_cpu_name_p (const char *ca
/* If not, try comparing based on numerical designation alone.
See if GIVEN is an unadorned number, or 'r' followed by a number. */
if (TOLOWER (*given) == 'r')
@@ -1691,7 +1568,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
if (!ISDIGIT (*given))
return FALSE;
-@@ -19086,10 +19934,15 @@ mips_matching_cpu_name_p (const char *ca
+@@ -19086,10 +19938,15 @@ mips_matching_cpu_name_p (const char *ca
hoping to find a number there too. */
if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
canonical += 2;
@@ -1710,7 +1587,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
return mips_strict_matching_cpu_name_p (canonical, given);
}
-@@ -19353,3 +20206,69 @@ tc_mips_regname_to_dw2regnum (char *regn
+@@ -19353,3 +20210,68 @@ tc_mips_regname_to_dw2regnum (char *regn
return regnum;
}
@@ -1734,11 +1611,10 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
+ regno2 = regno1 + 1;
+
+#warning "Fix this"
-+/*ololo
-+ if (insn_uses_reg(insn2, regno1, MIPS_GR_REG) ||
-+ insn_uses_reg(insn2, regno2, MIPS_GR_REG))
++ //if (insn_uses_reg(insn2, regno1, MIPS_GR_REG) ||
++ // insn_uses_reg(insn2, regno2, MIPS_GR_REG))
+ return 1;
-+*/
++
+
+ return 0;
+}
@@ -1811,7 +1687,7 @@ diff -rupN ./bu.orig/include/elf/mips.h ./bu.new/include/elf/mips.h
RELOC_NUMBER (R_MIPS_JUMP_SLOT, 127)
diff -rupN ./bu.orig/include/opcode/mips.h ./bu.new/include/opcode/mips.h
--- a/include/opcode/mips.h 2011-08-09 18:20:03.000000000 +0300
-+++ b/include/opcode/mips.h 2013-09-26 21:45:55.694488685 +0300
++++ b/include/opcode/mips.h 2013-10-19 16:21:40.062836212 +0300
@@ -59,6 +59,42 @@
The general coprocessor instructions use COPZ. */
@@ -2019,13 +1895,13 @@ diff -rupN ./bu.orig/include/opcode/mips.h ./bu.new/include/opcode/mips.h
#define ISA_MIPS64R2 INSN_ISA64R2
+/* RLX ASE */
-+#define ISA_RLX4081 INSN_RLX4081
-+#define ISA_RLX4180 INSN_RLX4180
-+#define ISA_RLX4181 INSN_RLX4181
-+#define ISA_RLX4281 INSN_RLX4281
-+#define ISA_RLX5181 INSN_RLX5181
-+#define ISA_RLX5280 INSN_RLX5280
-+#define ISA_RLX5281 INSN_RLX5281
++#define ISA_RLX4081 INSN_ISA1
++#define ISA_RLX4180 INSN_ISA1
++#define ISA_RLX4181 INSN_ISA1
++#define ISA_RLX4281 INSN_ISA1
++#define ISA_RLX5181 INSN_ISA1
++#define ISA_RLX5280 INSN_ISA1
++#define ISA_RLX5281 INSN_ISA1
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
diff --git a/toolchain/gcc/patches/4.8-linaro/200-musl.patch b/toolchain/gcc/patches/4.8-linaro/200-musl.patch
index 8cf45eb61..3fe5a7eba 100644
--- a/toolchain/gcc/patches/4.8-linaro/200-musl.patch
+++ b/toolchain/gcc/patches/4.8-linaro/200-musl.patch
@@ -1,6 +1,6 @@
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
-@@ -549,7 +549,7 @@ case ${target} in
+@@ -550,7 +550,7 @@ case ${target} in
esac
# Common C libraries.
@@ -9,7 +9,7 @@
# Common parts for widely ported systems.
case ${target} in
-@@ -652,6 +652,9 @@ case ${target} in
+@@ -653,6 +653,9 @@ case ${target} in
*-*-*uclibc*)
tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC"
;;
@@ -34,7 +34,7 @@
#undef LINK_SPEC
--- a/gcc/config/i386/linux.h
+++ b/gcc/config/i386/linux.h
-@@ -21,3 +21,4 @@ along with GCC; see the file COPYING3.
+@@ -21,3 +21,4 @@ along with GCC; see the file COPYING3.
#define GNU_USER_LINK_EMULATION "elf_i386"
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
@@ -127,7 +127,7 @@
+Use musl C library
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
-@@ -18,3 +18,5 @@ along with GCC; see the file COPYING3.
+@@ -18,3 +18,5 @@ along with GCC; see the file COPYING3.
<http://www.gnu.org/licenses/>. */
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
@@ -135,7 +135,7 @@
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-mips.so.1"
--- a/gcc/config/rs6000/linux64.h
+++ b/gcc/config/rs6000/linux64.h
-@@ -364,17 +364,21 @@ extern int dot_symbols;
+@@ -354,17 +354,21 @@ extern int dot_symbols;
#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1"
#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
@@ -159,11 +159,11 @@
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64)
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
-
- #define LINK_OS_LINUX_SPEC32 "-m elf32ppclinux %{!shared: %{!static: \
+ #undef DEFAULT_ASM_ENDIAN
+ #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
-@@ -789,15 +789,18 @@ extern int fixuplabelno;
+@@ -778,15 +778,18 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEF
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
@@ -295,7 +295,7 @@
;;
--- a/gcc/config/mips/linux64.h
+++ b/gcc/config/mips/linux64.h
-@@ -27,6 +27,9 @@ along with GCC; see the file COPYING3.
+@@ -27,6 +27,9 @@ along with GCC; see the file COPYING3.
#define GLIBC_DYNAMIC_LINKERN32 "/lib32/ld.so.1"
#define UCLIBC_DYNAMIC_LINKERN32 "/lib32/ld-uClibc.so.0"
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
@@ -306,3 +306,16 @@
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \
- BIONIC_DYNAMIC_LINKERN32)
+ BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32)
+--- a/gcc/config/sparc/linux64.h 2013-09-10 10:02:45.663973856 +0100
++++ b/gcc/config/sparc/linux64.h 2013-09-10 10:03:17.871972435 +0100
+@@ -104,6 +104,9 @@
+ #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+ #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
+
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-sparc.so.1"
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-sparc.so.1"
++
+ #ifdef SPARC_BI_ARCH
+
+ #undef SUBTARGET_EXTRA_SPECS
+
diff --git a/toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch
index a3816a17f..33cf8add3 100644
--- a/toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch
+++ b/toolchain/gcc/patches/4.8-linaro/810-arm-softfloat-libgcc.patch
@@ -12,3 +12,14 @@
# Just for these, we omit the frame pointer since it makes such a big
# difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -55,8 +55,6 @@
+ %{shared:-lc} \
+ %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #define LINUX_TARGET_LINK_SPEC "%{h*} \
diff --git a/toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch b/toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch
index 4a77b86c1..ee3f60273 100644
--- a/toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch
+++ b/toolchain/gcc/patches/4.8-linaro/850-use_shared_libgcc.patch
@@ -1,6 +1,6 @@
--- a/gcc/config/arm/linux-eabi.h
+++ b/gcc/config/arm/linux-eabi.h
-@@ -114,10 +114,6 @@
+@@ -118,10 +118,6 @@
#define ENDFILE_SPEC \
LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)
diff --git a/toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch b/toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch
index d8c460a92..14e4fbdce 100644
--- a/toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch
+++ b/toolchain/gcc/patches/4.8-linaro/870-ppc_no_crtsavres.patch
@@ -1,6 +1,6 @@
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
-@@ -17653,7 +17653,7 @@ rs6000_savres_strategy (rs6000_stack_t *
+@@ -17664,7 +17664,7 @@ rs6000_savres_strategy (rs6000_stack_t *
/* Define cutoff for using out-of-line functions to save registers. */
if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
{
diff --git a/toolchain/gcc/patches/4.8-linaro/880-no_java_section.patch b/toolchain/gcc/patches/4.8-linaro/880-no_java_section.patch
new file mode 100644
index 000000000..def6c9f4a
--- /dev/null
+++ b/toolchain/gcc/patches/4.8-linaro/880-no_java_section.patch
@@ -0,0 +1,11 @@
+--- a/gcc/defaults.h
++++ b/gcc/defaults.h
+@@ -380,7 +380,7 @@ see the files COPYING3 and COPYING.RUNTI
+ /* If we have named section and we support weak symbols, then use the
+ .jcr section for recording java classes which need to be registered
+ at program start-up time. */
+-#if defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK
++#if 0 && defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK
+ #ifndef JCR_SECTION_NAME
+ #define JCR_SECTION_NAME ".jcr"
+ #endif
diff --git a/toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch b/toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch
index 3b37a3f8f..eb9a7c6c7 100644
--- a/toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch
+++ b/toolchain/gcc/patches/4.8-linaro/910-mbsd_multi.patch
@@ -209,7 +209,7 @@
-Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol
-Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol
-Wformat-security -Wformat-y2k @gol
-@@ -4808,6 +4808,22 @@ This option is only supported for C and
+@@ -4809,6 +4809,22 @@ This option is only supported for C and
@option{-Wall} and by @option{-Wpedantic}, which can be disabled with
@option{-Wno-pointer-sign}.
@@ -232,7 +232,7 @@
@item -Wstack-protector
@opindex Wstack-protector
@opindex Wno-stack-protector
-@@ -6919,7 +6935,7 @@ so, the first branch is redirected to ei
+@@ -6920,7 +6936,7 @@ so, the first branch is redirected to ei
second branch or a point immediately following it, depending on whether
the condition is known to be true or false.
diff --git a/toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch
index 4baa96693..8698eda5f 100644
--- a/toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch
+++ b/toolchain/gcc/patches/4.8-linaro/920-specs_nonfatal_getenv.patch
@@ -1,6 +1,6 @@
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
-@@ -8003,7 +8003,10 @@ getenv_spec_function (int argc, const ch
+@@ -8004,7 +8004,10 @@ getenv_spec_function (int argc, const ch
value = getenv (argv[0]);
if (!value)
diff --git a/toolchain/gcc/patches/4.8-linaro/999_realtek.patch b/toolchain/gcc/patches/4.8-linaro/999_realtek.patch
index c5a0998a7..5f7e01660 100644
--- a/toolchain/gcc/patches/4.8-linaro/999_realtek.patch
+++ b/toolchain/gcc/patches/4.8-linaro/999_realtek.patch
@@ -85,7 +85,7 @@ diff -rupN ./gcc.orig/gcc/common.opt ./gcc.new/gcc/common.opt
diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
--- a/gcc/config/mips/mips.c 2013-02-19 02:04:49.000000000 +0200
-+++ b/gcc/config/mips/mips.c 2013-10-14 20:23:06.143036336 +0300
++++ b/gcc/config/mips/mips.c 2013-11-09 06:12:14.396962114 +0200
@@ -56,6 +56,9 @@ along with GCC; see the file COPYING3.
#include "target-globals.h"
#include "opts.h"
@@ -96,10 +96,10 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
#define UNSPEC_ADDRESS_P(X) \
(GET_CODE (X) == UNSPEC \
-@@ -925,6 +928,27 @@ static const struct mips_rtx_cost_data
- 1, /* branch_cost */
- 4 /* memory_latency */
- },
+@@ -731,6 +734,27 @@ static const struct mips_rtx_cost_data m
+ /* Costs to use when optimizing for speed, indexed by processor. */
+ static const struct mips_rtx_cost_data
+ mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
+ { /* RLX */
+ DEFAULT_COSTS
+ },
@@ -121,9 +121,9 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
+ { /* RLX */
+ DEFAULT_COSTS
+ },
- { /* R6000 */
- COSTS_N_INSNS (3), /* fp_add */
- COSTS_N_INSNS (5), /* fp_mult_sf */
+ { /* R3000 */
+ COSTS_N_INSNS (2), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
@@ -1212,13 +1236,62 @@ mips_far_type_p (const_tree type)
static bool
mips_mips16_decl_p (const_tree decl)
@@ -501,11 +501,11 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
bool
diff -rupN ./gcc.orig/gcc/config/mips/mips-cpus.def ./gcc.new/gcc/config/mips/mips-cpus.def
--- a/gcc/config/mips/mips-cpus.def 2013-01-10 22:38:27.000000000 +0200
-+++ b/gcc/config/mips/mips-cpus.def 2013-10-14 19:45:36.929578308 +0300
-@@ -53,6 +53,14 @@ MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0
- MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
- MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
++++ b/gcc/config/mips/mips-cpus.def 2013-10-19 16:36:32.376188609 +0300
+@@ -49,6 +49,13 @@ MIPS_CPU ("mips64", PROCESSOR_5KC, 64, P
+ MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY)
+ /* MIPS I processors. */
+MIPS_CPU ("rlx4081", PROCESSOR_RLX4081, 1, 0)
+MIPS_CPU ("rlx4180", PROCESSOR_RLX4180, 1, 0)
+MIPS_CPU ("rlx4181", PROCESSOR_RLX4181, 1, 0)
@@ -513,10 +513,9 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips-cpus.def ./gcc.new/gcc/config/mips/mi
+MIPS_CPU ("rlx5181", PROCESSOR_RLX5181, 1, 0)
+MIPS_CPU ("rlx5280", PROCESSOR_RLX5280, 1, 0)
+MIPS_CPU ("rlx5281", PROCESSOR_RLX5281, 1, 0)
-+
- /* MIPS II processors. */
- MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
-
+ MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
+ MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
+ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h
--- a/gcc/config/mips/mips.h 2013-01-10 22:38:27.000000000 +0200
+++ b/gcc/config/mips/mips.h 2013-10-14 19:57:12.512949903 +0300
@@ -732,11 +731,11 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h
diff -rupN ./gcc.orig/gcc/config/mips/mips.md ./gcc.new/gcc/config/mips/mips.md
--- a/gcc/config/mips/mips.md 2013-01-24 19:46:41.000000000 +0200
-+++ b/gcc/config/mips/mips.md 2013-10-14 19:46:13.179580218 +0300
-@@ -59,6 +59,13 @@
- r8000
- r9000
- r10000
++++ b/gcc/config/mips/mips.md 2013-10-19 16:36:20.482855340 +0300
+@@ -22,6 +22,13 @@
+ ;; <http://www.gnu.org/licenses/>.
+
+ (define_enum "processor" [
+ rlx4081
+ rlx4180
+ rlx4181
@@ -744,9 +743,9 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.md ./gcc.new/gcc/config/mips/mips.md
+ rlx5181
+ rlx5280
+ rlx5281
- sb1
- sb1a
- sr71000
+ r3000
+ 4kc
+ 4kp
@@ -679,11 +686,17 @@
;; Can the instruction be put into a delay slot?
diff --git a/toolchain/gcc/patches/4.8.0/200-musl.patch b/toolchain/gcc/patches/4.8.0/200-musl.patch
index 94a45e217..2e6df47e4 100644
--- a/toolchain/gcc/patches/4.8.0/200-musl.patch
+++ b/toolchain/gcc/patches/4.8.0/200-musl.patch
@@ -306,3 +306,16 @@
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \
- BIONIC_DYNAMIC_LINKERN32)
+ BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32)
+--- a/gcc/config/sparc/linux64.h 2013-09-10 10:02:45.663973856 +0100
++++ b/gcc/config/sparc/linux64.h 2013-09-10 10:03:17.871972435 +0100
+@@ -104,6 +104,9 @@
+ #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+ #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
+
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-sparc.so.1"
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-sparc.so.1"
++
+ #ifdef SPARC_BI_ARCH
+
+ #undef SUBTARGET_EXTRA_SPECS
+
diff --git a/toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch
index a3816a17f..33cf8add3 100644
--- a/toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch
+++ b/toolchain/gcc/patches/4.8.0/810-arm-softfloat-libgcc.patch
@@ -12,3 +12,14 @@
# Just for these, we omit the frame pointer since it makes such a big
# difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -55,8 +55,6 @@
+ %{shared:-lc} \
+ %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #define LINUX_TARGET_LINK_SPEC "%{h*} \
diff --git a/toolchain/gcc/patches/4.8.0/880-no_java_section.patch b/toolchain/gcc/patches/4.8.0/880-no_java_section.patch
new file mode 100644
index 000000000..def6c9f4a
--- /dev/null
+++ b/toolchain/gcc/patches/4.8.0/880-no_java_section.patch
@@ -0,0 +1,11 @@
+--- a/gcc/defaults.h
++++ b/gcc/defaults.h
+@@ -380,7 +380,7 @@ see the files COPYING3 and COPYING.RUNTI
+ /* If we have named section and we support weak symbols, then use the
+ .jcr section for recording java classes which need to be registered
+ at program start-up time. */
+-#if defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK
++#if 0 && defined (TARGET_ASM_NAMED_SECTION) && SUPPORTS_WEAK
+ #ifndef JCR_SECTION_NAME
+ #define JCR_SECTION_NAME ".jcr"
+ #endif
diff --git a/toolchain/gcc/patches/4.8.0/999_realtek.patch b/toolchain/gcc/patches/4.8.0/999_realtek.patch
new file mode 100644
index 000000000..e0f5bc237
--- /dev/null
+++ b/toolchain/gcc/patches/4.8.0/999_realtek.patch
@@ -0,0 +1,203 @@
+diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c
+--- a/gcc/config/mips/mips.c 2013-02-19 02:04:49.000000000 +0200
++++ b/gcc/config/mips/mips.c 2013-09-17 15:56:40.036229582 +0300
+@@ -1121,6 +1121,27 @@ static const struct mips_rtx_cost_data
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
++ },
++ { /* RLX */
++ DEFAULT_COSTS
+ }
+ };
+
+@@ -12794,6 +12815,9 @@ mips_issue_rate (void)
+ case PROCESSOR_R9000:
+ case PROCESSOR_OCTEON:
+ case PROCESSOR_OCTEON2:
++ case PROCESSOR_RLX5280:
++ case PROCESSOR_RLX5281:
++ case PROCESSOR_RLX4281:
+ return 2;
+
+ case PROCESSOR_SB1:
+diff -rupN ./gcc.orig/gcc/config/mips/mips-cpus.def ./gcc.new/gcc/config/mips/mips-cpus.def
+--- a/gcc/config/mips/mips-cpus.def 2013-01-10 22:38:27.000000000 +0200
++++ b/gcc/config/mips/mips-cpus.def 2013-09-17 17:10:08.249807200 +0300
+@@ -52,6 +52,14 @@ MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65,
+ MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
+ MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
+ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
++MIPS_CPU ("rlx4081", PROCESSOR_RLX4081, 1, 0)
++MIPS_CPU ("rlx4180", PROCESSOR_RLX4180, 1, 0)
++MIPS_CPU ("rlx4181", PROCESSOR_RLX4181, 1, 0)
++MIPS_CPU ("rlx4281", PROCESSOR_RLX4281, 1, 0)
++MIPS_CPU ("rlx5181", PROCESSOR_RLX5181, 1, 0)
++MIPS_CPU ("rlx5280", PROCESSOR_RLX5280, 1, 0)
++MIPS_CPU ("rlx5281", PROCESSOR_RLX5281, 1, 0)
++
+
+ /* MIPS II processors. */
+ MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
+diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h
+--- a/gcc/config/mips/mips.h 2013-01-10 22:38:27.000000000 +0200
++++ b/gcc/config/mips/mips.h 2013-09-17 16:38:07.036367401 +0300
+@@ -222,6 +222,32 @@ struct mips_cpu_info {
+ #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
+ #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
+
++#define TARGET_RLX4081 (mips_arch == PROCESSOR_RLX4081)
++#define TARGET_RLX4180 (mips_arch == PROCESSOR_RLX4180)
++#define TARGET_RLX4181 (mips_arch == PROCESSOR_RLX4181)
++#define TARGET_RLX4281 (mips_arch == PROCESSOR_RLX4281)
++#define TARGET_RLX5181 (mips_arch == PROCESSOR_RLX5181)
++#define TARGET_RLX5280 (mips_arch == PROCESSOR_RLX5280)
++#define TARGET_RLX5281 (mips_arch == PROCESSOR_RLX5281)
++
++/* All RLX processor */
++#define TARGET_RLX (TARGET_RLX4081 || TARGET_RLX4180 \
++ || TARGET_RLX4181 || TARGET_RLX4281 || TARGET_RLX5181 \
++ || TARGET_RLX5280 || TARGET_RLX5281)
++
++/* RLX processor which supports Radiax instructions */
++#define TARGET_RLX_RAD (TARGET_RLX5181 || TARGET_RLX5280 || TARGET_RLX5281)
++#define TARGET_RLX_NORAD (TARGET_RLX && !TARGET_RLX_RAD)
++
++/* RLX processor which supprts gpr-interlocks */
++#define TARGET_RLX_INTERLOCK (TARGET_RLX4281 || TARGET_RLX5280 || TARGET_RLX5281)
++#define TARGET_RLX_NO_INTERLOCK (TARGET_RLX && !TARGET_RLX_INTERLOCK)
++
++#define TARGET_RLX1 (TARGET_RLX4181 || TARGET_RLX4281 || TARGET_RLX5181 \
++ || TARGET_RLX5280 || TARGET_RLX5281)
++
++#define TARGET_TAROKO (TARGET_RLX4281 || TARGET_RLX5281)
++
+ /* Scheduling target defines. */
+ #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
+ #define TUNE_24K (mips_tune == PROCESSOR_24KC \
+@@ -695,7 +721,7 @@ struct mips_cpu_info {
+
+ #define MIPS_ISA_LEVEL_SPEC \
+ "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
+- %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
++ %{march=mips1|march=r2000|march=r3000|march=r3900|march=rlx4081|march=rlx4180|march=rlx4181|march=rlx5181|march=rlx5280|march=rlx5281:-mips1} \
+ %{march=mips2|march=r6000:-mips2} \
+ %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
+ %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
+@@ -838,7 +864,14 @@ struct mips_cpu_info {
+
+ /* ISA has the integer conditional move instructions introduced in mips4 and
+ ST Loongson 2E/2F. */
+-#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
++#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
++ || TARGET_LOONGSON_2EF \
++ || ((TARGET_RLX5280 \
++ || TARGET_RLX5181 \
++ || TARGET_RLX5281 \
++ || TARGET_RLX4181 \
++ || TARGET_RLX4281) \
++ && !TARGET_MIPS16))
+
+ /* ISA has LDC1 and SDC1. */
+ #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
+@@ -1012,7 +1045,8 @@ struct mips_cpu_info {
+ and "addiu $4,$4,1". */
+ #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
+ && !TARGET_MIPS3900 \
+- && !TARGET_MIPS16)
++ && !TARGET_MIPS16 \
++ && !TARGET_RLX_INTERLOCK)
+
+ /* Likewise mtc1 and mfc1. */
+ #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
+@@ -1039,7 +1073,8 @@ struct mips_cpu_info {
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2 \
+ || TARGET_MIPS5500 \
+- || TARGET_LOONGSON_2EF)
++ || TARGET_LOONGSON_2EF \
++ || TARGET_RLX)
+
+ /* ISA includes synci, jr.hb and jalr.hb. */
+ #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
+@@ -1047,7 +1082,8 @@ struct mips_cpu_info {
+ && !TARGET_MIPS16)
+
+ /* ISA includes sync. */
+-#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
++#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900 || TARGET_TAROKO) \
++ && !TARGET_MIPS16)
+ #define GENERATE_SYNC \
+ (target_flags_explicit & MASK_LLSC \
+ ? TARGET_LLSC && !TARGET_MIPS16 \
+@@ -1056,7 +1092,7 @@ struct mips_cpu_info {
+ /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
+ because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
+ instructions. */
+-#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
++#define ISA_HAS_LL_SC ((mips_isa >= 2 || TARGET_TAROKO) && !TARGET_MIPS16)
+ #define GENERATE_LL_SC \
+ (target_flags_explicit & MASK_LLSC \
+ ? TARGET_LLSC && !TARGET_MIPS16 \
+diff -rupN ./gcc.orig/gcc/config/mips/mips.md ./gcc.new/gcc/config/mips/mips.md
+--- a/gcc/config/mips/mips.md 2013-01-24 19:46:41.000000000 +0200
++++ b/gcc/config/mips/mips.md 2013-09-17 12:41:06.048912668 +0300
+@@ -64,6 +64,13 @@
+ sr71000
+ xlr
+ xlp
++ rlx4081
++ rlx4180
++ rlx4181
++ rlx4281
++ rlx5181
++ rlx5280
++ rlx5281
+ ])
+
+ (define_c_enum "unspec" [
+diff -rupN ./gcc.orig/gcc/config/mips/mips-tables.opt ./gcc.new/gcc/config/mips/mips-tables.opt
+--- a/gcc/config/mips/mips-tables.opt 2013-01-10 22:38:27.000000000 +0200
++++ b/gcc/config/mips/mips-tables.opt 2013-09-17 17:12:22.506481307 +0300
+@@ -624,3 +624,23 @@ Enum(mips_arch_opt_value) String(octeon2
+ EnumValue
+ Enum(mips_arch_opt_value) String(xlp) Value(85) Canonical
+
++EnumValue
++Enum(mips_arch_opt_value) String(rlx4081) Value(86) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx4180) Value(87) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx4181) Value(88) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx4281) Value(89) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx5181) Value(90) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx5280) Value(91) Canonical
++
++EnumValue
++Enum(mips_arch_opt_value) String(rlx5281) Value(92) Canonical