path: root/toolchain/binutils/patches/2.22/999_realtek_2_22.patch

diff -rupN ./bu.orig/bfd/archures.c ./bu.new/bfd/archures.c
--- a/bfd/archures.c	2011-08-02 02:04:19.000000000 +0300
+++ b/bfd/archures.c	2013-10-19 16:23:46.289505726 +0300
@@ -182,7 +182,14 @@ DESCRIPTION
 .#define bfd_mach_mipsisa64             64
 .#define bfd_mach_mipsisa64r2           65
 .#define bfd_mach_mips_micromips        96
-.  bfd_arch_i386,      {* Intel 386 *}
+.#define bfd_mach_mips_rlx4081          4081
+.#define bfd_mach_mips_rlx4180          4180
+.#define bfd_mach_mips_rlx4181          4181
+.#define bfd_mach_mips_rlx4281          4281
+.#define bfd_mach_mips_rlx5181          5181
+.#define bfd_mach_mips_rlx5280          5280
+.#define bfd_mach_mips_rlx5281          5281
+.#bfd_arch_i386,      {* Intel 386 *}
 .#define bfd_mach_i386_intel_syntax	(1 << 0)
 .#define bfd_mach_i386_i8086		(1 << 1)
 .#define bfd_mach_i386_i386		(1 << 2)
diff -rupN ./bu.orig/bfd/bfd-in2.h ./bu.new/bfd/bfd-in2.h
--- a/bfd/bfd-in2.h	2011-09-16 04:15:18.000000000 +0300
+++ b/bfd/bfd-in2.h	2013-11-30 09:41:21.611855847 +0200
@@ -1889,6 +1889,13 @@ enum bfd_architecture
 #define bfd_mach_mipsisa64             64
 #define bfd_mach_mipsisa64r2           65
 #define bfd_mach_mips_micromips        96
+#define bfd_mach_mips_rlx4081          4081
+#define bfd_mach_mips_rlx4180          4180
+#define bfd_mach_mips_rlx4181          4181
+#define bfd_mach_mips_rlx4281          4281
+#define bfd_mach_mips_rlx5181          5181
+#define bfd_mach_mips_rlx5280          5280
+#define bfd_mach_mips_rlx5281          5281
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_intel_syntax     (1 << 0)
 #define bfd_mach_i386_i8086            (1 << 1)
@@ -2239,7 +2246,8 @@ typedef enum bfd_reloc_status
      generated only when linking i960 coff files with i960 b.out
      symbols.  If this type is returned, the error_message argument
      to bfd_perform_relocation will be set.  */
-  bfd_reloc_dangerous
+  bfd_reloc_dangerous,
+  bfd_reloc_notmultipleof8_ltw
  }
  bfd_reloc_status_type;
 
@@ -2780,6 +2788,18 @@ to compensate for the borrow when the lo
 /* MIPS16 low 16 bits.  */
   BFD_RELOC_MIPS16_LO16,
 
+/* MIPS16 TLS relocations  */
+/*
+  BFD_RELOC_MIPS16_TLS_GD,
+  BFD_RELOC_MIPS16_TLS_LDM,
+  BFD_RELOC_MIPS16_TLS_DTPREL_HI16,
+  BFD_RELOC_MIPS16_TLS_DTPREL_LO16,
+  BFD_RELOC_MIPS16_TLS_GOTTPREL,
+  BFD_RELOC_MIPS16_TLS_TPREL_HI16,
+  BFD_RELOC_MIPS16_TLS_TPREL_LO16,
+  BFD_RELOC_RLX_OFF6A,
+*/
+
 /* Relocation against a MIPS literal section.  */
   BFD_RELOC_MIPS_LITERAL,
   BFD_RELOC_MICROMIPS_LITERAL,
diff -rupN ./bu.orig/bfd/cpu-mips.c ./bu.new/bfd/cpu-mips.c
--- a/bfd/cpu-mips.c	2011-07-24 17:20:05.000000000 +0300
+++ b/bfd/cpu-mips.c	2013-10-19 16:14:04.172826491 +0300
@@ -60,6 +60,13 @@ mips_compatible (const bfd_arch_info_typ
 
 enum
 {
+  I_mips_rlx4081,
+  I_mips_rlx4180,
+  I_mips_rlx4181,
+  I_mips_rlx4281,
+  I_mips_rlx5181,
+  I_mips_rlx5280,
+  I_mips_rlx5281,
   I_mips3000,
   I_mips3900,
   I_mips4000,
@@ -94,13 +101,20 @@ enum
   I_loongson_3a,
   I_mipsocteon,
   I_xlr,
-  I_micromips
+  I_micromips,
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
 
 static const bfd_arch_info_type arch_info_struct[] =
 {
+  N (32, 32, bfd_mach_mips_rlx4081,"mips:rlx4081",FALSE, NN(I_mips_rlx4081)),
+  N (32, 32, bfd_mach_mips_rlx4180,"mips:rlx4180",FALSE, NN(I_mips_rlx4180)),
+  N (32, 32, bfd_mach_mips_rlx4181,"mips:rlx4181",FALSE, NN(I_mips_rlx4181)),
+  N (32, 32, bfd_mach_mips_rlx4281,"mips:rlx4281",FALSE, NN(I_mips_rlx4281)),
+  N (32, 32, bfd_mach_mips_rlx5181,"mips:rlx5181",FALSE, NN(I_mips_rlx5181)),
+  N (32, 32, bfd_mach_mips_rlx5280,"mips:rlx5280",FALSE, NN(I_mips_rlx5280)),
+  N (32, 32, bfd_mach_mips_rlx5281,"mips:rlx5281",FALSE, NN(I_mips_rlx5281)),  
   N (32, 32, bfd_mach_mips3000, "mips:3000",      FALSE, NN(I_mips3000)),
   N (32, 32, bfd_mach_mips3900, "mips:3900",      FALSE, NN(I_mips3900)),
   N (64, 64, bfd_mach_mips4000, "mips:4000",      FALSE, NN(I_mips4000)),
@@ -135,7 +149,7 @@ static const bfd_arch_info_type arch_inf
   N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a",       FALSE, NN(I_loongson_3a)),
   N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, NN(I_mipsocteon)),
   N (64, 64, bfd_mach_mips_xlr, "mips:xlr",       FALSE, NN(I_xlr)),
-  N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
+  N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0),
 };
 
 /* The default architecture is mips:3000, but with a machine number of
diff -rupN ./bu.orig/bfd/doc/bfd.texinfo ./bu.new/bfd/doc/bfd.texinfo
--- a/bfd/doc/bfd.texinfo	2010-10-28 14:40:25.000000000 +0300
+++ b/bfd/doc/bfd.texinfo	2013-10-11 16:20:58.349499163 +0300
@@ -322,7 +322,7 @@ All of BFD lives in one directory.
 @printindex cp
 
 @tex
-% I think something like @colophon should be in texinfo.  In the
+% I think something like @@colophon should be in texinfo.  In the
 % meantime:
 \long\def\colophon{\hbox to0pt{}\vfill
 \centerline{The body of this manual is set in}
@@ -333,7 +333,7 @@ All of BFD lives in one directory.
 \centerline{{\sl\fontname\tensl\/}}
 \centerline{are used for emphasis.}\vfill}
 \page\colophon
-% Blame: doc@cygnus.com, 28mar91.
+% Blame: doc@@cygnus.com, 28mar91.
 @end tex
 
 @bye
diff -rupN ./bu.orig/bfd/elf32-mips.c ./bu.new/bfd/elf32-mips.c
--- a/bfd/elf32-mips.c	2011-07-24 17:20:05.000000000 +0300
+++ b/bfd/elf32-mips.c	2013-11-30 09:51:35.548540648 +0200
@@ -717,6 +717,8 @@ static reloc_howto_type elf_mips_howto_t
 	 0x0,			/* src_mask */
 	 0xffffffff,		/* dst_mask */
 	 FALSE),		/* pcrel_offset */
+
+
 };
 
 /* The reloc used for BFD_RELOC_CTOR when doing a 64 bit link.  This
@@ -830,6 +832,7 @@ static reloc_howto_type elf_mips16_howto
 	 0x0000ffff,		/* src_mask */
 	 0x0000ffff,	        /* dst_mask */
 	 FALSE),		/* pcrel_offset */
+
 };
 
 static reloc_howto_type elf_micromips_howto_table_rel[] =
@@ -1777,15 +1780,6 @@ static const struct elf_reloc_map mips_r
   { BFD_RELOC_MIPS_TLS_DTPREL32, R_MIPS_TLS_DTPREL32 },
   { BFD_RELOC_MIPS_TLS_DTPMOD64, R_MIPS_TLS_DTPMOD64 },
   { BFD_RELOC_MIPS_TLS_DTPREL64, R_MIPS_TLS_DTPREL64 },
-  { BFD_RELOC_MIPS_TLS_GD, R_MIPS_TLS_GD },
-  { BFD_RELOC_MIPS_TLS_LDM, R_MIPS_TLS_LDM },
-  { BFD_RELOC_MIPS_TLS_DTPREL_HI16, R_MIPS_TLS_DTPREL_HI16 },
-  { BFD_RELOC_MIPS_TLS_DTPREL_LO16, R_MIPS_TLS_DTPREL_LO16 },
-  { BFD_RELOC_MIPS_TLS_GOTTPREL, R_MIPS_TLS_GOTTPREL },
-  { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 },
-  { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 },
-  { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 },
-  { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }
 };
 
 static const struct elf_reloc_map mips16_reloc_map[] =
@@ -1796,6 +1790,7 @@ static const struct elf_reloc_map mips16
   { BFD_RELOC_MIPS16_CALL16, R_MIPS16_CALL16 - R_MIPS16_min },
   { BFD_RELOC_MIPS16_HI16_S, R_MIPS16_HI16 - R_MIPS16_min },
   { BFD_RELOC_MIPS16_LO16, R_MIPS16_LO16 - R_MIPS16_min },
+
 };
 
 static const struct elf_reloc_map micromips_reloc_map[] =
diff -rupN ./bu.orig/bfd/libbfd.h ./bu.new/bfd/libbfd.h
--- a/bfd/libbfd.h	2011-08-17 03:39:39.000000000 +0300
+++ b/bfd/libbfd.h	2013-09-26 20:01:45.170808974 +0300
@@ -1086,6 +1086,14 @@ static const char *const bfd_reloc_code_
   "BFD_RELOC_MIPS16_HI16",
   "BFD_RELOC_MIPS16_HI16_S",
   "BFD_RELOC_MIPS16_LO16",
+  "BFD_RELOC_MIPS16_TLS_GD",
+  "BFD_RELOC_MIPS16_TLS_LDM",
+  "BFD_RELOC_MIPS16_TLS_DTPREL_HI16",
+  "BFD_RELOC_MIPS16_TLS_DTPREL_LO16",
+  "BFD_RELOC_MIPS16_TLS_GOTTPREL",
+  "BFD_RELOC_MIPS16_TLS_TPREL_HI16",
+  "BFD_RELOC_MIPS16_TLS_TPREL_LO16",
+  "BFD_RELOC_RLX_OFF6A",
   "BFD_RELOC_MIPS_LITERAL",
   "BFD_RELOC_MICROMIPS_LITERAL",
   "BFD_RELOC_MICROMIPS_7_PCREL_S1",
diff -rupN ./bu.orig/bfd/reloc.c ./bu.new/bfd/reloc.c
--- a/bfd/reloc.c	2011-07-24 17:20:06.000000000 +0300
+++ b/bfd/reloc.c	2013-11-30 09:41:26.098522661 +0200
@@ -52,6 +52,7 @@ SECTION
 #include "bfd.h"
 #include "bfdlink.h"
 #include "libbfd.h"
+#include "elf/mips.h"
 /*
 DOCDD
 INODE
@@ -833,6 +834,14 @@ space consuming.  For each target:
      }
      */
 
+  /* R_RELOC_RLX_OFF6A: used in ltw instruction */
+  if (howto->type == R_RELOC_RLX_OFF6A)
+  {
+    if ((relocation % 8) != 0)
+      return bfd_reloc_notmultipleof8_ltw;
+  }
+
+
   relocation >>= (bfd_vma) howto->rightshift;
 
   /* Shift everything up to where it's going to be used.  */
diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c
--- a/gas/config/tc-mips.c	2011-11-21 11:29:32.000000000 +0200
+++ b/gas/config/tc-mips.c	2013-11-30 10:05:30.081898864 +0200
@@ -104,6 +104,35 @@ static char *mips_regmask_frag;
 
 #define ILLEGAL_REG (32)
 
+/* 2006-11-28 tonywu: add radiax alias name translation */
+#define M0L      1
+#define M0H      2
+#define M0       3
+#define M1L      5
+#define M1H      6
+#define M1       7
+#define M2L      9
+#define M2H     10
+#define M2      11
+#define M3L     13
+#define M3H     14
+#define M3      15
+#define ESTATUS  0
+#define ECAUSE   1
+#define INTVEC   2
+#define CBS0     0
+#define CBS1     1
+#define CBS2     2
+#define CBE0     4
+#define CBE1     5
+#define CBE2     6
+#define LPS0    16
+#define LPE0    17
+#define LPC0    18
+#define MMD     24
+/* 2006-11-28 tonywu: add radiax alias name translation */
+
+
 #define AT  mips_opts.at
 
 /* Allow override of standard little-endian ECOFF format.  */
@@ -299,6 +328,8 @@ static struct mips_set_options mips_opts
   /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
 };
 
+static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0, 0};
+
 /* These variables are filled in with the masks of registers used.
    The object format code reads them and puts them in the appropriate
    place.  */
@@ -362,6 +393,10 @@ static int file_ase_dspr2;
 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2		\
 			        || mips_opts.isa == ISA_MIPS64R2)
 
+/* True if ISA supports RLX */
+#define ISA_IS_RLX ((mips_opts.isa & INSN_RLX_MASK) != 0)
+
+
 /* True if -mmt was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mt;
@@ -521,6 +556,7 @@ static int mips_32bitmode = 0;
    || mips_opts.isa == ISA_MIPS32R2                   \
    || mips_opts.isa == ISA_MIPS64                     \
    || mips_opts.isa == ISA_MIPS64R2                   \
+   || ISA_IS_RLX                                      \
    || mips_opts.arch == CPU_R4010                     \
    || mips_opts.arch == CPU_R10000                    \
    || mips_opts.arch == CPU_R12000                    \
@@ -531,16 +567,27 @@ static int mips_32bitmode = 0;
    || mips_opts.micromips                             \
    )
 
+/* Whether the processor support dual-issue. */
+#define dual_issue                      \
+  (mips_opts.arch == CPU_RLX4281        \
+   || mips_opts.arch == CPU_RLX5280     \
+   || mips_opts.arch == CPU_RLX5281     \
+  )
+
 /* Whether the processor uses hardware interlocks to protect reads
    from the GPRs after they are loaded from memory, and thus does not
    require nops to be inserted.  This applies to instructions marked
    INSN_LOAD_MEMORY_DELAY.  These nops are only required at MIPS ISA
    level I and microMIPS mode instructions are always interlocked.  */
-#define gpr_interlocks                                \
-  (mips_opts.isa != ISA_MIPS1                         \
-   || mips_opts.arch == CPU_R3900                     \
-   || mips_opts.micromips                             \
-   )
+#define gpr_interlocks                  \
+  ((mips_opts.isa != ISA_MIPS1          \
+   && (!ISA_IS_RLX                      \
+     || mips_opts.arch == CPU_RLX4281   \
+     || mips_opts.arch == CPU_RLX5280   \
+     || mips_opts.arch == CPU_RLX5281)) \
+   || mips_opts.arch == CPU_R3900       \
+   || mips_opts.micromips               \
+  )
 
 /* Whether the processor uses hardware interlocks to avoid delays
    required by coprocessor instructions, and thus does not require
@@ -553,6 +600,13 @@ static int mips_32bitmode = 0;
 /* Itbl support may require additional care here.  */
 #define cop_interlocks                                \
   ((mips_opts.isa != ISA_MIPS1                        \
+     && (!ISA_IS_RLX                                   \
+     || mips_opts.arch == CPU_RLX4180                 \
+     || mips_opts.arch == CPU_RLX4181                 \
+     || mips_opts.arch == CPU_RLX4281                 \
+     || mips_opts.arch == CPU_RLX5181                 \
+     || mips_opts.arch == CPU_RLX5280                 \
+     || mips_opts.arch == CPU_RLX5281)                \
     && mips_opts.isa != ISA_MIPS2                     \
     && mips_opts.isa != ISA_MIPS3)                    \
    || mips_opts.arch == CPU_R4300                     \
@@ -601,6 +655,16 @@ static int mips_big_got = 0;
    instructions.  */
 static int mips_trap = 0;
 
+/* 1 if we should avoid put load in branch delay slot */
+static int fix_bdsl = 1;
+
+/* 1 if we want to warn for possible load-use in branch & jump delay slot */
+static int warn_possible_load_use = 0;
+
+/* 1 if we want to warn for missing delay slot at the end of noreorder section */
+static int warn_missing_delay_slot = 0;
+
+
 /* 1 if double width floating point constants should not be constructed
    by assembling two single width halves into two single width floating
    point registers which just happen to alias the double width destination
@@ -1352,6 +1416,8 @@ static void s_cprestore (int);
 static void s_cpreturn (int);
 static void s_dtprelword (int);
 static void s_dtpreldword (int);
+static void s_tprelword (int);
+static void s_tpreldword (int);
 static void s_gpvalue (int);
 static void s_gpword (int);
 static void s_gpdword (int);
@@ -1373,6 +1439,14 @@ static int validate_mips_insn (const str
 static int validate_micromips_insn (const struct mips_opcode *);
 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
+static inline int rlx_nops_for_new_insn(const struct mips_cl_insn *, const struct mips_cl_insn *);
+static inline int rlx_is_tword_use(const struct mips_cl_insn *, const struct mips_cl_insn *);
+static inline int rlx_is_insn_swappable(const struct mips_cl_insn *, const struct mips_cl_insn *);
+
+/* raise warning for load-use case (for processors without gpr-interlocks). */
+static void rlx_warn_load_use (struct mips_cl_insn *, struct mips_cl_insn *, char *, int);
+/* raise warning for bdsl at noreorder section (for bug of taroko < 1.3) */
+static void rlx_warn_bdsl (const struct mips_cl_insn *);
 
 /* Table and functions used to map between CPU/ISA names, and
    ISA levels, and CPU numbers.  */
@@ -1436,6 +1510,8 @@ static const pseudo_typeS mips_pseudo_ta
   {"gpdword", s_gpdword, 0},
   {"cpadd", s_cpadd, 0},
   {"insn", s_insn, 0},
+  {"tprelword", s_tprelword, 0},
+  {"tpreldword", s_tpreldword, 0},
 
   /* Relatively generic pseudo-ops that happen to be used on MIPS
      chips.  */
@@ -1836,7 +1912,8 @@ struct regname {
   unsigned int num;
 };
 
-#define RTYPE_MASK	0x1ff00
+//#define RTYPE_MASK	0x1ff00
+#define RTYPE_MASK	0x5ff00
 #define RTYPE_NUM	0x00100
 #define RTYPE_FPU	0x00200
 #define RTYPE_FCC	0x00400
@@ -1848,6 +1925,7 @@ struct regname {
 #define RTYPE_CCC	0x10000
 #define RNUM_MASK	0x000ff
 #define RWARN		0x80000
+#define RTYPE_RAD	0x40000
 
 #define GENERIC_REGISTER_NUMBERS \
     {"$0",	RTYPE_NUM | 0},  \
@@ -2039,8 +2117,37 @@ struct regname {
     {"$ac2",	RTYPE_ACC | 2}, \
     {"$ac3",	RTYPE_ACC | 3}
 
+#define RLX_RADIAX_REGISTER_NAMES \
+    {"$m0l", RTYPE_RAD | 1},      \
+    {"$m0h", RTYPE_RAD | 2},      \
+    {"$m0",  RTYPE_RAD | 3},      \
+    {"$m1l", RTYPE_RAD | 5},      \
+    {"$m1h", RTYPE_RAD | 6},      \
+    {"$m1",  RTYPE_RAD | 7},      \
+    {"$m2l", RTYPE_RAD | 9},      \
+    {"$m2h", RTYPE_RAD | 10},     \
+    {"$m2",  RTYPE_RAD | 11},     \
+    {"$m3l", RTYPE_RAD | 13},     \
+    {"$m3h", RTYPE_RAD | 14},     \
+    {"$m3",  RTYPE_RAD | 15},     \
+    {"$estatus", RTYPE_RAD | 0},  \
+    {"$ecause",  RTYPE_RAD | 1},  \
+    {"$intvec",  RTYPE_RAD | 2},  \
+    {"$cbs0",  RTYPE_RAD | 0},    \
+    {"$cbs1",  RTYPE_RAD | 1},    \
+    {"$cbs2",  RTYPE_RAD | 2},    \
+    {"$cbe0",  RTYPE_RAD | 4},    \
+    {"$cbe1",  RTYPE_RAD | 5},    \
+    {"$cbe2",  RTYPE_RAD | 6},    \
+    {"$lps0",  RTYPE_RAD | 16},   \
+    {"$lpe0",  RTYPE_RAD | 17},   \
+    {"$lpc0",  RTYPE_RAD | 18},   \
+    {"$mmd",   RTYPE_RAD | 24}
+
+
 static const struct regname reg_names[] = {
   GENERIC_REGISTER_NUMBERS,
+  RLX_RADIAX_REGISTER_NAMES,
   FPU_REGISTER_NAMES,
   FPU_CONDITION_CODE_NAMES,
   COPROC_CONDITION_CODE_NAMES,
@@ -2727,6 +2834,67 @@ fixup_has_matching_lo_p (fixS *fixp)
 	  && fixp->fx_offset == fixp->fx_next->fx_offset);
 }
 
+static void
+rlx_warn_load_use (struct mips_cl_insn *insn1,
+        struct mips_cl_insn *insn2,
+        char *file, int line)
+{
+    unsigned long prev_pinfo, pinfo;
+    unsigned int wrt, rd;
+    const unsigned read_mask[2] = { INSN_READ_RAD_T, INSN_READ_RAD_S };
+    int i;
+
+
+    prev_pinfo = insn1->insn_mo->pinfo;
+    pinfo = insn2->insn_mo->pinfo;
+
+    if (gpr_interlocks || mips_opts.mips16
+        || !mips_opts.noreorder
+        || !(prev_pinfo & INSN_LOAD_MEMORY_DELAY))
+      return;
+
+    know (prev_pinfo & INSN_WRITE_GPR_T);
+    wrt = EXTRACT_OPERAND (mips_opts.micromips, RT, *insn1);
+
+    /* check RT & RS */
+    for (i = 0; i < 2; ++i) {
+        if ((pinfo & read_mask[i]) == 0) continue;
+
+        if (i == 0)
+            rd = EXTRACT_OPERAND(mips_opts.micromips, RT, *insn2);
+        else
+            rd = EXTRACT_OPERAND(mips_opts.micromips, RS, *insn2);
+
+        if (wrt == rd) {
+            as_warn_where (file, line, "LOAD-USE: regno=%d", wrt);
+            /* tword load & tword use instructions */
+            if ((insn1->insn_mo->pinfo2 & INSN2_TWORD_LOAD)
+                && (insn2->insn_mo->pinfo2 & INSN2_TWORD_USE))
+                as_warn_where (file, line, "LOAD-USE: regno=%d", wrt + 1);
+        }
+        /* tword load & use, check WR_t + 1 */
+        else if ((insn1->insn_mo->pinfo2 & INSN2_TWORD_LOAD) && (wrt + 1 == rd))
+            as_warn_where (file, line, "LOAD-USE: regno=%d", rd);
+        /* load & tword use, check RD_t + 1 */
+        else if ((insn2->insn_mo->pinfo2 & INSN2_TWORD_USE) && (wrt == rd + 1))
+            as_warn_where (file, line, "LOAD-USE: regno=%d", wrt);
+    }
+}
+/* 2010-08-06 tonywu: redo load-delay slot check */
+
+static void
+rlx_check_noreorder_insns (struct mips_cl_insn *ip)
+{
+    char *file;
+    unsigned line;
+    /* get current file & line */
+    as_where(&file, &line);
+    if (fix_bdsl)
+      rlx_warn_bdsl (ip);
+    rlx_warn_load_use (history, ip, file, line);
+}
+
+
 /* This function returns true if modifying a register requires a
    delay.  */
 
@@ -2992,9 +3160,9 @@ gpr_read_mask (const struct mips_cl_insn
     {
       if (pinfo2 & INSN2_READ_GPR_D)
 	mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
-      if (pinfo & INSN_READ_GPR_T)
+      if (pinfo & INSN_READ_RAD_T)
 	mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
-      if (pinfo & INSN_READ_GPR_S)
+      if (pinfo & INSN_READ_RAD_S)
 	mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
       if (pinfo2 & INSN2_READ_GP)
 	mask |= 1 << GP;
@@ -3057,9 +3225,9 @@ gpr_write_mask (const struct mips_cl_ins
     }
   else
     {
-      if (pinfo & INSN_WRITE_GPR_D)
+      if (pinfo & INSN_WRITE_RAD_D)
 	mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
-      if (pinfo & INSN_WRITE_GPR_T)
+      if (pinfo & INSN_WRITE_RAD_T)
 	mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
       if (pinfo & INSN_WRITE_GPR_S)
 	mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
@@ -3251,6 +3419,11 @@ insns_between (const struct mips_cl_insn
 	  || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
 	{
 	  know (pinfo1 & INSN_WRITE_GPR_T);
+          /* 2006-10-16 tonywu: fix lt nop bug */
+          if (ISA_IS_RLX && rlx_is_tword_use(insn1, insn2))
+            return 1; 
+          /* 2006-10-16 tonywu: fix lt nop bug */
+
 	  if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
 	    return 1;
 	}
@@ -3303,8 +3476,10 @@ insns_between (const struct mips_cl_insn
     }
 
 #undef INSN2_USES_GPR
-
-  return 0;
+	if (ISA_IS_RLX)
+		return rlx_nops_for_new_insn(insn1, insn2);
+	else
+		return 0;
 }
 
 /* Return the number of nops that would be needed to work around the
@@ -3576,6 +3751,186 @@ nops_for_insn (int ignore, const struct
   return nops;
 }
 
+static int
+rlx_check_regnum(char **ps)
+{
+  int regno;
+  char *s;
+
+  s = *ps;
+
+  regno = 32;
+  if (s[0] == '$') 
+    { 
+      if (ISDIGIT (s[1])) 
+        { 
+          regno = 0; 
+          ++s;
+          do {
+            regno *= 10;
+            regno += *s - '0';
+            ++s;
+          }
+          while (ISDIGIT (*s));
+
+          /* 2006-11-28 tonywu: add radiax alias name */
+        }
+      else
+        {
+          if (s[1] == 'm' && s[2] == '0' && s[3] == 'l')
+            {
+              s += 4;
+              regno = M0L;
+            } 
+          else if (s[1] == 'm' && s[2] == '0' && s[3] == 'h')
+            {
+              s += 4;
+              regno = M0H;
+            } 
+          else if (s[1] == 'm' && s[2] == '0')
+            {
+              s += 3;
+              regno = M0;
+            } 
+          else if (s[1] == 'm' && s[2] == '1' && s[3] == 'l')
+            {
+              s += 4;
+              regno = M1L;
+            } 
+          else if (s[1] == 'm' && s[2] == '1' && s[3] == 'h')
+            {
+              s += 4;
+              regno = M1H;
+            } 
+          else if (s[1] == 'm' && s[2] == '1')
+            {
+              s += 3;
+              regno = M1;
+            } 
+          else if (s[1] == 'm' && s[2] == '2' && s[3] == 'l')
+            {
+              s += 4;
+              regno = M2L;
+            } 
+          else if (s[1] == 'm' && s[2] == '2' && s[3] == 'h')
+            {
+              s += 4;
+              regno = M2H;
+            } 
+          else if (s[1] == 'm' && s[2] == '2')
+            {
+              s += 3;
+              regno = M2;
+            } 
+          else if (s[1] == 'm' && s[2] == '3' && s[3] == 'l')
+            {
+              s += 4;
+              regno = M3L;
+            } 
+          else if (s[1] == 'm' && s[2] == '3' && s[3] == 'h')
+            {
+              s += 4;
+              regno = M3H;
+            } 
+          else if (s[1] == 'm' && s[2] == '3')
+            {
+              s += 3;
+              regno = M3;
+            } 
+          else if (s[1] == 'c' && s[2] == 'b' && s[3] == 's' && s[4] == '0') 
+            { 
+              s += 5; 
+              regno = CBS0; 
+            }
+          else if (s[1] == 'c' && s[2] == 'b' && s[3] == 's' && s[4] == '1')
+            { 
+              s += 5; 
+              regno = CBS1; 
+            } 
+          else if (s[1] == 'c' && s[2] == 'b' && s[3] == 's' && s[4] == '2') 
+            { 
+              s += 5; 
+              regno = CBS2; 
+            } 
+          else if (s[1] == 'c' && s[2] == 'b' && s[3] == 'e' && s[4] == '0') 
+            { 
+              s += 5; 
+              regno = CBE0;
+            } 
+          else if (s[1] == 'c' && s[2] == 'b' && s[3] == 'e' && s[4] == '1') 
+            { 
+              s += 5; 
+              regno = CBE1; 
+            } 
+          else if (s[1] == 'c' && s[2] == 'b' && s[3] == 'e' && s[4] == '2') 
+            {
+              s += 5; 
+              regno = CBE2;
+            } 
+          else if (s[1] == 'l' && s[2] == 'p' && s[3] == 's' && s[4] == '0') 
+            { 
+              s += 5; 
+              regno = LPS0; 
+            } 
+          else if (s[1] == 'l' && s[2] == 'p' && s[3] == 'e' && s[4] == '0') 
+            { 
+              s += 5; 
+              regno = LPE0; 
+            } 
+          else if (s[1] == 'l' && s[2] == 'p' && s[3] == 'c' && s[4] == '0') 
+            { 
+              s += 5; 
+              regno = LPC0; 
+            } 
+          else if (s[1] == 'm' && s[2] == 'm' && s[3] == 'd')
+            { 
+              s += 4; 
+              regno = MMD; 
+            } 
+          else if (s[1] == 'e' && s[2] == 's' && s[3] == 't' && s[4] == 'a' && 
+                   s[5] == 't' && s[6] == 'u' && s[7] == 's') 
+            { 
+              s += 8; 
+              regno = ESTATUS; 
+            } 
+          else if (s[1] == 'e' && s[2] == 'c' && s[3] == 'a' && 
+                   s[4] == 'u' && s[5] == 's' && s[6] == 'e') 
+            { 
+              s += 7; 
+              regno = ECAUSE; 
+            } 
+          else if (s[1] == 'i' && s[2] == 'n' && s[3] == 't' && 
+                   s[4] == 'v' && s[5] == 'e' && s[6] == 'c') 
+            { 
+              s += 7; 
+              regno = INTVEC; 
+            } 
+        } 
+    }
+
+  *ps = s;
+  return regno;
+}
+
+/* 2006-01-09 tonywu: fix branch delay slot filling bug */
+static inline int
+rlx_is_insn_swappable(const struct mips_cl_insn *history,
+                      const struct mips_cl_insn *insn)
+{
+  int swappable = 1;
+
+  if (rlx_is_tword_use(history,insn))
+    swappable = 0;
+
+  if (fix_bdsl == 1
+      && ((history->insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) != 0
+          || mips_opts.mips16))
+    swappable = 0;
+
+  return swappable;
+}
+
+
 /* The variable arguments provide NUM_INSNS extra instructions that
    might be added to HIST.  Return the largest number of nops that
    would be needed after the extended sequence, ignoring hazards
@@ -3753,6 +4108,9 @@ can_swap_branch_p (struct mips_cl_insn *
      target of the branch.  */
   if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
     return FALSE;
+  
+  if (ISA_IS_RLX && ! rlx_is_insn_swappable(history, ip) )
+     return FALSE;
 
   /* If the branch reads a register that the previous
      instruction sets, we can not swap.  */
@@ -4809,7 +5167,7 @@ macro_build (expressionS *ep, const char
 	 warning later on.  */
       if (strcmp (fmt, amo->args) == 0
 	  && amo->pinfo != INSN_MACRO
-	  && is_opcode_valid (amo)
+	//  && is_opcode_valid (amo)
 	  && is_size_valid (amo))
 	{
 	  if (is_delay_slot_valid (amo))
@@ -5105,6 +5463,8 @@ mips16_macro_build (expressionS *ep, con
   bfd_reloc_code_real_type r[3]
     = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
 
+  //mips16_ext = FALSE;
+
   mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
   gas_assert (mo);
   gas_assert (strcmp (name, mo->name) == 0);
@@ -8764,7 +9124,7 @@ macro (struct mips_cl_insn *ip)
       s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
       if (strcmp (s, ".lit8") == 0)
 	{
-	  if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+	  if ((mips_opts.isa != ISA_MIPS1 && !ISA_IS_RLX) || mips_opts.micromips)
 	    {
 	      macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
 			   BFD_RELOC_MIPS_LITERAL, mips_gp_register);
@@ -8787,7 +9147,7 @@ macro (struct mips_cl_insn *ip)
 	      macro_build_lui (&offset_expr, AT);
 	    }
 
-	  if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+	  if ((mips_opts.isa != ISA_MIPS1 && !ISA_IS_RLX) || mips_opts.micromips)
 	    {
 	      macro_build (&offset_expr, "ldc1", "T,o(b)",
 			   treg, BFD_RELOC_LO16, AT);
@@ -8804,8 +9164,8 @@ macro (struct mips_cl_insn *ip)
       r = BFD_RELOC_LO16;
     dob:
       gas_assert (!mips_opts.micromips);
-      gas_assert (mips_opts.isa == ISA_MIPS1);
-      macro_build (&offset_expr, "lwc1", "T,o(b)",
+      gas_assert (mips_opts.isa == ISA_MIPS1|| ISA_IS_RLX);
+      macro_build (&offset_expr, "if (mips_opts.isa != ISA_MIPS1)lwc1", "T,o(b)",
 		   target_big_endian ? treg + 1 : treg, r, breg);
       /* FIXME: A possible overflow which I don't know how to deal
 	 with.  */
@@ -8816,7 +9176,7 @@ macro (struct mips_cl_insn *ip)
 
     case M_S_DOB:
       gas_assert (!mips_opts.micromips);
-      gas_assert (mips_opts.isa == ISA_MIPS1);
+      gas_assert (mips_opts.isa == ISA_MIPS1 || ISA_IS_RLX);
       /* Even on a big endian machine $fn comes before $fn+1.  We have
 	 to adjust when storing to memory.  */
       macro_build (&offset_expr, "swc1", "T,o(b)",
@@ -8842,7 +9202,7 @@ macro (struct mips_cl_insn *ip)
       /* Itbl support may require additional care here.  */
       coproc = 1;
       fmt = "T,o(b)";
-      if (mips_opts.isa != ISA_MIPS1)
+      if (mips_opts.isa != ISA_MIPS1 && ! ISA_IS_RLX)
 	{
 	  s = "ldc1";
 	  goto ld_st;
@@ -8855,7 +9215,7 @@ macro (struct mips_cl_insn *ip)
       /* Itbl support may require additional care here.  */
       coproc = 1;
       fmt = "T,o(b)";
-      if (mips_opts.isa != ISA_MIPS1)
+      if (mips_opts.isa != ISA_MIPS1 && ! ISA_IS_RLX)
 	{
 	  s = "sdc1";
 	  goto ld_st;
@@ -9731,7 +10091,7 @@ macro (struct mips_cl_insn *ip)
     case M_TRUNCWS:
     case M_TRUNCWD:
       gas_assert (!mips_opts.micromips);
-      gas_assert (mips_opts.isa == ISA_MIPS1);
+      gas_assert (mips_opts.isa == ISA_MIPS1 || ISA_IS_RLX);
       used_at = 1;
       sreg = (ip->insn_opcode >> 11) & 0x1f;	/* floating reg */
       dreg = (ip->insn_opcode >> 06) & 0x1f;	/* floating reg */
@@ -10299,6 +10659,39 @@ validate_mips_insn (const struct mips_op
       case '\\': USE_BITS (OP_MASK_3BITPOS,	OP_SH_3BITPOS);	break;
       case '~': USE_BITS (OP_MASK_OFFSET12,	OP_SH_OFFSET12); break;
       case 'g': USE_BITS (OP_MASK_RD,		OP_SH_RD);	break;
+      /* 2006-01-04 tonywu: merged from 2.14 to 2.16 */ 
+      case '#': 
+       switch (c = *p++) 
+         { 
+           /* dbb: new instructions support */ 
+         case '`': USE_BITS (OP_MASK_EVENREG, OP_SH_EVENREG); break; 
+         case '~': USE_BITS (OP_MASK_IMMIDATE88, OP_SH_IMMIDATE88); break;
+         case '#': USE_BITS (OP_MASK_IMMIDATE74, OP_SH_IMMIDATE74); break; 
+         case '@': USE_BITS (OP_MASK_IMMIDATE6b, OP_SH_IMMIDATE6b); break; 
+         case '-': USE_BITS (OP_MASK_OFFSET6A, OP_SH_OFFSET6A); break; 
+           /* dbb: new instructions support */
+           /* DVR taro: modified for supporting audio engine instructions */ 
+         case '$': USE_BITS (OP_MASK_IMMIDATEa6, OP_SH_IMMIDATEa6); break; 
+           /* DVR taro: modified for supporting audio engine instructions */ 
+           /* DVR jacky: modified for supporting video engine instructions */ 
+         case '&': USE_BITS (OP_MASK_IMMIDATE6A, OP_SH_IMMIDATE6A); break; 
+         case '=': USE_BITS (OP_MASK_IMMIDATE8A, OP_SH_IMMIDATE8A); break; 
+           /* DVR jacky: modified for supporting video engine instructions */ 
+           /* 2008-07-08 tonywu: add for taroko processor */
+         case 'H': USE_BITS (OP_MASK_RLX_SEL, OP_SH_RLX_SEL); break;
+         case 'I': USE_BITS (OP_MASK_RLX_STYPE, OP_SH_RLX_STYPE); break;
+         case 'd': USE_BITS (OP_MASK_RD,         OP_SH_RD); p++; break;
+         case 's': USE_BITS (OP_MASK_RS,         OP_SH_RS); p++; break;
+         case 't': USE_BITS (OP_MASK_RT,         OP_SH_RT); p++; break;
+         case 'u': USE_BITS (OP_MASK_RD,         OP_SH_RD); break;
+         case 'k': USE_BITS (OP_MASK_RD,         OP_SH_RD); break;
+         /* 2008-07-08 tonywu: add for taroko processor */
+         default: 
+           as_bad (_("internal: bad rlx opcode (unknown operand type `#%c'): %s %s"), 
+                   c, opc->name, opc->args);
+           return 0;
+         }
+       break;
       default:
 	as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
 		c, opc->name, opc->args);
@@ -10583,6 +10976,7 @@ mips_ip (char *str, struct mips_cl_insn
   char *s;
   const char *args;
   char c = 0;
+  char t = 0;
   struct mips_opcode *insn;
   char *argsStart;
   unsigned int regno;
@@ -10598,6 +10992,7 @@ mips_ip (char *str, struct mips_cl_insn
   unsigned int rtype;
   char *dot;
   long end;
+  int multipletype;
 
   insn_error = NULL;
 
@@ -13160,12 +13555,13 @@ mips16_ip (char *str, struct mips_cl_ins
   unsigned int lastregno = 0;
   char *s_reset;
   size_t i;
+  int multipletype; 
 
   insn_error = NULL;
 
   forced_insn_length = 0;
 
-  for (s = str; ISLOWER (*s); ++s)
+  for (s = str; ISLOWER (*s) || *s == '0' ; ++s)
     ;
   switch (*s)
     {
@@ -13250,6 +13646,7 @@ mips16_ip (char *str, struct mips_cl_ins
       for (args = insn->args; 1; ++args)
 	{
 	  int c;
+	  int t;
 
 	  if (*s == ' ')
 	    ++s;
@@ -13811,8 +14208,355 @@ mips16_ip (char *str, struct mips_cl_ins
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
-
-	    default:
+              /* dbb: modified for supporting radiax instructions */ 
+            case '#': 
+              switch (*++args) 
+                { 
+                case 'd': 
+                case 's': 
+                case 't': 
+                  s_reset = s; 
+                  regno = rlx_check_regnum(&s);
+
+                  c = *args;
+                  t = *++args;
+
+                  switch (t)
+                    {
+                    case '1': /* m0(3), m1(7), m2(11), m3(15) */ 
+                      if (regno <= 0 || regno > 15 || (regno & 3) != 3) 
+                        as_bad (_("RADIAX: illegal register (%d) in %s type d%c"), 
+                                regno, str, t); 
+                      break;
+
+                    case '2': /* m0l, m0h, m0 ~ m3l, m3h, m3 */ 
+                      if (regno <= 0 || regno > 15 || (regno & 3) == 0) 
+                        as_bad (_("RADIAX: illegal register (%d) in %s type d%c"), 
+                                regno, str, t); 
+                      break;
+
+                    case '3': /* m0l, m0h, ~ m3l, m3h */ 
+                      if (regno <= 0 || regno > 15 
+                          || (regno & 3) == 0 
+                          || (regno & 3) == 3) 
+                        as_bad (_("RADIAX: illegal register (%d) in %s type d%c"), 
+                                regno, str, t); 
+                      break; 
+                    case '4': /* LXC0 registers */ 
+                      if (regno > 31) 
+                        as_bad (_("RLX: illegal register (%d) in %s type d%c"), 
+                                regno, str, t); 
+                      break;
+
+                    default: 
+                      as_bad (_("RLX: illegal register type d%c in %s"), t, str); 
+                      break; 
+                    }
+
+                  switch (c) 
+                    { 
+                    case 'd': INSERT_OPERAND (mips_opts.micromips,RD, *ip, regno); break; 
+                    case 's': INSERT_OPERAND (mips_opts.micromips,RS, *ip, regno); break; 
+                    case 't': INSERT_OPERAND (mips_opts.micromips,RT, *ip, regno); break; 
+                    }
+
+                  lastregno = regno; 
+                  continue;
+
+                case 'u': 
+                case 'k': 
+                  s_reset = s; 
+                  regno = rlx_check_regnum(&s);
+
+                  /* 2006-11-28 tonywu: add radiax alias name */ 
+                  c = *args;
+
+                  /* Now that we have assembled one operand, we use the args string 
+                   * to figure out where it goes in the instruction.  */ 
+                  if (regno == 32) 
+                    as_bad (_("RADIAX: illegal register (%d) in %s"), regno, str);
+
+                  switch (c) 
+                    { 
+                    case 'u': INSERT_OPERAND (mips_opts.micromips,RD, *ip, regno); break; 
+                    case 'k': INSERT_OPERAND (mips_opts.micromips,RD, *ip, regno); break; 
+                    }
+
+                  lastregno = regno;
+                  continue; 
+
+                  /* DVR taro: modified for supporting audio engine instructions */
+                case '$':    /* 6 bits immediate from 0 to 32,used in AE (OP_*_IMMIDATEa6) */ 
+                  my_getExpression (&imm_expr, s);
+                  check_absolute_expr (ip, &imm_expr);
+                  if (imm_expr.X_add_number > 32 || imm_expr.X_add_number < 0)
+                    as_bad (_("(%lu) is out of range 0-32"),
+                           (unsigned long) imm_expr.X_add_number);
+
+                  ip->insn_opcode |= ( (imm_expr.X_add_number & OP_MASK_IMMIDATEa6) 
+                                       << OP_SH_IMMIDATEa6);
+
+                  imm_expr.X_op = O_absent;
+                  s = expr_end;
+                  continue;
+
+                  /* DVR taro: modified for supporting audio engine instructions */
+                  /* DVR jacky: modified for supporting video engine instructions */
+                case '&':    /* 10 bits immediate from 0 to 32, used in VE (OP_*_IMMIDATE6A) */
+                  my_getExpression (&imm_expr, s);
+                  check_absolute_expr (ip, &imm_expr);
+                  if ((imm_expr.X_add_number & ~0x3FF) != 0)
+                    as_bad (_("Number (0x%lx) larger than 10 bits"),
+                            (unsigned long) imm_expr.X_add_number);
+
+                  ip->insn_opcode |= ((imm_expr.X_add_number & OP_MASK_IMMIDATE6A) 
+                                      << OP_SH_IMMIDATE6A);
+
+                  imm_expr.X_op = O_absent;
+                  s = expr_end;
+                  continue;
+                  /* DVR jacky: modified for supporting video engine instructions */
+
+                  /* 2007-10-05 tonywu: add for IMMEDIATE8A */
+                case '=':
+                  my_getExpression (&imm_expr, s);
+                  check_absolute_expr (ip, &imm_expr);
+                  if ((imm_expr.X_add_number & ~0xFF) != 0)
+                    as_bad (_("Number (0x%lx) larger than 8 bits"),
+                            (unsigned long) imm_expr.X_add_number);
+
+                  ip->insn_opcode |= ((imm_expr.X_add_number & OP_MASK_IMMIDATE8A) 
+                                      << OP_SH_IMMIDATE8A);
+
+                  imm_expr.X_op = O_absent;
+                  s = expr_end;
+                  continue;
+                  /* 2007-10-05 tonywu: add for IMMEDIATE8A */
+
+                case '-':
+                  /* 10bits offset used in ltw (OP_*_OFFSET6A),
+                   * in fact it is 13 bits, multiple of 8; */
+                  if (*s == '(' && strchr (s + 1, '(') == 0) 
+                    { 
+                      imm_expr.X_op = O_constant; 
+                      imm_expr.X_add_number = 0;
+                      continue;
+                    }
+
+                  my_getExpression (&imm_expr, s);
+                  check_absolute_expr (ip, &imm_expr);
+                  if (imm_expr.X_op == O_constant)
+                    {
+                      if ((imm_expr.X_add_number % 8) != 0)
+                        as_bad (_("(%lu) is not multiple of 8"),
+                                (unsigned long) imm_expr.X_add_number); 
+
+                      if (((imm_expr.X_add_number + 4096) & ~0x1FFF) != 0)
+                        as_bad (_("Number (0x%lx) larger than 13 bits"),
+                                (unsigned long) imm_expr.X_add_number);
+                      ip->insn_opcode |= (((imm_expr.X_add_number >> 3) & OP_MASK_OFFSET6A) 
+                                          << OP_SH_OFFSET6A);
+                      imm_expr.X_op = O_absent;
+                    }
+                  //else
+                  //  *imm_reloc = BFD_RELOC_RLX_OFF6A; 
+                  s = expr_end;
+                  continue;
+
+                  /* 11 bits immediate used in lt,st (OP_*_IMMIDATE6b), 
+                   * in fact it is 14 bits, multiple of 8; */
+                case '@':
+                  if (*s == '(' && strchr (s + 1, '(') == 0)
+                    {
+                      imm_expr.X_op = O_constant;
+                      imm_expr.X_add_number = 0;
+                      continue;
+                    }
+                  my_getExpression (&imm_expr, s);
+                  check_absolute_expr (ip, &imm_expr);
+                  if (imm_expr.X_add_number % 8 != 0)
+                    as_bad (_("(%d) is not multiple of 8"),
+                            (int) imm_expr.X_add_number); 
+
+                  if (((imm_expr.X_add_number + 8192) & ~0x3FFF) != 0)
+                    as_bad (_("Number (0x%lx) larger than 14 bits"),
+                            (unsigned long) imm_expr.X_add_number);
+                  ip->insn_opcode |= (((imm_expr.X_add_number >> 3) & OP_MASK_IMMIDATE6b) 
+                                      << OP_SH_IMMIDATE6b);
+                  imm_expr.X_op = O_absent;
+                  s = expr_end;
+                  continue;
+
+                  /* 4 bits immediate from 0 to 8,used in MFA,MFA2,RNDA2 (OP_*_IMMIDATE74) */
+                case '#':
+                  my_getExpression (&imm_expr, s);
+                  check_absolute_expr (ip, &imm_expr);
+                  if (imm_expr.X_add_number > 8 || imm_expr.X_add_number < 0)
+                    as_bad (_("(%d) is out of range 0-8"),
+                            (int) imm_expr.X_add_number);
+                  ip->insn_opcode |= ((imm_expr.X_add_number & OP_MASK_IMMIDATE74) 
+                                      << OP_SH_IMMIDATE74);
+                  imm_expr.X_op = O_absent;
+                  s = expr_end;
+                  continue;
+
+                  /* 8 bits immediate ,used in lbp,stp,etc(OP_*_IMMIDATE88) */
+                case '~':
+                  my_getExpression (&imm_expr, s);
+                  check_absolute_expr (ip, &imm_expr);
+                  if ((strncmp (str, "lbp", 3) == 0)
+                      || (strncmp (str, "sbp", 3) == 0))
+                    multipletype = 0;
+                  else if ((strncmp (str, "lhp", 3) == 0)
+                           || (strncmp (str, "shp", 3) == 0))
+                    multipletype = 2;
+                  else if ((strncmp (str, "lwp", 3) == 0)
+                           || (strncmp (str, "swp", 3) == 0))
+                    multipletype = 4;
+                  else
+                    multipletype = 8;
+
+                  switch (multipletype)
+                    {
+                    case 0:
+                      if (((imm_expr.X_add_number + 128) & ~0xff) != 0)
+                        as_bad (_("Number (0x%lx) larger than 8 bits"),
+                                (unsigned long) imm_expr.X_add_number);
+                      break;
+                    case 2:
+                      if ((imm_expr.X_add_number % 2) != 0)
+                        as_bad (_("(%lu) is not multiple of 2"),
+                                (unsigned long) imm_expr.X_add_number);
+                      if (((imm_expr.X_add_number + 256) & ~0x1FF) != 0)
+                        as_bad (_("Number (0x%lx) larger than 8 bits"),
+                                (unsigned long) imm_expr.X_add_number);
+                      imm_expr.X_add_number = imm_expr.X_add_number >> 1;
+                      break;
+                    case 4:
+                      if ((imm_expr.X_add_number % 4) != 0)
+                        as_bad (_("(%lu) is not multiple of 4"),
+                                (unsigned long) imm_expr.X_add_number);
+                      if (((imm_expr.X_add_number + 512) & ~0x3FF) != 0)
+                        as_bad (_("Number (0x%lx) larger than 8 bits"),
+                                (unsigned long) imm_expr.X_add_number);
+                      imm_expr.X_add_number = imm_expr.X_add_number >> 2;
+                      break;
+                    case 8:
+                      if ((imm_expr.X_add_number % 8) != 0)
+                        as_bad (_("(%lu) is not multiple of 8"),
+                                (unsigned long) imm_expr.X_add_number);
+                      if (((imm_expr.X_add_number + 1024) & ~0x7FF) != 0)
+                        as_bad (_("Number (0x%lx) larger than 8 bits"),
+                                (unsigned long) imm_expr.X_add_number);
+                      imm_expr.X_add_number = imm_expr.X_add_number >> 3;
+                      break;
+                    }
+
+                  ip->insn_opcode |= ((imm_expr.X_add_number & OP_MASK_IMMIDATE88)
+                                      << OP_SH_IMMIDATE88);
+                  imm_expr.X_op = O_absent;
+                  s = expr_end;
+                  continue;
+
+                  /* even register,used in lt,st,ltp,stp (OP_*_EVENREG) */
+                case '`':
+                  if (s[0] == '$')
+                    {
+                      regno = 0;
+                      if (ISDIGIT (s[1]))
+                        {
+                          ++s;
+                          do
+                            {
+                              regno *= 10;
+                              regno += *s - '0';
+                              ++s;
+                            }
+                          while (ISDIGIT (*s));
+                        }
+                      else if ((s[1] == 'f') && (s[2] == 'p'))
+                        {
+                          regno = 30;
+                          s += 3;
+                        }
+                      else if ((s[1] == 'a') && (s[2] == 't'))
+                        {
+                          regno = 1;
+                          s += 3;
+                        }
+                      else
+                        {
+                          insn_error = "register needed!";
+                          return;
+                        }
+                    }
+                  else
+                    {
+                      insn_error = "register needed!";
+                      return;
+                    }
+
+                  if (regno > 31)
+                    as_bad (_("invalid register number (%d)"), regno);
+
+                  if (regno % 2 != 0)
+                    as_bad (_("not an even register number(%d) "), regno);
+
+                  ip->insn_opcode |= (regno & OP_MASK_EVENREG) << OP_SH_EVENREG;
+                  continue; 
+
+                case 'H':
+                  if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
+                    s += 2;
+
+                  if (ISDIGIT (*s))
+                    {
+                      c = 0;
+                      do
+                        {
+                          c *= 10;
+                          c += *s - '0';
+                          ++s;
+                        }
+                      while (ISDIGIT (*s));
+                    }
+                  else
+                    c = 64; /* Invalid sel or stype value. */
+
+                  if (c > 63)
+                    as_bad (_("invalid coprocessor sel value (0-63)"));
+
+                  ip->insn_opcode |= (c & OP_MASK_RLX_SEL) << OP_SH_RLX_SEL;
+                  continue;
+
+                case 'I':
+                  if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
+                    s += 2;
+                  if (ISDIGIT (*s))
+                    {
+                      c = 0;
+                      do
+                        {
+                          c *= 10;
+                          c += *s - '0';
+                          ++s;
+                        }
+                      while (ISDIGIT (*s));
+                    }
+                  else
+                    c = 64; /* Invalid sel or stype value. */
+
+                  if (c > 63)
+                    as_bad (_("invalid coprocessor stype value (0-63)"));
+
+                  ip->insn_opcode |= (c & OP_MASK_RLX_STYPE) << OP_SH_RLX_STYPE;
+                  continue;
+                }
+
+              break;
+              /* dbb: radiax instructions support */
+              /* 2006-01-04 tonywu: merged from 2.14 to 2.16 */
+     default:
 	      internalError ();
 	    }
 	  break;
@@ -13930,6 +14674,9 @@ mips16_immed (char *file, unsigned int l
     {
       mintiny = - (1 << (op->nbits - 1));
       maxtiny = (1 << (op->nbits - 1)) - 1;
+      /* force extend `b 0x3ff' */
+      if (fix_bdsl && type == 'q')
+        --maxtiny;
     }
 
   /* Branch offsets have an implicit 0 in the lowest bit.  */
@@ -14040,7 +14787,15 @@ static const struct percent_op_match mip
   {"%gprel", BFD_RELOC_MIPS16_GPREL},
   {"%got", BFD_RELOC_MIPS16_GOT16},
   {"%call16", BFD_RELOC_MIPS16_CALL16},
-  {"%hi", BFD_RELOC_MIPS16_HI16_S}
+  {"%hi", BFD_RELOC_MIPS16_HI16_S}/*,
+  {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
+  {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
+  {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
+  {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
+  {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
+  {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
+  {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
+  */
 };
 
 
@@ -14209,6 +14964,7 @@ enum options
     OPTION_MIPS64,
     OPTION_MIPS32R2,
     OPTION_MIPS64R2,
+    OPTION_MCE,
     OPTION_MIPS16,
     OPTION_NO_MIPS16,
     OPTION_MIPS3D,
@@ -14285,6 +15041,9 @@ enum options
     OPTION_NO_PDR,
     OPTION_MVXWORKS_PIC,
 #endif /* OBJ_ELF */
+    OPTION_FIX_BDSL,
+    OPTION_WARN_POSSIBLE_LOAD_USE,
+    OPTION_WARN_MISSING_DELAY_SLOT,
     OPTION_END_OF_ENUM    
   };
   
@@ -14396,6 +15155,9 @@ struct option md_longopts[] =
   {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
   {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
 #endif /* OBJ_ELF */
+  {"ffix-bdsl", no_argument, NULL, OPTION_FIX_BDSL},
+  {"warn-possible-load-use", no_argument, NULL, OPTION_WARN_POSSIBLE_LOAD_USE},
+  {"warn-missing-delay-slot", no_argument, NULL, OPTION_WARN_MISSING_DELAY_SLOT},
 
   {NULL, no_argument, NULL, 0}
 };
@@ -14431,6 +15193,18 @@ md_parse_option (int c, char *arg)
       mips_disable_float_construction = 1;
       break;
 
+    case OPTION_FIX_BDSL:
+      fix_bdsl = 1;
+      break;
+
+    case OPTION_WARN_POSSIBLE_LOAD_USE:
+      warn_possible_load_use = 1;
+      break;
+
+    case OPTION_WARN_MISSING_DELAY_SLOT:
+      warn_missing_delay_slot = 1;
+      break;
+
     case OPTION_TRAP:
       mips_trap = 1;
       break;
@@ -14509,6 +15283,9 @@ md_parse_option (int c, char *arg)
       mips_set_option_string (&mips_arch_string, arg);
       break;
 
+    case OPTION_MCE:
+      break;
+
     case OPTION_M4650:
       mips_set_option_string (&mips_arch_string, "4650");
       mips_set_option_string (&mips_tune_string, "4650");
@@ -15036,7 +15813,7 @@ mips_after_parse_args (void)
 	  || mips_abi == O32_ABI))
     mips_32bitmode = 1;
 
-  if (mips_opts.isa == ISA_MIPS1 && mips_trap)
+  if ((mips_opts.isa == ISA_MIPS1 || ISA_IS_RLX) && mips_trap)
     as_bad (_("trap exception not supported at ISA 1"));
 
   /* If the selected architecture includes support for ASEs, enable
@@ -15113,6 +15890,9 @@ mips_after_parse_args (void)
     }
 }
 
+
+extern char *myname;
+
 void
 mips_init_after_args (void)
 {
@@ -15369,6 +16149,8 @@ md_apply_fix (fixS *fixP, valueT *valP,
     case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
     case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
     case BFD_RELOC_MIPS_TLS_GOTTPREL:
+    case BFD_RELOC_MIPS_TLS_TPREL32:
+    case BFD_RELOC_MIPS_TLS_TPREL64:
     case BFD_RELOC_MIPS_TLS_TPREL_HI16:
     case BFD_RELOC_MIPS_TLS_TPREL_LO16:
     case BFD_RELOC_MICROMIPS_TLS_GD:
@@ -15378,6 +16160,14 @@ md_apply_fix (fixS *fixP, valueT *valP,
     case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
     case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
     case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
+    /*case BFD_RELOC_MIPS16_TLS_GD:
+    case BFD_RELOC_MIPS16_TLS_LDM:
+    case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
+    case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
+    case BFD_RELOC_MIPS16_TLS_GOTTPREL:
+    case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
+    case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
+    */
       S_SET_THREAD_LOCAL (fixP->fx_addsy);
       /* fall through */
 
@@ -15570,6 +16360,36 @@ md_apply_fix (fixS *fixP, valueT *valP,
       fixP->fx_done = 0;
       break;
 
+/*
+    case BFD_RELOC_RLX_OFF6A: 
+      if (fixP->fx_done) 
+        { 
+          valueT tmp_value; 
+          valueT org_value;
+
+          buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); 
+          tmp_value = *(valueT *) (fixP->fx_frag->fr_literal + fixP->fx_where); 
+          org_value = *valP; 
+          if (target_big_endian) 
+            { 
+              tmp_value = (((tmp_value & 0xff) << 24) 
+                           | ((tmp_value & 0xff00) << 8) 
+                           | (((tmp_value & 0xff0000) >> 8)) 
+                           | (((tmp_value & 0xff000000) >> 24))); 
+            }
+
+          if ((org_value % 8) != 0) 
+            as_bad (_("(%d) is not multiple of 8"), (int) org_value); 
+
+          if ((org_value & ~0x1FFF) != 0) 
+            as_bad (_("(%d) is too large to stay in 13 bits"), (int) org_value);
+
+          tmp_value |= (((org_value >> 3) & OP_MASK_OFFSET6A) << OP_SH_OFFSET6A); 
+          md_number_to_chars ((char *) buf, tmp_value, 4);
+        } 
+      break;
+*/
+
     default:
       internalError ();
     }
@@ -16552,7 +17372,8 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED)
    use in DWARF debug information.  */
 
 static void
-s_dtprel_internal (size_t bytes)
+s_tls_rel_directive (const size_t bytes, const char *dirstr,
+		     bfd_reloc_code_real_type rtype)
 {
   expressionS ex;
   char *p;
@@ -16561,19 +17382,13 @@ s_dtprel_internal (size_t bytes)
 
   if (ex.X_op != O_symbol)
     {
-      as_bad (_("Unsupported use of %s"), (bytes == 8
-					   ? ".dtpreldword"
-					   : ".dtprelword"));
+      as_bad (_("Unsupported use of %s"), dirstr);
       ignore_rest_of_line ();
     }
 
   p = frag_more (bytes);
   md_number_to_chars (p, 0, bytes);
-  fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
-	       (bytes == 8
-		? BFD_RELOC_MIPS_TLS_DTPREL64
-		: BFD_RELOC_MIPS_TLS_DTPREL32));
-
+  fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
   demand_empty_rest_of_line ();
 }
 
@@ -16582,7 +17397,7 @@ s_dtprel_internal (size_t bytes)
 static void
 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
 {
-  s_dtprel_internal (4);
+  s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
 }
 
 /* Handle .dtpreldword.  */
@@ -16590,9 +17405,26 @@ s_dtprelword (int ignore ATTRIBUTE_UNUSE
 static void
 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
 {
-  s_dtprel_internal (8);
+  s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
+}
+
+/* Handle .tprelword.  */
+
+static void
+s_tprelword (int ignore ATTRIBUTE_UNUSED)
+{
+  s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
 }
 
+/* Handle .tpreldword.  */
+
+static void
+s_tpreldword (int ignore ATTRIBUTE_UNUSED)
+{
+  s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
+}
+
+
 /* Handle the .gpvalue pseudo-op.  This is used when generating NewABI PIC
    code.  It sets the offset to use in gp_rel relocations.  */
 
@@ -16996,6 +17828,9 @@ mips16_extended_frag (fragS *fragp, asec
     {
       mintiny = - (1 << (op->nbits - 1));
       maxtiny = (1 << (op->nbits - 1)) - 1;
+      /* force extend `b 0x3ff' */
+      if (fix_bdsl && type == 'q')
+        --maxtiny;
     }
 
   sym_frag = symbol_get_frag (fragp->fr_symbol);
@@ -17203,7 +18038,7 @@ relaxed_branch_length (fragS *fragp, ase
 	{
 	  /* Additional space for PIC loading of target address.  */
 	  length += 8;
-	  if (mips_opts.isa == ISA_MIPS1)
+	  if (mips_opts.isa == ISA_MIPS1 || ISA_IS_RLX)
 	    /* Additional space for $at-stabilizing nop.  */
 	    length += 4;
 	}
@@ -17809,7 +18644,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNU
 	      md_number_to_chars ((char *) buf, insn, 4);
 	      buf += 4;
 
-	      if (mips_opts.isa == ISA_MIPS1)
+	      if (mips_opts.isa == ISA_MIPS1 || ISA_IS_RLX)
 		{
 		  /* nop */
 		  md_number_to_chars ((char *) buf, 0, 4);
@@ -18906,6 +19741,17 @@ static const struct mips_cpu_info mips_c
   { "mips64",         MIPS_CPU_IS_ISA,		ISA_MIPS64,     CPU_MIPS64 },
   { "mips64r2",       MIPS_CPU_IS_ISA,		ISA_MIPS64R2,   CPU_MIPS64R2 },
 
+
+  /* RLX */
+  // trying to set isa to mips1
+  { "rlx4081",        0,			ISA_MIPS1,    CPU_R3000 },
+  { "rlx4180",        0,			ISA_MIPS1,    CPU_R3000 },
+  { "rlx4181",        0,			ISA_MIPS1,    CPU_R3000 },
+  { "rlx4281",        0,			ISA_MIPS1,    CPU_R3000 },
+  { "rlx5181",        0,			ISA_MIPS1,    CPU_R3000 },
+  { "rlx5280",        0,			ISA_MIPS1,    CPU_R3000 },
+  { "rlx5281",        0,			ISA_MIPS1,    CPU_R3000 },
+
   /* MIPS I */
   { "r3000",          0,			ISA_MIPS1,      CPU_R3000 },
   { "r2000",          0,			ISA_MIPS1,      CPU_R3000 },
@@ -19078,7 +19924,13 @@ mips_matching_cpu_name_p (const char *ca
   /* If not, try comparing based on numerical designation alone.
      See if GIVEN is an unadorned number, or 'r' followed by a number.  */
   if (TOLOWER (*given) == 'r')
-    given++;
+    {
+      /* 2006-01-19 tonywu: add to parse LX/RX CPUs */ 
+      if (TOLOWER (given[1]) == 'l' && TOLOWER (given[2]) == 'x')
+        given += 3; 
+      else
+        given++;
+    }
   if (!ISDIGIT (*given))
     return FALSE;
 
@@ -19086,10 +19938,15 @@ mips_matching_cpu_name_p (const char *ca
      hoping to find a number there too.  */
   if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
     canonical += 2;
-  else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
-    canonical += 2;
   else if (TOLOWER (canonical[0]) == 'r')
-    canonical += 1;
+    {
+      if (TOLOWER (canonical[1]) == 'l' && TOLOWER (canonical[2]) == 'x') 
+        canonical += 3;
+      else if (TOLOWER (canonical[1]) == 'm')
+        canonical += 2;
+      else
+        canonical += 1;
+    }
 
   return mips_strict_matching_cpu_name_p (canonical, given);
 }
@@ -19353,3 +20210,68 @@ tc_mips_regname_to_dw2regnum (char *regn
 
   return regnum;
 }
+
+
+/* 2006-01-05 tonywu: merged from 2.14 */
+static inline int
+rlx_is_tword_use(const struct mips_cl_insn *insn1, const struct mips_cl_insn *insn2)
+{
+  int regno1;
+  int regno2;
+ 
+  if (insn1 == NULL || insn2 == NULL) 
+    return 0;
+ 
+  if (strncmp(insn1->insn_mo->name, "lt", 2) != 0
+      && strncmp(insn1->insn_mo->name, "ltw", 3) != 0)
+    return 0;
+ 
+  regno1 = EXTRACT_OPERAND(mips_opts.micromips, RT, *insn1); 
+  regno2 = regno1 + 1;
+
+#warning "Fix this"
+  //if (insn_uses_reg(insn2, regno1, MIPS_GR_REG) || 
+  //    insn_uses_reg(insn2, regno2, MIPS_GR_REG)) 
+    return 1;
+
+
+  return 0;
+} 
+
+static inline int
+rlx_nops_for_new_insn(const struct mips_cl_insn *pre, const struct mips_cl_insn *now)
+{ 
+  if ((pre == NULL) || (now == NULL)) 
+    return 0;
+
+  if ((pre->insn_mo->match == 0 && pre->insn_mo->mask == 0xffffffff) || 
+      (now->insn_mo->match == 0 && now->insn_mo->mask == 0xffffffff)) 
+    return 0;
+
+  if (pre->insn_mo == &dummy_opcode || now->insn_mo == &dummy_opcode) 
+    return 0;
+
+  if (strcmp(pre->insn_mo->name, "madda") == 0 &&
+      strcmp(now->insn_mo->name, "mfa") == 0 && 
+      EXTRACT_OPERAND(mips_opts.micromips, RD, *pre) == EXTRACT_OPERAND(mips_opts.micromips, RT, *now))
+    return 2;
+
+  return 0;
+}
+
+static void
+rlx_warn_bdsl (const struct mips_cl_insn *insn2)
+{
+    struct mips_cl_insn *insn1 = history;
+
+    if ((insn1->insn_mo->pinfo
+          & (INSN_UNCOND_BRANCH_DELAY
+            | INSN_COND_BRANCH_DELAY)) != 0
+        && ((insn2->insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) != 0
+            || (mips_opts.mips16
+		&& strcmp(insn2->insn_mo->name, "nop") != 0)))
+      {
+	as_warn (_("Branch-Deay-Slot-Load at noreorder section for `%s'"),
+	    insn2->insn_mo->name);
+      }
+}
diff -rupN ./bu.orig/include/elf/mips.h ./bu.new/include/elf/mips.h
--- a/include/elf/mips.h	2011-07-24 17:20:12.000000000 +0300
+++ b/include/elf/mips.h	2013-09-26 20:56:56.787659157 +0300
@@ -89,7 +89,8 @@ START_RELOC_NUMBERS (elf_mips_reloc_type
   RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49)
   RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50)
   RELOC_NUMBER (R_MIPS_GLOB_DAT, 51)
-  FAKE_RELOC (R_MIPS_max, 52)
+  RELOC_NUMBER (R_RELOC_RLX_OFF6A, 52)
+  FAKE_RELOC (R_MIPS_max, 53)
   /* These relocs are used for the mips16.  */
   FAKE_RELOC (R_MIPS16_min, 100)
   RELOC_NUMBER (R_MIPS16_26, 100)
@@ -98,7 +99,14 @@ START_RELOC_NUMBERS (elf_mips_reloc_type
   RELOC_NUMBER (R_MIPS16_CALL16, 103)
   RELOC_NUMBER (R_MIPS16_HI16, 104)
   RELOC_NUMBER (R_MIPS16_LO16, 105)
-  FAKE_RELOC (R_MIPS16_max, 106)
+  RELOC_NUMBER (R_MIPS16_TLS_GD, 106)
+  RELOC_NUMBER (R_MIPS16_TLS_LDM, 107)
+  RELOC_NUMBER (R_MIPS16_TLS_DTPREL_HI16, 108)
+  RELOC_NUMBER (R_MIPS16_TLS_DTPREL_LO16, 109)
+  RELOC_NUMBER (R_MIPS16_TLS_GOTTPREL, 110)
+  RELOC_NUMBER (R_MIPS16_TLS_TPREL_HI16, 111)
+  RELOC_NUMBER (R_MIPS16_TLS_TPREL_LO16, 112)
+  FAKE_RELOC (R_MIPS16_max, 113)
   /* These relocations are specific to VxWorks.  */
   RELOC_NUMBER (R_MIPS_COPY, 126)
   RELOC_NUMBER (R_MIPS_JUMP_SLOT, 127)
diff -rupN ./bu.orig/include/opcode/mips.h ./bu.new/include/opcode/mips.h
--- a/include/opcode/mips.h	2011-08-09 18:20:03.000000000 +0300
+++ b/include/opcode/mips.h	2013-10-19 16:21:40.062836212 +0300
@@ -59,6 +59,42 @@
 
    The general coprocessor instructions use COPZ.  */
 
+/* dbb: modified for supporting radiax instructions */
+#define OP_MASK_IMMIDATE74	0xf    /* used in MFA,MFA2,RNDA2 */
+#define OP_SH_IMMIDATE74	7      /* used in MFA,MFA2,RNDA2 */
+#define OP_MASK_IMMIDATE6b	0x7ff  /* used in lt,st */
+#define OP_SH_IMMIDATE6b	6      /* used in lt,st */
+#define OP_MASK_IMMIDATE88	0xff   /* used in lbp,stp,etc */
+#define OP_SH_IMMIDATE88	8      /* used in lbp,stp,etc */
+#define OP_MASK_EVENREG		0x1f   /* used in lt,st,ltp,stp */
+#define OP_SH_EVENREG		16     /* used in lt,st,ltp,stp */
+#define OP_MASK_OFFSET6A	0x3ff  /* used in ltw */
+#define OP_SH_OFFSET6A		6      /* used in ltw */
+/* dbb: modified for supporting radiax instructions */
+
+/* DVR taro: modified for supporting audio engine instructions */
+#define OP_MASK_IMMIDATEa6	0x3f
+#define OP_SH_IMMIDATEa6	10
+/* DVR taro: modified for supporting audio engine instructions */
+
+/* DVR jacky: modified for supporting audio engine instructions */
+#define OP_MASK_IMMIDATE6A	0x3ff
+#define OP_SH_IMMIDATE6A	6
+/* DVR jacky: modified for supporting audio engine instructions */
+
+/* DVR yj: modified for supporting video engine2 instructions */
+#define OP_MASK_IMMIDATE8A	0xff
+#define OP_SH_IMMIDATE8A	8
+/* DVR yj: modified for supporting video engine2 instructions */
+
+/* 2009-03-19 tonywu: add for taroko */
+#define OP_MASK_RLX_SEL		0x3f
+#define OP_SH_RLX_SEL		0
+#define OP_MASK_RLX_STYPE	0x3f
+#define OP_SH_RLX_STYPE		6
+/* 2009-03-19 tonywu: add for taroko */
+
+
 #define OP_MASK_OP		0x3f
 #define OP_SH_OP		26
 #define OP_MASK_RS		0x1f
@@ -416,6 +452,33 @@ struct mips_opcode
 	Requires that "+A" or "+E" occur first to set position.
 	Enforces: 32 < (pos+size) <= 64.
 
+**** dbb  modified for supporting radiax instructions **************************
+   "#`"  even register,used in lt,st,ltp,stp (OP_*_EVENREG)
+   "#~" 8 bits immediate ,used in lbp,stp,etc(OP_*_IMMIDATE88)
+   "##" 4 bits immediate from 0 to 8,used in MFA,MFA2,RNDA2 (OP_*_IMMIDATE74)
+   "#@" 11 bits immediate used in lt,st (OP_*_IMMIDATE6b),in fact it is 14 bits,multiple of 8;
+   "#-"  10 bits offset,used in ltw(OP_*_OFFSET6A)
+   "#$"
+   "#&"
+   "#="
+   "#H"
+   "#I"
+   "#u"
+   "#k"
+   "#d1"
+   "#d2"
+   "#d3"
+   "#d4"
+   "#s1"
+   "#s2"
+   "#s3"
+   "#t1"
+   "#t2"
+   "#t3"
+**** dbb  modified for supporting radiax instructions **************************
+
+
+
    Floating point instructions:
    "D" 5 bit destination register (OP_*_FD)
    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
@@ -531,9 +594,9 @@ struct mips_opcode
    instructions, if it is not equal to INSN_MACRO.  */
 
 /* Modifies the general purpose register in OP_*_RD.  */
-#define INSN_WRITE_GPR_D            0x00000001
+#define INSN_WRITE_RAD_D            0x00000001
 /* Modifies the general purpose register in OP_*_RT.  */
-#define INSN_WRITE_GPR_T            0x00000002
+#define INSN_WRITE_RAD_T            0x00000002
 /* Modifies general purpose register 31.  */
 #define INSN_WRITE_GPR_31           0x00000004
 /* Modifies the floating point register in OP_*_FD.  */
@@ -543,9 +606,9 @@ struct mips_opcode
 /* Modifies the floating point register in OP_*_FT.  */
 #define INSN_WRITE_FPR_T            0x00000020
 /* Reads the general purpose register in OP_*_RS.  */
-#define INSN_READ_GPR_S             0x00000040
+#define INSN_READ_RAD_S             0x00000040
 /* Reads the general purpose register in OP_*_RT.  */
-#define INSN_READ_GPR_T             0x00000080
+#define INSN_READ_RAD_T             0x00000080
 /* Reads the floating point register in OP_*_FS.  */
 #define INSN_READ_FPR_S             0x00000100
 /* Reads the floating point register in OP_*_FT.  */
@@ -617,6 +680,7 @@ struct mips_opcode
    same information.  */
 #define INSN2_M_FP_D		    0x00000010
 /* Modifies the general purpose register in OP_*_RZ.  */
+
 #define INSN2_WRITE_GPR_Z	    0x00000020
 /* Modifies the floating point register in OP_*_FZ.  */
 #define INSN2_WRITE_FPR_Z	    0x00000040
@@ -673,13 +737,18 @@ struct mips_opcode
 /* Reads the general purpose registers in MICROMIPSOP_*_MM/N.  */
 #define INSN2_READ_GPR_MMN	    0x80000000
 
+/* DMP CEI 
+   Identify an opcode is DMP CEI or not. */
+#define INSN2_TWORD_LOAD            0x00400000
+#define INSN2_TWORD_USE             0x00800000
+
 /* Masks used to mark instructions to indicate which MIPS ISA level
    they were introduced in.  INSN_ISA_MASK masks an enumeration that
    specifies the base ISA level(s).  The remainder of a 32-bit
    word constructed using these macros is a bitmask of the remaining
    INSN_* values below.  */
 
-#define INSN_ISA_MASK		  0x0000000ful
+#define INSN_ISA_MASK		  0x0000001ful
 
 /* We cannot start at zero due to ISA_UNKNOWN below.  */
 #define INSN_ISA1                 1
@@ -689,17 +758,39 @@ struct mips_opcode
 #define INSN_ISA5                 5
 #define INSN_ISA32                6
 #define INSN_ISA32R2              7
-#define INSN_ISA64                8
-#define INSN_ISA64R2              9
+
+/* RLX ASE */
+#define INSN_RLX_MASK		  0x00000008ul
+
+#define INSN_RLX4081              9  /* Kinmen */
+#define INSN_RLX4180              10 /* Lexra */
+#define INSN_RLX4181              11 /* RLX */
+#define INSN_RLX4281              12 /* Taroko */
+#define INSN_RLX5181              13 /* RLX + Radiax-1 */
+#define INSN_RLX5280              14 /* Lexra + Radiax-1 */
+#define INSN_RLX5281              15 /* Taroko + Radiax-1 + Radiax-2 */
+
+#define INSN_ISA64                16
+#define INSN_ISA64R2              17
 /* Below this point the INSN_* values correspond to combinations of ISAs.
    They are only for use in the opcodes table to indicate membership of
    a combination of ISAs that cannot be expressed using the usual inclusion
    ordering on the above INSN_* values.  */
-#define INSN_ISA3_32              10
-#define INSN_ISA3_32R2            11
-#define INSN_ISA4_32              12
-#define INSN_ISA4_32R2            13
-#define INSN_ISA5_32R2            14
+#define INSN_ISA3_32              18
+#define INSN_ISA3_32R2            19
+#define INSN_ISA4_32              20
+#define INSN_ISA4_32R2            21
+#define INSN_ISA5_32R2            22
+
+/* RLX ASE group */
+#define INSN_RLX_ALL              24
+#define INSN_RLX_UDI              25
+#define INSN_RLX_TAROKO           26
+#define INSN_RLX_RAD1             27
+#define INSN_RLX_RAD2             28
+#define INSN_RLX_DMP              29
+#define INSN_ISA2_RLX             30
+#define INSN_ISA32_RALL           31
 
 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
    INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
@@ -710,10 +801,13 @@ struct mips_opcode
    (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
    is non-zero.  */
 static const unsigned int mips_isa_table[] =
-  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
-
+{
+  0x00000001, 0x20000003, 0x20060007, 0x201e000f, 0x203e001f, 0x600a0023,
+  0x603e0063, 0x40000081, 0x40800101, 0x40800201, 0x61800401, 0x63800801,
+  0x75801001, 0x55802001, 0x6f804001, 0x603e803f, 0x603f807f,
+};
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK		  0xc3ff0c20
+#define INSN_CHIP_MASK		  0xc3ff1c00
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON		  0x00000800
@@ -766,7 +860,7 @@ static const unsigned int mips_isa_table
 /* Loongson 3A.  */
 #define INSN_LOONGSON_3A          0x00000400
 /* RMI Xlr instruction */
-#define INSN_XLR              	  0x00000020
+#define INSN_XLR              	  0x00001000
 
 /* MCU (MicroController) ASE */
 #define INSN_MCU		  0x00000010
@@ -786,6 +880,14 @@ static const unsigned int mips_isa_table
 #define       ISA_MIPS32R2    INSN_ISA32R2
 #define       ISA_MIPS64R2    INSN_ISA64R2
 
+/* RLX ASE */
+#define       ISA_RLX4081     INSN_ISA1
+#define       ISA_RLX4180     INSN_ISA1
+#define       ISA_RLX4181     INSN_ISA1
+#define       ISA_RLX4281     INSN_ISA1
+#define       ISA_RLX5181     INSN_ISA1
+#define       ISA_RLX5280     INSN_ISA1
+#define       ISA_RLX5281     INSN_ISA1
 
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
@@ -825,6 +927,14 @@ static const unsigned int mips_isa_table
 #define CPU_OCTEON	6501
 #define CPU_XLR     	887682   	/* decimal 'XLR'   */
 
+#define CPU_RLX4081     4081      /* RLX4081 */
+#define CPU_RLX4180     4180      /* RLX4180 */
+#define CPU_RLX4181     4181      /* RLX4181 */
+#define CPU_RLX4281     4281      /* RLX4281 */
+#define CPU_RLX5181     5181      /* RLX5181 */
+#define CPU_RLX5280     5280      /* RLX5280 */
+#define CPU_RLX5281     5281      /* RLX5281 */
+
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
@@ -1285,6 +1395,16 @@ extern int bfd_mips_num_opcodes;
    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
    "m" 7 bit register list for save instruction (18 bit extended)
    "M" 7 bit register list for restore instruction (18 bit extended)
+
+   Cache instruction:
+   "o" 0 bit offset (for compatible with mips1 mode)
+
+   Macro instructions:
+   "I" 32 bit immediate (value placed in imm_expr).
+
+   Coprocessor instructions:
+   "T" 5 bit target register (MIPS16OP_*_REGR32)
+   "G" 5 bit destination register (MIPS16OP_*_REG32R)
   */
 
 /* Save/restore encoding for the args field when all 4 registers are
diff -rupN ./bu.orig/opcodes/micromips-opc.c ./bu.new/opcodes/micromips-opc.c
--- a/opcodes/micromips-opc.c	2011-08-09 18:20:03.000000000 +0300
+++ b/opcodes/micromips-opc.c	2013-09-26 23:20:37.284803535 +0300
@@ -58,17 +58,17 @@
 
 /* For 32-bit microMIPS instructions.  */
 #define WR_s	INSN_WRITE_GPR_S
-#define WR_d	INSN_WRITE_GPR_D
-#define WR_t	INSN_WRITE_GPR_T
+#define WR_d	INSN_WRITE_RAD_D
+#define WR_t	INSN_WRITE_RAD_T
 #define WR_31	INSN_WRITE_GPR_31
 #define WR_D	INSN_WRITE_FPR_D
 #define WR_T	INSN_WRITE_FPR_T
 #define WR_S	INSN_WRITE_FPR_S
 #define WR_CC	INSN_WRITE_COND_CODE
 
-#define RD_s	INSN_READ_GPR_S
-#define RD_b	INSN_READ_GPR_S
-#define RD_t	INSN_READ_GPR_T
+#define RD_s	INSN_READ_RAD_S
+#define RD_b	INSN_READ_RAD_S
+#define RD_t	INSN_READ_RAD_T
 #define RD_T	INSN_READ_FPR_T
 #define RD_S	INSN_READ_FPR_S
 #define RD_R	INSN_READ_FPR_R
diff -rupN ./bu.orig/opcodes/mips16-opc.c ./bu.new/opcodes/mips16-opc.c
--- a/opcodes/mips16-opc.c	2011-07-24 17:04:51.000000000 +0300
+++ b/opcodes/mips16-opc.c	2013-09-26 22:12:20.864576529 +0300
@@ -67,6 +67,16 @@
 #define I64	INSN_ISA64
 #define T3	INSN_3900
 
+/* 2006-01-19 tonywu: define RLXn to simplify opcodes listing */
+#define RALL	INSN_RLX_ALL
+#define I32_R	INSN_ISA32_RALL
+
+#define COD	INSN_COPROC_MOVE_DELAY
+#define CLD	INSN_COPROC_MEMORY_DELAY
+#define RD_C0	INSN_COP
+#define WR_C0	INSN_COP
+
+
 const struct mips_opcode mips16_opcodes[] =
 {
 /* name,    args,	match,	mask,	pinfo,         	pinfo2, membership */
@@ -110,6 +120,9 @@ const struct mips_opcode mips16_opcodes[
 {"bne",	    "x,y,p",	0, (int) M_BNE, INSN_MACRO,	0,	I1 },
 {"bne",     "x,U,p",	0, (int) M_BNE_I, INSN_MACRO,	0,	I1 },
 {"bnez",    "x,p",	0x2800, 0xf800, CBR|RD_x,	0,	I1 },
+/* 2006-01-19 tonywu: add blank break instructions */
+{"break",   "",		0xe805, 0xffff, TRAP,		0,	RALL },
+/* 2006-01-19 tonywu: add blank break instructions */
 {"break",   "6",	0xe805, 0xf81f, TRAP,		0,	I1 },
 {"bteqz",   "p",	0x6000, 0xff00, CBR|RD_T,	0,	I1 },
 {"btnez",   "p",	0x6100, 0xff00, CBR|RD_T,	0,	I1 },
@@ -244,6 +257,16 @@ const struct mips_opcode mips16_opcodes[
 {"zeb",	    "x",	0xe811, 0xf8ff, WR_x|RD_x,	0,      I32 },
 {"zeh",	    "x",	0xe831, 0xf8ff, WR_x|RD_x,	0,      I32 },
 {"zew",	    "x",	0xe851, 0xf8ff, WR_x|RD_x,	0,      I64 },
+  /* 2006-01-19 tonywu: add 16-bit mac instructions */
+{"madh",    "x,y",	0xf800, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0, RALL },
+{"madl",    "x,y",	0xf802, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0, RALL },
+{"mazh",    "x,y",	0xf804, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0, RALL },
+{"mazl",    "x,y",	0xf806, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0, RALL },
+{"msbh",    "x,y",	0xf810, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0, RALL },
+{"msbl",    "x,y",	0xf812, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0, RALL },
+{"mszh",    "x,y",	0xf814, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0, RALL },
+{"mszl",    "x,y",	0xf816, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0, RALL },
+  /* 2006-01-19 tonywu: add 16-bit mac instructions */
 };
 
 const int bfd_mips16_num_opcodes =
diff -rupN ./bu.orig/opcodes/mips-dis.c ./bu.new/opcodes/mips-dis.c
--- a/opcodes/mips-dis.c	2011-08-09 18:20:03.000000000 +0300
+++ b/opcodes/mips-dis.c	2013-10-14 20:11:22.849664241 +0300
@@ -169,6 +169,52 @@ static const char * const mips_gpr_names
   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
 };
 
+/* 2007-09-28 tonywu: extend to from 16 to 32 to prevent
+ * undefined pattern from crashing objdump
+ */
+static const char *const rlx_radacc_names_alias[32] = {
+  "reserved", "m0l",      "m0h",      "m0",
+  "reserved", "m1l",      "m1h",      "m1",
+  "reserved", "m2l",      "m2h",      "m2",
+  "reserved", "m3l",      "m3h",      "m3",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved"
+};
+/* 2007-09-28 tonywu: extend to from 16 to 32 to prevent
+ * undefined pattern from crashing objdump
+ */
+
+/* 2007-09-28 tonywu: extend to from 14 to 32 to prevent
+ * undefined pattern from crashing objdump
+ */
+static const char *const rlx_radreg_names_alias[32] = {
+  "cbs0",     "cbs1",     "cbs2",     "reserved",
+  "cbe0",     "cbe1",     "cbe2",     "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "lps0",     "lpe0",     "lpc0",     "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "mmd",      "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved"
+};
+
+/* 2007-09-28 tonywu: extend to from 14 to 32 to prevent
+ * undefined pattern from crashing objdump
+ */
+/* tonywu 2006-01-04: merge from 2.14 */
+static const char *const rlx_cplxc0_names_alias[32] = {
+  "estatus",  "ecause",   "intvec",   "cvstag",
+  "bpctl", "wmpctl", "wmpstatus", "wmpvaddr",
+  "tlptr", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "wmpextramask",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved",
+  "reserved", "reserved", "reserved", "reserved"
+};
+
 static const char * const mips_fpr_names_numeric[32] =
 {
   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
@@ -503,11 +549,24 @@ const struct mips_arch_choice mips_arch_
 {
   { "numeric",	0, 0, 0, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-
   { "r3000",	1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
     mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
   { "r3900",	1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "rlx4081",     1, bfd_mach_mips_rlx4081, CPU_RLX4081, ISA_MIPS1,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "rlx4180",     1, bfd_mach_mips_rlx4180, CPU_RLX4180, ISA_MIPS1,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "rlx4181",     1, bfd_mach_mips_rlx4181, CPU_RLX4181, ISA_MIPS1,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "rlx4281",     1, bfd_mach_mips_rlx4281, CPU_RLX4281, ISA_MIPS1,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "rlx5181",     1, bfd_mach_mips_rlx5181, CPU_RLX5181, ISA_MIPS1,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "rlx5280",     1, bfd_mach_mips_rlx5280, CPU_RLX5280, ISA_MIPS1,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "rlx5281",     1, bfd_mach_mips_rlx5281, CPU_RLX5281, ISA_MIPS1,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r4000",	1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
     mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
   { "r4010",	1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
@@ -920,6 +979,7 @@ print_insn_args (const char *d,
 		 const struct mips_opcode *opp)
 {
   int op, delta;
+  int mtype;
   unsigned int lsb, msb, msbd;
 
   lsb = 0;
@@ -1479,6 +1539,134 @@ print_insn_args (const char *d,
 				 (l >> OP_SH_FT) & OP_MASK_FT);
 	  break;
 
+//----------------------------------------------------------------------
+        case '#':
+          d++;
+          switch (*d)
+            {
+              case '@':
+                delta = ((l >> OP_SH_IMMIDATE6b) & OP_MASK_IMMIDATE6b) * 8;
+                if (delta & 0x2000)
+                  delta |= ~0x3fff;
+
+                (*info->fprintf_func) (info->stream, "%d", delta);
+                break;
+
+                /* 4 bits immediate from 0 to 8,used in MFA,MFA2,RNDA2 (OP_*_IMMIDATE74) */ 
+              case '#': 
+                (*info->fprintf_func) (info->stream, "%ld", 
+                                       (l >> OP_SH_IMMIDATE74) & OP_MASK_IMMIDATE74);
+                break;
+
+                /* 8 bits immediate, used in lbp,stp,etc(OP_*_IMMIDATE88) */ 
+              case '~':
+                delta = (l >> OP_SH_IMMIDATE88) & OP_MASK_IMMIDATE88;
+                if (delta & 0x80) 
+                  delta |= ~0xff; 
+                if ((strncmp (opp->name, "lbp", 3) == 0 
+                     || strncmp (opp->name, "sbp", 3) == 0)) 
+                  mtype = 1; 
+                else if ((strncmp (opp->name, "lhp", 3) == 0 
+                          || strncmp (opp->name, "shp", 3) == 0)) 
+                  mtype = 2; 
+                else if ((strncmp (opp->name, "lwp", 3) == 0 
+                          || strncmp (opp->name, "swp", 3) == 0)) 
+                  mtype = 4; 
+                else 
+                  mtype = 8; 
+
+                (*info->fprintf_func) (info->stream, "%i", delta * mtype); 
+                break;
+
+                /* even register,used in lt,st,ltp,stp (OP_*_EVENREG) */ 
+              case '`': 
+                delta = (l >> OP_SH_EVENREG) & OP_MASK_EVENREG; 
+                if ((delta % 2) != 0) 
+                  delta--;        /* for "lt" insn */ 
+                (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[delta]); 
+                break;
+
+                /* DVR taro: modified for supporting AE instructions */ 
+              case '$': 
+                (*info->fprintf_func) (info->stream, "%ld", 
+                                       (l >> OP_SH_IMMIDATEa6) & OP_MASK_IMMIDATEa6); 
+                break; 
+                /* DVR taro: modified for supporting AE instructions */
+
+                /* DVR jacky:  modified for supporting VE instructions */ 
+              case '&': 
+                (*info->fprintf_func) (info->stream, "%ld",
+                                       (l >> OP_SH_IMMIDATE6A) & OP_MASK_IMMIDATE6A); 
+                break;
+
+              case '=': 
+                (*info->fprintf_func) (info->stream, "%ld", 
+                                       (l >> OP_SH_IMMIDATE8A) & OP_MASK_IMMIDATE8A); 
+                break; 
+                /* DVR jacky:  modified for supporting VE instructions */
+
+                /* 2008-07-08 tonywu: add for taroko processor */ 
+              case 'H':
+                (*info->fprintf_func) (info->stream, "%ld", 
+                                       (l >> OP_SH_RLX_SEL) & OP_MASK_RLX_SEL); 
+                break;
+
+              case 'I': 
+                (*info->fprintf_func) (info->stream, "%ld", 
+                                       (l >> OP_SH_RLX_STYPE) & OP_MASK_RLX_STYPE); 
+                break;
+                /* 2008-07-08 tonywu: add for taroko processor */
+
+                /* 10 bits offset,used in ltw(OP_*_OFFSET6A) */ 
+              case '-': 
+                delta = (l >> OP_SH_OFFSET6A) & OP_MASK_OFFSET6A; 
+                if (delta & 0x200) 
+                  delta |= ~0x3ff;
+
+                /* 2006-02-08 tonywu: fix ltw objdump displacement */ 
+                delta <<= 3; 
+                (*info->fprintf_func) (info->stream, "%d", delta); 
+                break;
+
+              case 'k':
+              case 'u': 
+                delta = (l >> OP_SH_RD) & OP_MASK_RD; 
+                if (delta > 31 || delta < 0) 
+                  (*info->fprintf_func) (info->stream, "INVALID"); 
+                else 
+                  (*info->fprintf_func) (info->stream, "%s", 
+                                         rlx_radreg_names_alias[delta]); 
+                break;
+
+              case 'd': delta = (l >> OP_SH_RD) & OP_MASK_RD; goto GET_TYPE;
+              case 's': delta = (l >> OP_SH_RS) & OP_MASK_RS; goto GET_TYPE; 
+              case 't': delta = (l >> OP_SH_RT) & OP_MASK_RT; goto GET_TYPE; 
+GET_TYPE: 
+		switch (*++d)
+		  { 
+		    case '1': /* ACC */ 
+		    case '2': /* ACC */
+		    case '3': /* ACC */ 
+		      if (delta > 15 || delta < 0) 
+			(*info->fprintf_func) (info->stream, "INVALID"); 
+		      else 
+			(*info->fprintf_func) (info->stream, "%s", 
+					       rlx_radacc_names_alias[delta]); 
+		      break; 
+		    case '4': 
+		      if (delta > 31 || delta < 0) 
+			(*info->fprintf_func) (info->stream, "INVALID"); 
+		      else 
+			(*info->fprintf_func) (info->stream, "%s", 
+					       rlx_cplxc0_names_alias[delta]); 
+		    break; 
+		  } 
+		break; 
+            }
+          break; 
+          /* dbb: modified for supporting radiax instructions */
+
+
 	default:
 	  /* xgettext:c-format */
 	  (*info->fprintf_func) (info->stream,
@@ -1555,7 +1743,7 @@ print_insn_mips (bfd_vma memaddr,
 	      if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
 	        {
 		  if ((op->pinfo & (INSN_WRITE_GPR_31
-				    | INSN_WRITE_GPR_D)) != 0)
+				    | INSN_WRITE_RAD_D)) != 0)
 		    info->insn_type = dis_jsr;
 		  else
 		    info->insn_type = dis_branch;
@@ -1643,6 +1831,10 @@ print_mips16_insn_arg (char type,
       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
       break;
 
+    case 'o':
+      (*info->fprintf_func) (info->stream, "0");
+      break;
+
     case 'S':
       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
       break;
@@ -2170,7 +2362,8 @@ print_insn_mips16 (bfd_vma memaddr, stru
     {
       if (op->pinfo != INSN_MACRO
 	  && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
-	  && (insn & op->mask) == op->match)
+	  && (insn & op->mask) == op->match
+	  && OPCODE_IS_MEMBER (op, mips_isa, mips_processor))
 	{
 	  const char *s;
 
@@ -2915,7 +3108,7 @@ print_insn_micromips (bfd_vma memaddr, s
 	  if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
 	       | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
 	    {
-	      if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
+	      if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_RAD_T)) != 0)
 		info->insn_type = dis_jsr;
 	      else
 		info->insn_type = dis_branch;
diff -rupN ./bu.orig/opcodes/mips-opc.c ./bu.new/opcodes/mips-opc.c
--- a/opcodes/mips-opc.c	2011-08-09 18:20:03.000000000 +0300
+++ b/opcodes/mips-opc.c	2013-10-11 16:50:51.176218785 +0300
@@ -41,15 +41,15 @@
 #define TRAP	INSN_NO_DELAY_SLOT
 #define SM	INSN_STORE_MEMORY
 
-#define WR_d    INSN_WRITE_GPR_D
-#define WR_t    INSN_WRITE_GPR_T
+#define WR_d    INSN_WRITE_RAD_D
+#define WR_t    INSN_WRITE_RAD_T
 #define WR_31   INSN_WRITE_GPR_31
 #define WR_D    INSN_WRITE_FPR_D
 #define WR_T	INSN_WRITE_FPR_T
 #define WR_S	INSN_WRITE_FPR_S
-#define RD_s    INSN_READ_GPR_S
-#define RD_b    INSN_READ_GPR_S
-#define RD_t    INSN_READ_GPR_T
+#define RD_s    INSN_READ_RAD_S
+#define RD_b    INSN_READ_RAD_S
+#define RD_t    INSN_READ_RAD_T
 #define RD_S    INSN_READ_FPR_S
 #define RD_T    INSN_READ_FPR_T
 #define RD_R	INSN_READ_FPR_R
@@ -166,6 +166,34 @@
 /* MIPS MT ASE support.  */
 #define MT32	INSN_MT
 
+/* pinfo2 */
+#define TWORD_LOAD      INSN2_TWORD_LOAD
+#define TWORD_USE       INSN2_TWORD_USE
+
+/* RLX pinfo */
+#define RD_LXC0 INSN_COP
+#define WR_LXC0 INSN_COP
+
+#define WRAD_d  INSN_WRITE_RAD_D
+#define WRAD_t  INSN_WRITE_RAD_T
+#define RRAD_d  INSN_READ_RAD_D
+#define RRAD_t  INSN_READ_RAD_T
+#define RRAD_s  INSN_READ_RAD_S
+
+/* simplify opcode listing */
+#define RALL    INSN_RLX_ALL
+#define RUDI    INSN_RLX_UDI
+#define RT      INSN_RLX_TAROKO
+#define RAD1    INSN_RLX_RAD1
+#define RAD2    INSN_RLX_RAD2
+#define I2_R    INSN_ISA2_RLX
+#define I32_R   INSN_ISA32_RALL
+
+/* for ltw */
+#define R4181   INSN_RLX4181
+#define R4281   INSN_RLX4281
+
+
 /* Loongson support.  */
 #define WR_z	INSN2_WRITE_GPR_Z
 #define WR_Z	INSN2_WRITE_FPR_Z
@@ -195,1891 +223,962 @@ const struct mips_opcode mips_builtin_op
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,    args,	match,	    mask,	pinfo,          	pinfo2,		membership */
-{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	0,		I4_32|G3	},
-{"pref",    "k,A(b)",	0,    (int) M_PREF_AB,	INSN_MACRO,		0,		I4_32|G3	},
-{"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,		0,		I4_33	},
-{"nop",     "",         0x00000000, 0xffffffff, 0,              	INSN2_ALIAS,	I1      }, /* sll */
-{"ssnop",   "",         0x00000040, 0xffffffff, 0,              	INSN2_ALIAS,	I1	}, /* sll */
-{"ehb",     "",         0x000000c0, 0xffffffff, 0,              	INSN2_ALIAS,	I1	}, /* sll */
-{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,			INSN2_ALIAS,	I1	}, /* addiu */
-{"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,			INSN2_ALIAS,	I1	}, /* ori */
-{"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,		0,		I1	},
-{"move",    "d,s",	0,    (int) M_MOVE,	INSN_MACRO,		0,		I1	},
-{"move",    "d,s",	0x0000002d, 0xfc1f07ff, WR_d|RD_s,		INSN2_ALIAS,	I3	},/* daddu */
-{"move",    "d,s",	0x00000021, 0xfc1f07ff, WR_d|RD_s,		INSN2_ALIAS,	I1	},/* addu */
-{"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,		INSN2_ALIAS,	I1	},/* or */
-{"b",       "p",	0x10000000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1	},/* beq 0,0 */
-{"b",       "p",	0x04010000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1	},/* bgez 0 */
-{"bal",     "p",	0x04110000, 0xffff0000,	UBD|WR_31,		INSN2_ALIAS,	I1	},/* bgezal 0*/
-
-/* Loongson specific instructions.  Loongson 3A redefines the Coprocessor 2
-   instructions.  Put them here so that disassembler will find them first.
-   The assemblers uses a hash table based on the instruction name anyhow.  */
-{"campi",	"d,s",		0x70000075,	0xfc1f07ff,	WR_d|RD_s,	0,	IL3A	},
-{"campv",	"d,s",		0x70000035,	0xfc1f07ff,	WR_d|RD_s,	0,	IL3A	},
-{"camwi",	"d,s,t",	0x700000b5,	0xfc0007ff,	RD_s|RD_t,	RD_d,	IL3A	},
-{"ramri",	"d,s",		0x700000f5,	0xfc1f07ff,	WR_d|RD_s,	0,	IL3A	},
-{"gsle",	"s,t",		0x70000026,	0xfc00ffff,	RD_s|RD_t,	0,	IL3A	},
-{"gsgt",	"s,t",		0x70000027,	0xfc00ffff,	RD_s|RD_t,	0,	IL3A	},
-{"gslble",	"t,b,d",	0xc8000010,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gslbgt",	"t,b,d",	0xc8000011,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gslhle",	"t,b,d",	0xc8000012,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gslhgt",	"t,b,d",	0xc8000013,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gslwle",	"t,b,d",	0xc8000014,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gslwgt",	"t,b,d",	0xc8000015,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gsldle",	"t,b,d",	0xc8000016,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gsldgt",	"t,b,d",	0xc8000017,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gssble",	"t,b,d",	0xe8000010,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gssbgt",	"t,b,d",	0xe8000011,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gsshle",	"t,b,d",	0xe8000012,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gsshgt",	"t,b,d",	0xe8000013,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gsswle",	"t,b,d",	0xe8000014,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gsswgt",	"t,b,d",	0xe8000015,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gssdle",	"t,b,d",	0xe8000016,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gssdgt",	"t,b,d",	0xe8000017,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gslwlec1",	"T,b,d",	0xc8000018,	0xfc0007ff,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
-{"gslwgtc1",	"T,b,d",	0xc8000019,	0xfc0007ff,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
-{"gsldlec1",	"T,b,d",	0xc800001a,	0xfc0007ff,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
-{"gsldgtc1",	"T,b,d",	0xc800001b,	0xfc0007ff,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
-{"gsswlec1",	"T,b,d",	0xe800001c,	0xfc0007ff,	RD_T|RD_b|SM,	RD_d,	IL3A	},
-{"gsswgtc1",	"T,b,d",	0xe800001d,	0xfc0007ff,	RD_T|RD_b|SM,	RD_d,	IL3A	},
-{"gssdlec1",	"T,b,d",	0xe800001e,	0xfc0007ff,	RD_T|RD_b|SM,	RD_d,	IL3A	},
-{"gssdgtc1",	"T,b,d",	0xe800001f,	0xfc0007ff,	RD_T|RD_b|SM,	RD_d,	IL3A	},
-{"gslwlc1",	"T,+a(b)",	0xc8000004,	0xfc00c03f,	WR_T|RD_b|LDD,	0,	IL3A	},
-{"gslwrc1",	"T,+a(b)",	0xc8000005,	0xfc00c03f,	WR_T|RD_b|LDD,	0,	IL3A	},
-{"gsldlc1",	"T,+a(b)",	0xc8000006,	0xfc00c03f,	WR_T|RD_b|LDD,	0,	IL3A	},
-{"gsldrc1",	"T,+a(b)",	0xc8000007,	0xfc00c03f,	WR_T|RD_b|LDD,	0,	IL3A	},
-{"gsswlc1",	"T,+a(b)",	0xe8000004,	0xfc00c03f,	RD_T|RD_b|SM,	0,	IL3A	},
-{"gsswrc1",	"T,+a(b)",	0xe8000005,	0xfc00c03f,	RD_T|RD_b|SM,	0,	IL3A	},
-{"gssdlc1",	"T,+a(b)",	0xe8000006,	0xfc00c03f,	RD_T|RD_b|SM,	0,	IL3A	},
-{"gssdrc1",	"T,+a(b)",	0xe8000007,	0xfc00c03f,	RD_T|RD_b|SM,	0,	IL3A	},
-{"gslbx",	"t,+b(b,d)",	0xd8000000,	0xfc000007,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gslhx",	"t,+b(b,d)",	0xd8000001,	0xfc000007,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gslwx",	"t,+b(b,d)",	0xd8000002,	0xfc000007,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gsldx",	"t,+b(b,d)",	0xd8000003,	0xfc000007,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
-{"gssbx",	"t,+b(b,d)",	0xf8000000,	0xfc000007,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gsshx",	"t,+b(b,d)",	0xf8000001,	0xfc000007,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gsswx",	"t,+b(b,d)",	0xf8000002,	0xfc000007,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gssdx",	"t,+b(b,d)",	0xf8000003,	0xfc000007,	RD_t|RD_b|SM,	RD_d,	IL3A	},
-{"gslwxc1",	"T,+b(b,d)",	0xd8000006,	0xfc000007,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
-{"gsldxc1",	"T,+b(b,d)",	0xd8000007,	0xfc000007,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
-{"gsswxc1",	"T,+b(b,d)",	0xf8000006,	0xfc000007,	RD_T|RD_b|SM,	RD_d,	IL3A	},
-{"gssdxc1",	"T,+b(b,d)",	0xf8000007,	0xfc000007,	RD_T|RD_b|SM,	RD_d,	IL3A	},
-{"gslq",	"+z,t,+c(b)",	0xc8000020,	0xfc008020,	WR_t|RD_b|LDD,	WR_z,	IL3A	},
-{"gssq",	"+z,t,+c(b)",	0xe8000020,	0xfc008020,	RD_t|RD_b|SM,	RD_z,	IL3A	},
-{"gslqc1",	"+Z,T,+c(b)",	0xc8008020,	0xfc008020,	WR_T|RD_b|LDD,	WR_Z,	IL3A	},
-{"gssqc1",	"+Z,T,+c(b)",	0xe8008020,	0xfc008020,	RD_T|RD_b|SM,	RD_Z,	IL3A	},
-
-{"abs",     "d,v",	0,    (int) M_ABS,	INSN_MACRO,		0,		I1	},
-{"abs.s",   "D,V",	0x46000005, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
-{"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
-{"abs.ps",  "D,V",	0x46c00005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5_33|IL2F	},
-{"abs.ps",  "D,V",	0x45600005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		IL2E	},
-{"aclr",    "\\,~(b)",	0x04070000, 0xfc1f8000,	SM|RD_b|NODS,		0,		MC	},
-{"aclr",    "\\,o(b)",	0,    (int) M_ACLR_OB,	INSN_MACRO,		0,		MC	},
-{"aclr",    "\\,A(b)",	0,    (int) M_ACLR_AB,	INSN_MACRO,		0,		MC	},
-{"add",     "d,v,t",	0x00000020, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"add",     "t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		0,		I1	},
-{"add",	"D,S,T",	0x45c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"add",	"D,S,T",	0x4b40000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
-{"add.s",   "D,V,T",	0x46000000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
-{"add.d",   "D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
-{"add.ob",  "X,Y,Q",	0x7800000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"add.ob",  "D,S,T",	0x4ac0000b, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"add.ob",  "D,S,T[e]",	0x4800000b, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"add.ob",  "D,S,k",	0x4bc0000b, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"add.ps",  "D,V,T",	0x46c00000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33|IL2F	},
-{"add.ps",  "D,V,T",	0x45600000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		IL2E	},
-{"add.qh",  "X,Y,Q",	0x7820000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"adda.ob", "Y,Q",	0x78000037, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
-{"adda.qh", "Y,Q",	0x78200037, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"addi",    "t,r,j",	0x20000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
-{"addiu",   "t,r,j",	0x24000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
-{"addl.ob", "Y,Q",	0x78000437, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
-{"addl.qh", "Y,Q",	0x78200437, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"addr.ps", "D,S,T",	0x46c00018, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		M3D	},
-{"addu",    "d,v,t",	0x00000021, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"addu",    "t,r,I",	0,    (int) M_ADDU_I,	INSN_MACRO,		0,		I1	},
-{"addu",	"D,S,T",	0x45800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"addu",	"D,S,T",	0x4b00000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
-{"alni.ob", "X,Y,Z,O",	0x78000018, 0xff00003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"alni.ob", "D,S,T,%",	0x48000018, 0xff00003f,	WR_D|RD_S|RD_T, 	0,		N54	},
-{"alni.qh", "X,Y,Z,O",	0x7800001a, 0xff00003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"alnv.ps", "D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		I5_33	},
-{"alnv.ob", "X,Y,Z,s",	0x78000019, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		MX|SB1	},
-{"alnv.qh", "X,Y,Z,s",	0x7800001b, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		MX	},
-{"and",     "d,v,t",	0x00000024, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"and",     "t,r,I",	0,    (int) M_AND_I,	INSN_MACRO,		0,		I1	},
-{"and",	"D,S,T",	0x47c00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"and",	"D,S,T",	0x4bc00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"and.ob",  "X,Y,Q",	0x7800000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"and.ob",  "D,S,T",	0x4ac0000c, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"and.ob",  "D,S,T[e]",	0x4800000c, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"and.ob",  "D,S,k",	0x4bc0000c, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"and.qh",  "X,Y,Q",	0x7820000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"andi",    "t,r,i",	0x30000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
-{"aset",    "\\,~(b)",	0x04078000, 0xfc1f8000,	SM|RD_b|NODS,		0,		MC	},
-{"aset",    "\\,o(b)",	0,    (int) M_ASET_OB,	INSN_MACRO,		0,		MC	},
-{"aset",    "\\,A(b)",	0,    (int) M_ASET_AB,	INSN_MACRO,		0,		MC	},
-{"baddu",   "d,v,t",	0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT	},
+{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,       0,    	I4_32 },
+{"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,	0,    	I4_33 },
+{"nop",     "",         0x00000000, 0xffffffff, 0,          INSN2_ALIAS,	I1  }, /* sll */
+{"ssnop",   "",         0x00000040, 0xffffffff, 0,          INSN2_ALIAS,	I32 }, /* sll */
+{"ssnop",   "",         0x00000040, 0xffffffff, 0,          INSN2_ALIAS,	RT  }, /* sll */
+
+{"ehb",     "",         0x000000c0, 0xffffffff, 0,          INSN2_ALIAS,	I33 }, /* sll */
+{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,		INSN2_ALIAS,	I1 }, /* addiu */
+{"li",	    "t,i",      0x34000000, 0xffe00000, WR_t,			INSN2_ALIAS,	I1 }, /* ori */
+{"li",      "t,I",      0,    (int) M_LI,	    INSN_MACRO,		0,    	I1 },
+{"move",    "d,s",      0,    (int) M_MOVE,	    INSN_MACRO,		0,    		I1 },
+{"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,		INSN2_ALIAS,	I3 },/* daddu */
+{"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,		INSN2_ALIAS,	I1 },/* addu */
+{"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,		INSN2_ALIAS,	I1 },/* or */
+{"b",       "p",        0x10000000, 0xffff0000, UBD,			INSN2_ALIAS,	I1 },/* beq 0,0 */
+{"b",       "p",        0x04010000, 0xffff0000, UBD,			INSN2_ALIAS,	I1 },/* bgez 0 */
+{"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,		INSN2_ALIAS,	I1 },/* bgezal 0*/
+
+{"abs",     "d,v",      0,    (int) M_ABS,	    INSN_MACRO,		0,    		I1 },
+{"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,		0,    		I1 },
+{"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,		0,    		I1 },
+{"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,		0,    		I5 },
+{"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,		0,    		I1 },
+{"add",     "t,r,I",    0,    (int) M_ADD_I,	INSN_MACRO,		0,    		I1 },
+{"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,	0,    		I1 },
+{"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,    		I1 },
+{"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,    		I5 },
+{"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,		0,    		I1 },
+{"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,		0,    		I1 },
+{"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,		0,    		I1 },
+{"addu",    "t,r,I",    0,    (int) M_ADDU_I,	INSN_MACRO,		0,    		I1 },
+{"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,	0,    		I5 },
+{"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,		0,    		I1 },
+{"and",     "t,r,I",    0,    (int) M_AND_I,	INSN_MACRO,		0,		I1 },
+{"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,		0,		I1 },
 /* b is at the top of the table.  */
 /* bal is at the top of the table.  */
-{"bbit032", "s,+x,p",	0xd8000000, 0xfc000000, RD_s|CBD,		0,		IOCT	},
-{"bbit0",   "s,+X,p",	0xd8000000, 0xfc000000, RD_s|CBD,		0,		IOCT	}, /* bbit032 */
-{"bbit0",   "s,+x,p",	0xc8000000, 0xfc000000, RD_s|CBD,		0,		IOCT	},
-{"bbit132", "s,+x,p",	0xf8000000, 0xfc000000, RD_s|CBD,		0,		IOCT	},
-{"bbit1",   "s,+X,p",	0xf8000000, 0xfc000000, RD_s|CBD,		0,		IOCT	}, /* bbit132 */
-{"bbit1",   "s,+x,p",	0xe8000000, 0xfc000000, RD_s|CBD,		0,		IOCT	},
 /* bc0[tf]l? are at the bottom of the table.  */
-{"bc1any2f", "N,p",	0x45200000, 0xffe30000,	CBD|RD_CC|FP_S,		0,		M3D	},
-{"bc1any2t", "N,p",	0x45210000, 0xffe30000,	CBD|RD_CC|FP_S,		0,		M3D	},
-{"bc1any4f", "N,p",	0x45400000, 0xffe30000,	CBD|RD_CC|FP_S,		0,		M3D	},
-{"bc1any4t", "N,p",	0x45410000, 0xffe30000,	CBD|RD_CC|FP_S,		0,		M3D	},
-{"bc1f",    "p",	0x45000000, 0xffff0000,	CBD|RD_CC|FP_S,		0,		I1	},
-{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 	0,		I4_32	},
-{"bc1fl",   "p",	0x45020000, 0xffff0000,	CBL|RD_CC|FP_S,		0,		I2|T3	},
-{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 	0,		I4_32	},
-{"bc1t",    "p",	0x45010000, 0xffff0000,	CBD|RD_CC|FP_S,		0,		I1	},
-{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 	0,		I4_32	},
-{"bc1tl",   "p",	0x45030000, 0xffff0000,	CBL|RD_CC|FP_S,		0,		I2|T3	},
-{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 	0,		I4_32	},
+{"bc1f",    "p",        0x45000000, 0xffff0000,	CBD|RD_CC|FP_S,		0,		I1},
+{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 	0,		I4_32 },
+{"bc1fl",   "p",        0x45020000, 0xffff0000,	CBL|RD_CC|FP_S,		0,		I2 },
+{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 	0,		I4_32 },
+{"bc1t",    "p",        0x45010000, 0xffff0000,	CBD|RD_CC|FP_S,		0,		I1},
+{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 	0,		I4_32 },
+{"bc1tl",   "p",        0x45030000, 0xffff0000,	CBL|RD_CC|FP_S,		0,		I2 },
+{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 	0,		I4_32 },
+{"bc2f",    "p",        0x49000000, 0xffff0000,	CBD|RD_CC,		0,		I1 },
+{"bc2fl",   "p",        0x49020000, 0xffff0000,	CBL|RD_CC,		0,		I2 },
+{"bc2t",    "p",        0x49010000, 0xffff0000,	CBD|RD_CC,		0,		I1 },
+{"bc2tl",   "p",        0x49030000, 0xffff0000,	CBL|RD_CC,		0,		I2 },
+{"bc3f",    "p",        0x4d000000, 0xffff0000,	CBD|RD_CC,		0,		I1 },
+{"bc3fl",   "p",        0x4d020000, 0xffff0000,	CBL|RD_CC,		0,		I2 },
+{"bc3t",    "p",        0x4d010000, 0xffff0000,	CBD|RD_CC,		0,		I1 },
+{"bc3tl",   "p",        0x4d030000, 0xffff0000,	CBL|RD_CC,		0,		I2 },
 /* bc2* are at the bottom of the table.  */
 /* bc3* are at the bottom of the table.  */
-{"beqz",    "s,p",	0x10000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
-{"beqzl",   "s,p",	0x50000000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
-{"beq",     "s,t,p",	0x10000000, 0xfc000000,	CBD|RD_s|RD_t,		0,		I1	},
-{"beq",     "s,I,p",	0,    (int) M_BEQ_I,	INSN_MACRO,		0,		I1	},
-{"beql",    "s,t,p",	0x50000000, 0xfc000000,	CBL|RD_s|RD_t,		0,		I2|T3	},
-{"beql",    "s,I,p",	0,    (int) M_BEQL_I,	INSN_MACRO,		0,		I2|T3	},
-{"bge",     "s,t,p",	0,    (int) M_BGE,	INSN_MACRO,		0,		I1	},
-{"bge",     "s,I,p",	0,    (int) M_BGE_I,	INSN_MACRO,		0,		I1	},
-{"bgel",    "s,t,p",	0,    (int) M_BGEL,	INSN_MACRO,		0,		I2|T3	},
-{"bgel",    "s,I,p",	0,    (int) M_BGEL_I,	INSN_MACRO,		0,		I2|T3	},
-{"bgeu",    "s,t,p",	0,    (int) M_BGEU,	INSN_MACRO,		0,		I1	},
-{"bgeu",    "s,I,p",	0,    (int) M_BGEU_I,	INSN_MACRO,		0,		I1	},
-{"bgeul",   "s,t,p",	0,    (int) M_BGEUL,	INSN_MACRO,		0,		I2|T3	},
-{"bgeul",   "s,I,p",	0,    (int) M_BGEUL_I,	INSN_MACRO,		0,		I2|T3	},
-{"bgez",    "s,p",	0x04010000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
-{"bgezl",   "s,p",	0x04030000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
-{"bgezal",  "s,p",	0x04110000, 0xfc1f0000,	CBD|RD_s|WR_31,		0,		I1	},
-{"bgezall", "s,p",	0x04130000, 0xfc1f0000,	CBL|RD_s|WR_31,		0,		I2|T3	},
-{"bgt",     "s,t,p",	0,    (int) M_BGT,	INSN_MACRO,		0,		I1	},
-{"bgt",     "s,I,p",	0,    (int) M_BGT_I,	INSN_MACRO,		0,		I1	},
-{"bgtl",    "s,t,p",	0,    (int) M_BGTL,	INSN_MACRO,		0,		I2|T3	},
-{"bgtl",    "s,I,p",	0,    (int) M_BGTL_I,	INSN_MACRO,		0,		I2|T3	},
-{"bgtu",    "s,t,p",	0,    (int) M_BGTU,	INSN_MACRO,		0,		I1	},
-{"bgtu",    "s,I,p",	0,    (int) M_BGTU_I,	INSN_MACRO,		0,		I1	},
-{"bgtul",   "s,t,p",	0,    (int) M_BGTUL,	INSN_MACRO,		0,		I2|T3	},
-{"bgtul",   "s,I,p",	0,    (int) M_BGTUL_I,	INSN_MACRO,		0,		I2|T3	},
-{"bgtz",    "s,p",	0x1c000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
-{"bgtzl",   "s,p",	0x5c000000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
-{"ble",     "s,t,p",	0,    (int) M_BLE,	INSN_MACRO,		0,		I1	},
-{"ble",     "s,I,p",	0,    (int) M_BLE_I,	INSN_MACRO,		0,		I1	},
-{"blel",    "s,t,p",	0,    (int) M_BLEL,	INSN_MACRO,		0,		I2|T3	},
-{"blel",    "s,I,p",	0,    (int) M_BLEL_I,	INSN_MACRO,		0,		I2|T3	},
-{"bleu",    "s,t,p",	0,    (int) M_BLEU,	INSN_MACRO,		0,		I1	},
-{"bleu",    "s,I,p",	0,    (int) M_BLEU_I,	INSN_MACRO,		0,		I1	},
-{"bleul",   "s,t,p",	0,    (int) M_BLEUL,	INSN_MACRO,		0,		I2|T3	},
-{"bleul",   "s,I,p",	0,    (int) M_BLEUL_I,	INSN_MACRO,		0,		I2|T3	},
-{"blez",    "s,p",	0x18000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
-{"blezl",   "s,p",	0x58000000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
-{"blt",     "s,t,p",	0,    (int) M_BLT,	INSN_MACRO,		0,		I1	},
-{"blt",     "s,I,p",	0,    (int) M_BLT_I,	INSN_MACRO,		0,		I1	},
-{"bltl",    "s,t,p",	0,    (int) M_BLTL,	INSN_MACRO,		0,		I2|T3	},
-{"bltl",    "s,I,p",	0,    (int) M_BLTL_I,	INSN_MACRO,		0,		I2|T3	},
-{"bltu",    "s,t,p",	0,    (int) M_BLTU,	INSN_MACRO,		0,		I1	},
-{"bltu",    "s,I,p",	0,    (int) M_BLTU_I,	INSN_MACRO,		0,		I1	},
-{"bltul",   "s,t,p",	0,    (int) M_BLTUL,	INSN_MACRO,		0,		I2|T3	},
-{"bltul",   "s,I,p",	0,    (int) M_BLTUL_I,	INSN_MACRO,		0,		I2|T3	},
-{"bltz",    "s,p",	0x04000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
-{"bltzl",   "s,p",	0x04020000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
-{"bltzal",  "s,p",	0x04100000, 0xfc1f0000,	CBD|RD_s|WR_31,		0,		I1	},
-{"bltzall", "s,p",	0x04120000, 0xfc1f0000,	CBL|RD_s|WR_31,		0,		I2|T3	},
-{"bnez",    "s,p",	0x14000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
-{"bnezl",   "s,p",	0x54000000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
-{"bne",     "s,t,p",	0x14000000, 0xfc000000,	CBD|RD_s|RD_t,		0,		I1	},
-{"bne",     "s,I,p",	0,    (int) M_BNE_I,	INSN_MACRO,		0,		I1	},
-{"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 		0,		I2|T3	},
-{"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		0,		I2|T3	},
-{"break",   "",		0x0000000d, 0xffffffff,	TRAP,			0,		I1	},
-{"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,			0,		I1	},
-{"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,			0,		I1	},
-{"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
+{"beqz",    "s,p",      0x10000000, 0xfc1f0000,	CBD|RD_s,		0,		I1 },
+{"beqzl",   "s,p",      0x50000000, 0xfc1f0000,	CBL|RD_s,		0,		I2 },
+{"beq",     "s,t,p",    0x10000000, 0xfc000000,	CBD|RD_s|RD_t,		0,		I1 },
+{"beq",     "s,I,p",    0,    (int) M_BEQ_I,	INSN_MACRO,		0,		I1 },
+{"beql",    "s,t,p",    0x50000000, 0xfc000000,	CBL|RD_s|RD_t,		0,		I2 },
+{"beql",    "s,I,p",    0,    (int) M_BEQL_I,	INSN_MACRO,		0,		I2 },
+{"bge",     "s,t,p",    0,    (int) M_BGE,	INSN_MACRO,		0,		I1 },
+{"bge",     "s,I,p",    0,    (int) M_BGE_I,	INSN_MACRO,		0,		I1 },
+{"bgel",    "s,t,p",    0,    (int) M_BGEL,	INSN_MACRO,		0,		I2 },
+{"bgel",    "s,I,p",    0,    (int) M_BGEL_I,	INSN_MACRO,		0,		I2 },
+{"bgeu",    "s,t,p",    0,    (int) M_BGEU,	INSN_MACRO,		0,		I1 },
+{"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,	INSN_MACRO,		0,		I1 },
+{"bgeul",   "s,t,p",    0,    (int) M_BGEUL,	INSN_MACRO,		0,		I2 },
+{"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,	INSN_MACRO,		0,		I2 },
+{"bgez",    "s,p",    0x04010000, 0xfc1f0000,	CBD|RD_s,		0,		I1 },
+{"bgezl",   "s,p",    0x04030000, 0xfc1f0000,	CBL|RD_s,		0,		I2 },
+{"bgezal",  "s,p",    0x04110000, 0xfc1f0000,	CBD|RD_s|WR_31,		0,		I1 },
+{"bgezall", "s,p",    0x04130000, 0xfc1f0000,	CBL|RD_s|WR_31,		0,		I2 },
+{"bgt",     "s,t,p",    0,    (int) M_BGT,	INSN_MACRO,		0,		I1 },
+{"bgt",     "s,I,p",    0,    (int) M_BGT_I,	INSN_MACRO,		0,		I1 },
+{"bgtl",    "s,t,p",    0,    (int) M_BGTL,	INSN_MACRO,		0,		I2 },
+{"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,	INSN_MACRO,		0,		I2 },
+{"bgtu",    "s,t,p",    0,    (int) M_BGTU,	INSN_MACRO,		0,		I1 },
+{"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,	INSN_MACRO,		0,		I1 },
+{"bgtul",   "s,t,p",    0,    (int) M_BGTUL,	INSN_MACRO,		0,		I2 },
+{"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,	INSN_MACRO,		0,		I2 },
+{"bgtz",    "s,p",    0x1c000000, 0xfc1f0000,	CBD|RD_s,		0,		I1 },
+{"bgtzl",   "s,p",    0x5c000000, 0xfc1f0000,	CBL|RD_s,		0,		I2 },
+{"ble",     "s,t,p",    0,    (int) M_BLE,	INSN_MACRO,		0,		I1 },
+{"ble",     "s,I,p",    0,    (int) M_BLE_I,	INSN_MACRO,		0,		I1 },
+{"blel",    "s,t,p",    0,    (int) M_BLEL,	INSN_MACRO,		0,		I2 },
+{"blel",    "s,I,p",    0,    (int) M_BLEL_I,	INSN_MACRO,		0,		I2 },
+{"bleu",    "s,t,p",    0,    (int) M_BLEU,	INSN_MACRO,		0,		I1 },
+{"bleu",    "s,I,p",    0,    (int) M_BLEU_I,	INSN_MACRO,		0,		I1 },
+{"bleul",   "s,t,p",    0,    (int) M_BLEUL,	INSN_MACRO,		0,		I2 },
+{"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,	INSN_MACRO,		0,		I2 },
+{"blez",    "s,p",    0x18000000, 0xfc1f0000,	CBD|RD_s,		0,		I1 },
+{"blezl",   "s,p",    0x58000000, 0xfc1f0000,	CBL|RD_s,		0,		I2 },
+{"blt",     "s,t,p",    0,    (int) M_BLT,	INSN_MACRO,		0,		I1 },
+{"blt",     "s,I,p",    0,    (int) M_BLT_I,	INSN_MACRO,		0,		I1 },
+{"bltl",    "s,t,p",    0,    (int) M_BLTL,	INSN_MACRO,		0,		I2 },
+{"bltl",    "s,I,p",    0,    (int) M_BLTL_I,	INSN_MACRO,		0,		I2 },
+{"bltu",    "s,t,p",    0,    (int) M_BLTU,	INSN_MACRO,		0,		I1 },
+{"bltu",    "s,I,p",    0,    (int) M_BLTU_I,	INSN_MACRO,		0,		I1 },
+{"bltul",   "s,t,p",	0,    (int) M_BLTUL,	INSN_MACRO,		0,		I2 },
+{"bltul",   "s,I,p",	0,    (int) M_BLTUL_I,	INSN_MACRO,		0,		I2 },
+{"bltz",    "s,p",	0x04000000, 0xfc1f0000,	CBD|RD_s,		0,		I1 },
+{"bltzl",   "s,p",	0x04020000, 0xfc1f0000,	CBL|RD_s,		0,		I2 },
+{"bltzal",  "s,p",	0x04100000, 0xfc1f0000,	CBD|RD_s|WR_31,		0,		I1 },
+{"bltzall", "s,p",	0x04120000, 0xfc1f0000,	CBL|RD_s|WR_31,		0,		I2 },
+{"bnez",    "s,p",	0x14000000, 0xfc1f0000,	CBD|RD_s,		0,		I1 },
+{"bnezl",   "s,p",	0x54000000, 0xfc1f0000,	CBL|RD_s,		0,		I2 },
+{"bne",     "s,t,p",	0x14000000, 0xfc000000,	CBD|RD_s|RD_t,		0,		I1 },
+{"bne",     "s,I,p",	0,    (int) M_BNE_I,	INSN_MACRO,		0,		I1 },
+{"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 		0,		I2 },
+{"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		0,		I2 },
+{"break",   "",		0x0000000d, 0xffffffff, TRAP,			0,		I1 },
+{"break",   "c",	0x0000000d, 0xfc00ffff, TRAP,			0,		I1 },
+{"break",   "c,q",	0x0000000d, 0xfc00003f, TRAP,			0,		I1 },
+{"c.f.d",   "S,T",	0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.f.ps",  "S,T",	0x46c00030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.f.ps",  "S,T",	0x45600030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.f.ps",  "M,S,T",	0x46c00030, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.un.d",  "S,T",	0x46200031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
+{"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.f.ps",  "S,T",	0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.f.ps",  "M,S,T",	0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.un.d",  "S,T",	0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.un.ps", "S,T",	0x46c00031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.un.ps", "S,T",	0x45600031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.un.ps", "M,S,T",	0x46c00031, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.eq.d",  "S,T",	0x46200032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
+{"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.un.ps", "S,T",	0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.un.ps", "M,S,T",	0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.eq.d",  "S,T",	0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.eq.ob", "Y,Q",	0x78000001, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"c.eq.ob", "S,T",	0x4ac00001, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.eq.ob", "S,T[e]",	0x48000001, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.eq.ob", "S,k",	0x4bc00001, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.eq.ps", "S,T",	0x46c00032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.eq.ps", "S,T",	0x45600032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.eq.ps", "M,S,T",	0x46c00032, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.eq.qh", "Y,Q",	0x78200001, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
-{"c.ueq.d", "S,T",	0x46200033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
+{"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.eq.ps", "S,T",	0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.eq.ps", "M,S,T",	0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ueq.d", "S,T",	0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.ueq.ps","S,T",	0x46c00033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.ueq.ps","S,T",	0x45600033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.ueq.ps","M,S,T",	0x46c00033, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
+{"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.ueq.ps","S,T",	0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ueq.ps","M,S,T",	0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1      },
-{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.olt.s", "S,T",	0x46000034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
-{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.olt.ps","S,T",	0x46c00034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.olt.ps","S,T",	0x45600034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.olt.ps","M,S,T",	0x46c00034, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ult.d", "S,T",	0x46200035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
+{"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
+{"c.olt.s", "S,T",	0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,	0,		I1 },
+{"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.olt.ps","S,T",	0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.olt.ps","M,S,T",	0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ult.d", "S,T",	0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.ult.ps","S,T",	0x46c00035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.ult.ps","S,T",	0x45600035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.ult.ps","M,S,T",	0x46c00035, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1      },
-{"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.ole.ps","S,T",	0x46c00036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.ole.ps","S,T",	0x45600036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.ole.ps","M,S,T",	0x46c00036, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ule.d", "S,T",	0x46200037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.ule.ps","S,T",	0x46c00037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.ule.ps","S,T",	0x45600037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.ule.ps","M,S,T",	0x46c00037, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.sf.d",  "S,T",	0x46200038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.sf.ps", "S,T",	0x46c00038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.sf.ps", "S,T",	0x45600038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.sf.ps", "M,S,T",	0x46c00038, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ngle.d","S,T",	0x46200039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.ngle.ps","S,T",	0x46c00039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.ngle.ps","S,T",	0x45600039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.ngle.ps","M,S,T",	0x46c00039, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.seq.d", "S,T",	0x4620003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.seq.ps","S,T",	0x46c0003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.seq.ps","S,T",	0x4560003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.seq.ps","M,S,T",	0x46c0003a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.ngl.d", "S,T",	0x4620003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.ngl.ps","S,T",	0x46c0003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.ngl.ps","S,T",	0x4560003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.ngl.ps","M,S,T",	0x46c0003b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.lt.d",  "S,T",	0x4620003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.lt.s",  "S,T",	0x4600003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
-{"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.lt.ob", "Y,Q",	0x78000004, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"c.lt.ob", "S,T",	0x4ac00004, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.lt.ob", "S,T[e]",	0x48000004, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.lt.ob", "S,k",	0x4bc00004, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.lt.ps", "S,T",	0x46c0003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.lt.ps", "S,T",	0x4560003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.lt.ps", "M,S,T",	0x46c0003c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.lt.qh", "Y,Q",	0x78200004, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
-{"c.nge.d", "S,T",	0x4620003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.nge.ps","S,T",	0x46c0003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.nge.ps","S,T",	0x4560003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.nge.ps","M,S,T",	0x46c0003d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.le.d",  "S,T",	0x4620003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.le.s",  "S,T",	0x4600003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
-{"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.le.ob", "Y,Q",	0x78000005, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"c.le.ob", "S,T",	0x4ac00005, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.le.ob", "S,T[e]",	0x48000005, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.le.ob", "S,k",	0x4bc00005, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"c.le.ps", "S,T",	0x46c0003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.le.ps", "S,T",	0x4560003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.le.ps", "M,S,T",	0x46c0003e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"c.le.qh", "Y,Q",	0x78200005, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
-{"c.ngt.d", "S,T",	0x4620003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
-{"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32	},
-{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
-{"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32	},
-{"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
-{"c.ngt.ps","S,T",	0x4560003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
-{"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
-{"cabs.eq.d",  "M,S,T",	0x46200072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.eq.ps", "M,S,T",	0x46c00072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.eq.s",  "M,S,T",	0x46000072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.f.d",   "M,S,T",	0x46200070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.f.ps",  "M,S,T",	0x46c00070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.f.s",   "M,S,T",	0x46000070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.le.d",  "M,S,T",	0x4620007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.le.ps", "M,S,T",	0x46c0007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.le.s",  "M,S,T",	0x4600007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.lt.d",  "M,S,T",	0x4620007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.lt.ps", "M,S,T",	0x46c0007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.lt.s",  "M,S,T",	0x4600007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.nge.d", "M,S,T",	0x4620007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.nge.ps","M,S,T",	0x46c0007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.nge.s", "M,S,T",	0x4600007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.ngl.d", "M,S,T",	0x4620007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ngl.ps","M,S,T",	0x46c0007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ngl.s", "M,S,T",	0x4600007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.ngle.d","M,S,T",	0x46200079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ngle.s","M,S,T",	0x46000079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.ngt.d", "M,S,T",	0x4620007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ngt.ps","M,S,T",	0x46c0007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ngt.s", "M,S,T",	0x4600007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.ole.d", "M,S,T",	0x46200076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ole.ps","M,S,T",	0x46c00076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ole.s", "M,S,T",	0x46000076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.olt.d", "M,S,T",	0x46200074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.olt.ps","M,S,T",	0x46c00074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.olt.s", "M,S,T",	0x46000074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.seq.d", "M,S,T",	0x4620007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.seq.ps","M,S,T",	0x46c0007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.seq.s", "M,S,T",	0x4600007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.sf.d",  "M,S,T",	0x46200078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.sf.ps", "M,S,T",	0x46c00078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.sf.s",  "M,S,T",	0x46000078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.ueq.d", "M,S,T",	0x46200073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ueq.ps","M,S,T",	0x46c00073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ueq.s", "M,S,T",	0x46000073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.ule.d", "M,S,T",	0x46200077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ule.ps","M,S,T",	0x46c00077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ule.s", "M,S,T",	0x46000077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.ult.d", "M,S,T",	0x46200075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ult.ps","M,S,T",	0x46c00075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.ult.s", "M,S,T",	0x46000075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-{"cabs.un.d",  "M,S,T",	0x46200071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.un.ps", "M,S,T",	0x46c00071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
-{"cabs.un.s",  "M,S,T",	0x46000071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
-/* CW4010 instructions which are aliases for the cache instruction.  */
-{"flushi",  "",		0xbc010000, 0xffffffff, 0,			0,		L1	},
-{"flushd",  "",		0xbc020000, 0xffffffff, 0, 			0,		L1	},
-{"flushid", "",		0xbc030000, 0xffffffff, 0, 			0,		L1	},
-{"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,		0,		L1	},
-{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           	0,		I3_32|T3},
-{"cache",   "k,A(b)",	0,    (int) M_CACHE_AB, INSN_MACRO,		0,		I3_32|T3},
-{"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33	},
-{"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
-{"ceil.w.s", "D,S",	0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
-{"cfc0",    "t,G",	0x40400000, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		I1	},
-{"cfc1",    "t,G",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	0,		I1	},
-{"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	0,		I1	},
-/* cfc2 is at the bottom of the table.  */
-/* cfc3 is at the bottom of the table.  */
-{"cftc1",   "d,E",	0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,		MT32	},
-{"cftc1",   "d,T",	0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,		MT32	},
-{"cftc2",   "d,E",	0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,	0,		MT32	},
-{"cins32",  "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
-{"cins",    "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s,		0,		IOCT	}, /* cins32 */
-{"cins",    "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
-{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 	0,		I32|N55 },
-{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 	0,		I32|N55 },
-{"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1	},
-{"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	0,		I1	},
-{"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	0,		I1	},
-/* ctc2 is at the bottom of the table.  */
-/* ctc3 is at the bottom of the table.  */
-{"cttc1",   "t,g",	0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,		MT32	},
-{"cttc1",   "t,S",	0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,		MT32	},
-{"cttc2",   "t,g",	0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,	0,		MT32	},
-{"cvt.d.l", "D,S",	0x46a00021, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I3_33	},
-{"cvt.d.s", "D,S",	0x46000021, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
-{"cvt.d.w", "D,S",	0x46800021, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
-{"cvt.l.d", "D,S",	0x46200025, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I3_33	},
-{"cvt.l.s", "D,S",	0x46000025, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"cvt.s.l", "D,S",	0x46a00020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"cvt.s.d", "D,S",	0x46200020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
-{"cvt.s.w", "D,S",	0x46800020, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
-{"cvt.s.pl","D,S",	0x46c00028, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I5_33	},
-{"cvt.s.pu","D,S",	0x46c00020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I5_33	},
-{"cvt.w.d", "D,S",	0x46200024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
-{"cvt.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
-{"cvt.ps.pw", "D,S",	0x46800026, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		M3D	},
-{"cvt.ps.s","D,V,T",	0x46000026, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S|FP_D, 0,		I5_33	},
-{"cvt.pw.ps", "D,S",	0x46c00024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		M3D	},
-{"dabs",    "d,v",	0,    (int) M_DABS,	INSN_MACRO,		0,		I3	},
-{"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
-{"dadd",    "t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		0,		I3	},
-{"dadd",	"D,S,T",	0x45e00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dadd",	"D,S,T",	0x4b60000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"daddi",   "t,r,j",	0x60000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
-{"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
-{"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
-{"daddu",   "t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,		0,		I3	},
-{"daddwc",  "d,s,t", 	0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0,	0,	XLR	},
-{"dbreak",  "",		0x7000003f, 0xffffffff,	0,			0,		N5	},
-{"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64|N55 },
-{"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64|N55 },
+{"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.ult.ps","S,T",	0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ult.ps","M,S,T",  0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ole.d", "S,T",    0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1      },
+{"c.ole.d", "M,S,T",  0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
+{"c.ole.s", "S,T",    0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ole.s", "M,S,T",  0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.ole.ps","S,T",    0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ole.ps","M,S,T",  0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ule.d", "S,T",	  0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.ule.d", "M,S,T",  0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
+{"c.ule.s", "S,T",    0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ule.s", "M,S,T",  0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.ule.ps","S,T",    0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ule.ps","M,S,T",  0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.sf.d",  "S,T",    0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.sf.d",  "M,S,T",  0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
+{"c.sf.s",  "S,T",    0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.sf.s",  "M,S,T",  0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.sf.ps", "S,T",    0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.sf.ps", "M,S,T",  0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ngle.d","S,T",    0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.ngle.d","M,S,T",  0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
+{"c.ngle.s","S,T",    0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ngle.s","M,S,T",  0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.ngle.ps","S,T",	  0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.seq.d", "S,T",    0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.seq.d", "M,S,T",  0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
+{"c.seq.s", "S,T",    0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.seq.s", "M,S,T",  0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.seq.ps","S,T",    0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.seq.ps","M,S,T",  0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ngl.d", "S,T",    0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.ngl.d", "M,S,T",  0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
+{"c.ngl.s", "S,T",    0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
+{"c.ngl.s", "M,S,T",  0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.ngl.ps","S,T",    0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.ngl.ps","M,S,T",  0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.lt.d",  "S,T",    0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.lt.d",  "M,S,T",  0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4_32 },
+{"c.lt.s",  "S,T",    0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,	0,		I1 },
+{"c.lt.s",  "M,S,T",  0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32 },
+{"c.lt.ps", "S,T",    0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.lt.ps", "M,S,T",  0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0,		I5 },
+{"c.nge.d", "S,T",	  0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0,		I1 },
+{"c.nge.d", "M,S,T",  0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0,		I4_32 },
+{"c.nge.s", "S,T",    0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1      },
+{"c.nge.s", "M,S,T",  0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 },
+{"c.nge.ps","S,T",    0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0, I5 },
+{"c.nge.ps","M,S,T",  0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0, I5 },
+{"c.le.d",  "S,T",    0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0, I1 },
+{"c.le.d",  "M,S,T",  0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 },
+{"c.le.s",  "S,T",    0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,	0, I1 },
+{"c.le.s",  "M,S,T",  0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 },
+{"c.le.ps", "S,T",    0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0, I5 },
+{"c.le.ps", "M,S,T",  0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0, I5 },
+{"c.ngt.d", "S,T",	  0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0, I1 },
+{"c.ngt.d", "M,S,T",  0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 },
+{"c.ngt.s", "S,T",    0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1      },
+{"c.ngt.s", "M,S,T",  0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 },
+{"c.ngt.ps","S,T",    0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,	0, I5 },
+{"c.ngt.ps","M,S,T",  0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,	0, I5 },
+{"cache",   "k,o(b)", 0xbc000000, 0xfc000000, RD_b,                 0, I3_32},
+{"cache",   "k,o(b)", 0xbc000000, 0xfc000000, RD_b,                 0, RUDI },
+{"cache",   "k,A(b)", 0,    (int) M_CACHE_AB, INSN_MACRO,           0, I3_32 },
+{"ceil.l.d", "D,S",	  0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,		0, I3_33      },
+{"ceil.l.s", "D,S",	  0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,  0, I3_33      },
+{"ceil.w.d", "D,S",	  0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,  0, I2         },
+{"ceil.w.s", "D,S",	  0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,       0, I2 },
+{"cfc0",    "t,G",	  0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,       0, I1 },
+{"cfc0",    "t,G,#H", 0x40400000, 0xffe007c0, LCD|WR_t|RD_C0,       0, RT   },
+{"cfc1",    "t,G",    0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,  0, I1 },
+{"cfc1",    "t,G,#H", 0x44400000, 0xffe007c0, LCD|WR_t|RD_C1|FP_S,  0, RT   },
+{"cfc1",    "t,S",    0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,  0, I1 },
+{"cfc2",    "t,G",    0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,       0, I1 },
+{"cfc2",    "t,G,#H", 0x48400000, 0xffe007c0, LCD|WR_t|RD_C2,       0, RT   },
+{"cfc3",    "t,G",    0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,       0, I1 },
+{"cfc3",    "t,G,#H", 0x4c400000, 0xffe007c0, LCD|WR_t|RD_C3,       0, RT   },
+{"clo",     "U,s",    0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,       0, I32  },
+{"clz",     "U,s",    0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,       0, I32  },
+{"ctc0",    "t,G,#H", 0x40c00000, 0xffe007c0, COD|RD_t|WR_CC,       0, RT   },
+{"ctc0",    "t,G",    0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,       0, I1 },
+{"ctc1",    "t,G",    0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,	0, I1 },
+{"ctc1",    "t,G,#H", 0x44c00000, 0xffe007c0, COD|RD_t|WR_CC|FP_S,	0, RT   },
+{"ctc1",    "t,S",    0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,	0, I1 },
+{"ctc2",    "t,G",    0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,		0, I1 },
+{"ctc2",    "t,G,#H", 0x48c00000, 0xffe007c0, COD|RD_t|WR_CC,		0, RT   },
+{"ctc3",    "t,G",    0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,		0, I1 },
+{"ctc3",    "t,G,#H", 0x4cc00000, 0xffe007c0, COD|RD_t|WR_CC,		0, RT   },
+{"cvt.d.l", "D,S",	0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33 },
+{"cvt.d.s", "D,S",	0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I1 },
+{"cvt.d.w", "D,S",	0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I1 },
+{"cvt.l.d", "D,S",	0x46200025, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33 },
+{"cvt.l.s", "D,S",	0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_S,	0,		I3_33 },
+{"cvt.s.l", "D,S",	0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_S,	0,		I3_33 },
+{"cvt.s.d", "D,S",	0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I1 },
+{"cvt.s.w", "D,S",	0x46800020, 0xffff003f, WR_D|RD_S|FP_S,		0,		I1 },
+{"cvt.s.pl","D,S",	0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I5 },
+{"cvt.s.pu","D,S",	0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I5 },
+{"cvt.w.d", "D,S",	0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I1 },
+{"cvt.w.s", "D,S",	0x46000024, 0xffff003f, WR_D|RD_S|FP_S,		0,		I1 },
+{"cvt.ps.s","D,V,T",	0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,		I5 },
+{"dabs",    "d,v",	0,    (int) M_DABS,	INSN_MACRO,		0,		I3 },
+{"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3 },
+{"dadd",    "t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		0,		I3 },
+{"daddi",   "t,r,j",	0x60000000, 0xfc000000, WR_t|RD_s,		0,		I3 },
+{"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s,		0,		I3 },
+{"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3 },
+{"daddu",   "t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,		0,		I3 },
+{"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64 },
+{"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64 },
 /* dctr and dctw are used on the r5000.  */
-{"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,			0,		I3	},
-{"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,			0,		I3	},
-{"deret",   "",         0x4200001f, 0xffffffff, NODS, 			0,		I32|G2	},
-{"dext",    "t,r,I,+I",	0,    (int) M_DEXT,	INSN_MACRO,		0,		I65	},
-{"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
-{"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
-{"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
+{"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,			0,		I3 },
+{"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,			0,		I3 },
+{"deret",   "",     0x4200001f, 0xffffffff, 0, 			0,			I32_R},
+{"dext",    "t,r,I,+I",	0,    (int) M_DEXT,	INSN_MACRO,		0,		I65 },
+{"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,    		0,		I65 },
+{"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,    		0,		I65 },
+{"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,    		0,		I65 },
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		0,		I3	},
-{"ddiv",    "d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		0,		I3	},
+{"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		0,		I3 },
+{"ddiv",    "d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		0,		I3 },
 /* For ddivu, see the comments about div.  */
 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"ddivu",   "d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3	},
-{"ddivu",   "d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3	},
-{"di",      "",		0x41606000, 0xffffffff,	WR_t|WR_C0,		0,		I33|IOCT},
-{"di",      "t",	0x41606000, 0xffe0ffff,	WR_t|WR_C0,		0,		I33|IOCT},
-{"dins",    "t,r,I,+I",	0,    (int) M_DINS,	INSN_MACRO,		0,		I65	},
-{"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
-{"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
-{"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
+{"ddivu",   "d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3 },
+{"ddivu",   "d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3 },
+{"di",      "",		0x41606000, 0xffffffff, WR_t|WR_C0,		0,		I33 },
+{"di",      "t",	0x41606000, 0xffe0ffff, WR_t|WR_C0,		0,		I33 },
+{"dins",    "t,r,I,+I",	0,    (int) M_DINS,	INSN_MACRO,		0,		I65 },
+{"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,    		0,		I65 },
+{"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,    		0,		I65 },
+{"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,    		0,		I65 },
 /* The MIPS assembler treats the div opcode with two operands as
    though the first operand appeared twice (the first operand is both
    a source and a destination).  To get the div machine instruction,
    you must use an explicit destination of $0.  */
 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
-{"div",     "d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,		0,		I1	},
-{"div",     "d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,		0,		I1	},
-{"div.d",   "D,V,T",	0x46200003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
-{"div.s",   "D,V,T",	0x46000003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
-{"div.ps",  "D,V,T",	0x46c00003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1	},
+{"div",     "d,v,t",    0,    (int) M_DIV_3,	INSN_MACRO,		0,		I1 },
+{"div",     "d,v,I",    0,    (int) M_DIV_3I,	INSN_MACRO,		0,		I1 },
+{"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		I1 },
+{"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,	0,		I1 },
 /* For divu, see the comments about div.  */
 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
-{"divu",    "d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,		0,		I1	},
-{"divu",    "d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,		0,		I1	},
-{"dla",     "t,A(b)",	0,    (int) M_DLA_AB,	INSN_MACRO,		0,		I3	},
-{"dlca",    "t,A(b)",	0,    (int) M_DLCA_AB,	INSN_MACRO,		0,		I3	},
-{"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,			0,		I3	}, /* addiu */
-{"dli",	    "t,i",	0x34000000, 0xffe00000, WR_t,			0,		I3	}, /* ori */
-{"dli",     "t,I",	0,    (int) M_DLI,	INSN_MACRO,		0,		I3	},
-{"dmacc",   "d,s,t",	0x00000029, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
-{"dmacchi", "d,s,t",	0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
-{"dmacchis", "d,s,t",	0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
-{"dmacchiu", "d,s,t",	0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
-{"dmacchius", "d,s,t",	0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
-{"dmaccs",  "d,s,t",	0x00000429, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
-{"dmaccu",  "d,s,t",	0x00000069, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
-{"dmaccus", "d,s,t",	0x00000469, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
-{"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,		N411    },
-{"dmfc0",   "t,G",	0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,		0,		I3|IOCT	},
-{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I64|IOCT},
-{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I64|IOCT},
-{"dmt",     "",		0x41600bc1, 0xffffffff, TRAP,			0,		MT32	},
-{"dmt",     "t",	0x41600bc1, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
-{"dmtc0",   "t,G",	0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,	0,		I3|IOCT	},
-{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I64|IOCT},
-{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I64|IOCT},
-{"dmfc1",   "t,S",	0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,	0,		I3	},
-{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,		I3      },
-{"dmtc1",   "t,S",	0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,	0,		I3	},
-{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,		I3      },
-/* dmfc2 is at the bottom of the table.  */
-/* dmtc2 is at the bottom of the table.  */
-/* dmfc3 is at the bottom of the table.  */
-/* dmtc3 is at the bottom of the table.  */
-{"dmul",    "d,v,t",	0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		IOCT	},
-{"dmul",    "d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,		I3	},
-{"dmul",    "d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		0,		I3	},
-{"dmulo",   "d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		0,		I3	},
-{"dmulo",   "d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		0,		I3	},
-{"dmulou",  "d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		0,		I3	},
-{"dmulou",  "d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,		0,		I3	},
-{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3	},
-{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3	},
-{"dneg",    "d,w",	0x0000002e, 0xffe007ff,	WR_d|RD_t,		0,		I3	}, /* dsub 0 */
-{"dnegu",   "d,w",	0x0000002f, 0xffe007ff,	WR_d|RD_t,		0,		I3	}, /* dsubu 0*/
-{"dpop",    "d,v",	0x7000002d, 0xfc1f07ff, WR_d|RD_s,		0,		IOCT	},
+{"divu",    "d,v,t",    0,    (int) M_DIVU_3,	INSN_MACRO,		0,		I1 },
+{"divu",    "d,v,I",    0,    (int) M_DIVU_3I,	INSN_MACRO,		0,		I1 },
+{"dla",     "t,A(b)",   0,    (int) M_DLA_AB,	INSN_MACRO,		0,		I3 },
+{"dlca",    "t,A(b)",   0,    (int) M_DLCA_AB,	INSN_MACRO,		0,		I3 },
+{"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,			0,		I3 }, /* addiu */
+{"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,			0,		I3 }, /* ori */
+{"dli",     "t,I",      0,    (int) M_DLI,	INSN_MACRO,		            0,		I3  },
+{"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,		    0,		I3  },
+{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	    0,		I64 },
+{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	    0,		I64 },
+{"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,	0,		I3  },
+{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I64 },
+{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I64 },
+{"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,	    0,		I3  },
+{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,		I3  },
+{"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,	    0,		I3  },
+{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,		I3  },
+{"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,		    0,		I3  },
+{"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8,	LCD|WR_t|RD_C2,		    0,		I64 },
+{"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,	I3 },
+{"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,   0,	I64 },
+{"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,  	    0,		I3      },
+{"dmfc3",   "t,G,H",    0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, 	    0,		I64     },
+{"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,		I3      },
+{"dmtc3",   "t,G,H",    0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,		I64     },
+{"dmul",    "d,v,t",    0,    (int) M_DMUL,	INSN_MACRO,		    0,		I3 },
+{"dmul",    "d,v,I",    0,    (int) M_DMUL_I,	INSN_MACRO,		0,		I3 },
+{"dmulo",   "d,v,t",    0,    (int) M_DMULO,	INSN_MACRO,		0,		I3 },
+{"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,	INSN_MACRO,		0,		I3 },
+{"dmulou",  "d,v,t",    0,    (int) M_DMULOU,	INSN_MACRO,		0,		I3 },
+{"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I,	INSN_MACRO,		0,		I3 },
+{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3 },
+{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3 },
+{"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,		0,		I3 }, /* dsub 0 */
+{"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,		0,		I3 }, /* dsubu 0*/
 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"drem",    "d,v,t",	0,    (int) M_DREM_3,	INSN_MACRO,		0,		I3	},
-{"drem",    "d,v,I",	0,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3	},
+{"drem",    "d,v,t",    3,    (int) M_DREM_3,	INSN_MACRO,		0,		I3 },
+{"drem",    "d,v,I",    3,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3 },
 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"dremu",   "d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3	},
-{"dremu",   "d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3	},
-{"dret",    "",		0x7000003e, 0xffffffff,	0,			0,		N5	},
-{"drol",    "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I3	},
-{"drol",    "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I3	},
-{"dror",    "d,v,t",	0,    (int) M_DROR,	INSN_MACRO,		0,		I3	},
-{"dror",    "d,v,I",	0,    (int) M_DROR_I,	INSN_MACRO,		0,		I3	},
-{"dror",    "d,w,<",	0x0020003a, 0xffe0003f,	WR_d|RD_t,		0,		N5|I65	},
-{"drorv",   "d,t,s",	0x00000056, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		N5|I65	},
-{"dror32",  "d,w,<",	0x0020003e, 0xffe0003f,	WR_d|RD_t,		0,		N5|I65	},
-{"drotl",   "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I65	},
-{"drotl",   "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I65	},
-{"drotr",   "d,v,t",	0,    (int) M_DROR,	INSN_MACRO,		0,		I65	},
-{"drotr",   "d,v,I",	0,    (int) M_DROR_I,	INSN_MACRO,		0,		I65	},
-{"drotrv",  "d,t,s",	0x00000056, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		I65	},
-{"drotr32", "d,w,<",	0x0020003e, 0xffe0003f,	WR_d|RD_t,		0,		I65	},
-{"dsbh",    "d,w",	0x7c0000a4, 0xffe007ff,	WR_d|RD_t,		0,		I65	},
-{"dshd",    "d,w",	0x7c000164, 0xffe007ff,	WR_d|RD_t,		0,		I65	},
-{"dsllv",   "d,t,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	},
-{"dsll32",  "d,w,<",	0x0000003c, 0xffe0003f, WR_d|RD_t,		0,		I3	},
-{"dsll",    "d,w,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	}, /* dsllv */
-{"dsll",    "d,w,>",	0x0000003c, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsll32 */
-{"dsll",    "d,w,<",	0x00000038, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
-{"dsll",	"D,S,T",	0x45a00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dsll",	"D,S,T",	0x4b20000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"dsrav",   "d,t,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	},
-{"dsra32",  "d,w,<",	0x0000003f, 0xffe0003f, WR_d|RD_t,		0,		I3	},
-{"dsra",    "d,w,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	}, /* dsrav */
-{"dsra",    "d,w,>",	0x0000003f, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsra32 */
-{"dsra",    "d,w,<",	0x0000003b, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
-{"dsra",	"D,S,T",	0x45e00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dsra",	"D,S,T",	0x4b60000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"dsrlv",   "d,t,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	},
-{"dsrl32",  "d,w,<",	0x0000003e, 0xffe0003f, WR_d|RD_t,		0,		I3	},
-{"dsrl",    "d,w,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	}, /* dsrlv */
-{"dsrl",    "d,w,>",	0x0000003e, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsrl32 */
-{"dsrl",    "d,w,<",	0x0000003a, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
-{"dsrl",	"D,S,T",	0x45a00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dsrl",	"D,S,T",	0x4b20000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"dsub",    "d,v,t",	0x0000002e, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I3	},
-{"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		0,		I3	},
-{"dsub",	"D,S,T",	0x45e00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dsub",	"D,S,T",	0x4b60000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I3	},
-{"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		0,		I3	},
-{"dvpe",    "",		0x41600001, 0xffffffff, TRAP,			0,		MT32	},
-{"dvpe",    "t",	0x41600001, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
-{"ei",      "",		0x41606020, 0xffffffff,	WR_t|WR_C0,		0,		I33|IOCT},
-{"ei",      "t",	0x41606020, 0xffe0ffff,	WR_t|WR_C0,		0,		I33|IOCT},
-{"emt",     "",		0x41600be1, 0xffffffff, TRAP,			0,		MT32	},
-{"emt",     "t",	0x41600be1, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
-{"eret",    "",         0x42000018, 0xffffffff, NODS,      		0,		I3_32	},
-{"evpe",    "",		0x41600021, 0xffffffff, TRAP,			0,		MT32	},
-{"evpe",    "t",	0x41600021, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
-{"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
-{"exts32",  "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
-{"exts",    "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s,		0,		IOCT	}, /* exts32 */
-{"exts",    "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
-{"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33	},
-{"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
-{"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
-{"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
-{"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
-{"iret",    "",		0x42000038, 0xffffffff,	NODS,			0,		MC	},
-{"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	},
-/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
-   the same hazard barrier effect.  */
-{"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32	},
-{"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	}, /* jr */
+{"dremu",   "d,v,t",    3,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3 },
+{"dremu",   "d,v,I",    3,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3 },
+{"drol",    "d,v,t",    0,    (int) M_DROL,	INSN_MACRO,		    0,		I3 },
+{"drol",    "d,v,I",    0,    (int) M_DROL_I,	INSN_MACRO,		0,		I3 },
+{"dror",    "d,v,t",    0,    (int) M_DROR,	INSN_MACRO,		    0,		I3 },
+{"dror",    "d,v,I",    0,    (int) M_DROR_I,	INSN_MACRO,		0,		I3 },
+{"dror",    "d,w,<",    0x0020003a, 0xffe0003f, WR_d|RD_t,		0,		I65 },
+{"drorv",   "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,	0,		I65 },
+{"dror32",  "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,		0,		I65 },
+{"drotl",   "d,v,t",    0,    (int) M_DROL,	INSN_MACRO,		    0,		I65 },
+{"drotl",   "d,v,I",    0,    (int) M_DROL_I,	INSN_MACRO,		0,		I65 },
+{"drotr",   "d,v,t",    0,    (int) M_DROR,	INSN_MACRO,		    0,		I65 },
+{"drotr",   "d,v,I",    0,    (int) M_DROR_I,	INSN_MACRO,		0,		I65 },
+{"drotrv",  "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,	0,		I65 },
+{"drotr32", "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,		0,		I65 },
+{"dsbh",    "d,w",      0x7c0000a4, 0xffe007ff, WR_d|RD_t,		0,		I65 },
+{"dshd",    "d,w",      0x7c000164, 0xffe007ff, WR_d|RD_t,		0,		I65 },
+{"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,	0,		I3 },
+{"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,		0,		I3 },
+{"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,	0,		I3 }, /* dsllv */
+{"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,		0,		I3 }, /* dsll32 */
+{"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,		0,		I3 },
+{"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,	0,		I3 },
+{"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,		0,		I3 },
+{"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,	0,		I3 }, /* dsrav */
+{"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,		0,		I3 }, /* dsra32 */
+{"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,		0,		I3 },
+{"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,	0,		I3 },
+{"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,		0,		I3 },
+{"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,	0,		I3 }, /* dsrlv */
+{"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,		0,		I3 }, /* dsrl32 */
+{"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,		0,		I3 },
+{"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		I3 },
+{"dsub",    "d,v,I",    0,    (int) M_DSUB_I,	INSN_MACRO,		0,		I3 },
+{"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		I3 },
+{"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,	INSN_MACRO,		0,		I3 },
+{"ei",      "",         0x41606020, 0xffffffff, WR_t|WR_C0,		0,		I33 },
+{"ei",      "t",        0x41606020, 0xffe0ffff, WR_t|WR_C0,		0,		I33 },
+{"eret",    "",         0x42000018, 0xffffffff, 0,      		0,		I3_32 },
+{"ext",    "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,    	0,		I33 },
+{"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,	0,		I3_33 },
+{"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_S,	0,	I3_33 },
+{"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,	I2 },
+{"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2 },
+{"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33 },
+{"jr",      "s",    0x00000008, 0xfc1fffff, UBD|RD_s,		0,		I1    },
+{"jr.hb",   "s",    0x00000408, 0xfc1fffff, UBD|RD_s,		0,		I33    },
+{"j",       "s",    0x00000008, 0xfc1fffff, UBD|RD_s,		0,		I1    }, /* jr */
 /* SVR4 PIC code requires special handling for j, so it must be a
    macro.  */
-{"j",	    "a",	0,     (int) M_J_A,	INSN_MACRO,		0,		I1	},
+{"j",	    "a",	0,     (int) M_J_A,	INSN_MACRO,		0,		I1 },
 /* This form of j is used by the disassembler and internally by the
    assembler, but will never match user input (because the line above
    will match first).  */
-{"j",       "a",	0x08000000, 0xfc000000,	UBD,			0,		I1	},
-{"jalr",    "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d,		0,		I1	},
-{"jalr",    "d,s",	0x00000009, 0xfc1f07ff,	UBD|RD_s|WR_d,		0,		I1	},
-/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
-   with the same hazard barrier effect.  */
-{"jalr.hb", "s",	0x0000fc09, 0xfc1fffff,	UBD|RD_s|WR_d,		0,		I32	},
-{"jalr.hb", "d,s",	0x00000409, 0xfc1f07ff,	UBD|RD_s|WR_d,		0,		I32	},
+{"j",       "a",	0x08000000, 0xfc000000,	UBD,			0,		I1 },
+{"jalr",    "s",	0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,		0,		I1 },
+{"jalr",    "d,s",	0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,		0,		I1 },
+{"jalr.hb", "s",	0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,		0,		I33 },
+{"jalr.hb", "d,s",	0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,		0,		I33 },
 /* SVR4 PIC code requires special handling for jal, so it must be a
    macro.  */
-{"jal",     "d,s",	0,     (int) M_JAL_2,	INSN_MACRO,		0,		I1	},
-{"jal",     "s",	0,     (int) M_JAL_1,	INSN_MACRO,		0,		I1	},
-{"jal",     "a",	0,     (int) M_JAL_A,	INSN_MACRO,		0,		I1	},
+{"jal",     "d,s",	0,     (int) M_JAL_2,	INSN_MACRO,		0,		I1 },
+{"jal",     "s",	0,     (int) M_JAL_1,	INSN_MACRO,		0,		I1 },
+{"jal",     "a",	0,     (int) M_JAL_A,	INSN_MACRO,		0,		I1 },
 /* This form of jal is used by the disassembler and internally by the
    assembler, but will never match user input (because the line above
    will match first).  */
-{"jal",     "a",	0x0c000000, 0xfc000000,	UBD|WR_31,		0,		I1	},
-{"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,		0,		I1	},
-{"la",      "t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,		0,		I1	},
-{"lb",      "t,o(b)",	0x80000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
-{"lb",      "t,A(b)",	0,    (int) M_LB_AB,	INSN_MACRO,		0,		I1	},
-{"lbu",     "t,o(b)",	0x90000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
-{"lbu",     "t,A(b)",	0,    (int) M_LBU_AB,	INSN_MACRO,		0,		I1	},
-{"lca",     "t,A(b)",	0,    (int) M_LCA_AB,	INSN_MACRO,		0,		I1	},
-/* The macro has to be first to handle o32 correctly.  */
-{"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO,		0,		I1	},
-{"ld",      "t,o(b)",	0xdc000000, 0xfc000000, WR_t|RD_b,		0,		I3	},
-{"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		0,		I1	},
-{"ldaddw",  "t,b",	0x70000010, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
-{"ldaddwu", "t,b",	0x70000011, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
-{"ldaddd",  "t,b",	0x70000012, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
-{"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
-{"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
-{"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
-{"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
-{"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	}, /* ldc1 */
-{"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2	},
-{"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		0,		I2	},
-{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2	},
-{"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		0,		I2	},
-{"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3	},
-{"ldl",	    "t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,		0,		I3	},
-{"ldr",	    "t,o(b)",	0x6c000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3	},
-{"ldr",     "t,A(b)",	0,    (int) M_LDR_AB,	INSN_MACRO,		0,		I3	},
-{"ldxc1",   "D,t(b)",	0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I4_33	},
-{"lh",      "t,o(b)",	0x84000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
-{"lh",      "t,A(b)",	0,    (int) M_LH_AB,	INSN_MACRO,		0,		I1	},
-{"lhu",     "t,o(b)",	0x94000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
-{"lhu",     "t,A(b)",	0,    (int) M_LHU_AB,	INSN_MACRO,		0,		I1	},
+{"jal",     "a",	0x0c000000, 0xfc000000,	UBD|WR_31,		0,		I1 },
+{"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,		0,		I1 },
+{"la",      "t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,		0,		I1 },
+{"lb",      "t,o(b)",	0x80000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1 },
+{"lb",      "t,A(b)",	0,    (int) M_LB_AB,	INSN_MACRO,		0,		I1 },
+{"lbu",     "t,o(b)",	0x90000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1 },
+{"lbu",     "t,A(b)",	0,    (int) M_LBU_AB,	INSN_MACRO,		0,		I1 },
+{"lca",     "t,A(b)",	0,    (int) M_LCA_AB,	INSN_MACRO,		0,		I1 },
+{"ld",	    "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,		0,		I3 },
+{"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO,		0,		I1 },
+{"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		0,		I1 },
+{"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2 },
+{"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2 },
+{"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		0,		I2 },
+{"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		0,		I2 },
+{"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2 }, /* ldc1 */
+{"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,		0,		I1 },
+{"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		0,		I1 },
+{"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2 },
+{"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		0,		I2 },
+{"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2 },
+{"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		0,		I2 },
+{"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3 },
+{"ldl",	    "t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,		0,		I3 },
+{"ldr",	    "t,o(b)",	0x6c000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3 },
+{"ldr",     "t,A(b)",	0,    (int) M_LDR_AB,	INSN_MACRO,		0,		I3 },
+{"ldxc1",   "D,t(b)",	0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I4_33 },
+{"lh",      "t,o(b)",	0x84000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1 },
+{"lh",      "t,A(b)",	0,    (int) M_LH_AB,	INSN_MACRO,		0,		I1 },
+{"lhu",     "t,o(b)",	0x94000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1 },
+{"lhu",     "t,A(b)",	0,    (int) M_LHU_AB,	INSN_MACRO,		0,		I1 },
 /* li is at the start of the table.  */
-{"li.d",    "t,F",	0,    (int) M_LI_D,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"li.d",    "T,L",	0,    (int) M_LI_DD,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"li.s",    "t,f",	0,    (int) M_LI_S,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"li.s",    "T,l",	0,    (int) M_LI_SS,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"ll",	    "t,o(b)",	0xc0000000, 0xfc000000, LDD|RD_b|WR_t,		0,		I2	},
-{"ll",	    "t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,		0,		I2	},
-{"lld",	    "t,o(b)",	0xd0000000, 0xfc000000, LDD|RD_b|WR_t,		0,		I3	},
-{"lld",     "t,A(b)",	0,    (int) M_LLD_AB,	INSN_MACRO,		0,		I3	},
-{"lui",     "t,u",	0x3c000000, 0xffe00000,	WR_t,			0,		I1	},
-{"luxc1",   "D,t(b)",	0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I5_33|N55},
-{"lw",      "t,o(b)",	0x8c000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
-{"lw",      "t,A(b)",	0,    (int) M_LW_AB,	INSN_MACRO,		0,		I1	},
-{"lwc0",    "E,o(b)",	0xc0000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
-{"lwc0",    "E,A(b)",	0,    (int) M_LWC0_AB,	INSN_MACRO,		0,		I1	},
-{"lwc1",    "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1	},
-{"lwc1",    "E,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1	},
-{"lwc1",    "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"lwc1",    "E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"l.s",     "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1	}, /* lwc1 */
-{"l.s",     "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
-{"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		0,		I1	},
-{"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
-{"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		0,		I1	},
-{"lwl",     "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
-{"lwl",     "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I1	},
-{"lcache",  "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I2	}, /* same */
-{"lcache",  "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I2	}, /* as lwl */
-{"lwr",     "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
-{"lwr",     "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I1	},
-{"flush",   "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I2	}, /* same */
-{"flush",   "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I2	}, /* as lwr */
-{"fork",    "d,s,t",	0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,	0,		MT32	},
-{"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I3	},
-{"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,		0,		I3	},
-{"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0,		I4_33	},
-{"lwxs",    "d,t(b)",	0x70000088, 0xfc0007ff,	LDD|RD_b|RD_t|WR_d,	0,		SMT	},
-{"macc",    "d,s,t",	0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
-{"macc",    "d,s,t",	0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },
-{"maccs",   "d,s,t",	0x00000428, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
-{"macchi",  "d,s,t",	0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
-{"macchi",  "d,s,t",	0x00000358, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },
-{"macchis", "d,s,t",	0x00000628, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
-{"macchiu", "d,s,t",	0x00000268, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
-{"macchiu", "d,s,t",	0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },
-{"macchius","d,s,t",	0x00000668, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
-{"maccu",   "d,s,t",	0x00000068, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
-{"maccu",   "d,s,t",	0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },
-{"maccus",  "d,s,t",	0x00000468, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
-{"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		P3      },
-{"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		P3      },
-{"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I4_33	},
-{"madd.d",	"D,S,T",	0x46200018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"madd.d",	"D,S,T",	0x72200018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
-{"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,		I4_33	},
-{"madd.s",	"D,S,T",	0x46000018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"madd.s",	"D,S,T",	0x72000018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
-{"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I5_33	},
-{"madd.ps",	"D,S,T",	0x45600018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"madd.ps",	"D,S,T",	0x71600018,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
-{"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
-{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
-{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
-{"madd",    "7,s,t",	0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32	},
-{"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
-{"maddp",   "s,t",      0x70000441, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	     0,		SMT	},
-{"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
-{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
-{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
-{"maddu",   "7,s,t",	0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32	},
-{"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
-{"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,	0,		N411    },
-{"max.ob",  "X,Y,Q",	0x78000007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"max.ob",  "D,S,T",	0x4ac00007, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"max.ob",  "D,S,T[e]",	0x48000007, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"max.ob",  "D,S,k",	0x4bc00007, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"max.qh",  "X,Y,Q",	0x78200007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"mfpc",    "t,P",	0x4000c801, 0xffe0ffc1,	LCD|WR_t|RD_C0,		0,		M1|N5	},
-{"mfps",    "t,P",	0x4000c800, 0xffe0ffc1,	LCD|WR_t|RD_C0,		0,		M1|N5	},
-{"mftacx",  "d",	0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,		0,		MT32	},
-{"mftacx",  "d,*",	0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,		0,		MT32	},
-{"mftc0",   "d,+t",	0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,	0,		MT32	},
-{"mftc0",   "d,+T",	0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,	0,		MT32	},
-{"mftc0",   "d,E,H",	0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,	0,		MT32	},
-{"mftc1",   "d,T",	0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,		MT32	},
-{"mftc1",   "d,E",	0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,		MT32	},
-{"mftc2",   "d,E",	0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,	0,		MT32	},
-{"mftdsp",  "d",	0x41100021, 0xffff07ff, TRAP|WR_d,		0,		MT32	},
-{"mftgpr",  "d,t",	0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,		0,		MT32	},
-{"mfthc1",  "d,T",	0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,		MT32	},
-{"mfthc1",  "d,E",	0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,		MT32	},
-{"mfthc2",  "d,E",	0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,	0,		MT32	},
-{"mfthi",   "d",	0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,		0,		MT32	},
-{"mfthi",   "d,*",	0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,		0,		MT32	},
-{"mftlo",   "d",	0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,		0,		MT32	},
-{"mftlo",   "d,*",	0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,		0,		MT32	},
-{"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,		0,		MT32	},
-{"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		I1|IOCT	},
-{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I32|IOCT},
-{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I32|IOCT},
-{"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	0,		I1	},
-{"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	0,		I1	},
-{"mfhc1",   "t,S",	0x44600000, 0xffe007ff,	LCD|WR_t|RD_S|FP_D,	0,		I33	},
-{"mfhc1",   "t,G",	0x44600000, 0xffe007ff,	LCD|WR_t|RD_S|FP_D,	0,		I33	},
-/* mfc2 is at the bottom of the table.  */
-/* mfhc2 is at the bottom of the table.  */
-/* mfc3 is at the bottom of the table.  */
-{"mfdr",    "t,G",	0x7000003d, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		N5      },
-{"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,		0,		I1	},
-{"mfhi",    "d,9",	0x00000010, 0xff9f07ff, WR_d|RD_HI,		0,		D32	},
-{"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,		0,		I1	},
-{"mflo",    "d,9",	0x00000012, 0xff9f07ff, WR_d|RD_LO,		0,		D32	},
-{"mflhxu",  "d",	0x00000052, 0xffff07ff,	WR_d|MOD_HILO,		0,		SMT	},
-{"mfcr",    "t,s",	0x70000018, 0xfc00ffff, WR_t,			0,		XLR 	},
-{"min.ob",  "X,Y,Q",	0x78000006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"min.ob",  "D,S,T",	0x4ac00006, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"min.ob",  "D,S,T[e]",	0x48000006, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"min.ob",  "D,S,k",	0x4bc00006, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"min.qh",  "X,Y,Q",	0x78200006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
-{"mov.s",   "D,S",	0x46000006, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
-{"mov.ps",  "D,S",	0x46c00006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5_33|IL2F	},
-{"mov.ps",  "D,S",	0x45600006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		IL2E	},
-{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,		I4_32  },
-{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		I4_32	},
-{"movf.l",  "D,S,N",	0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		MX|SB1	},
-{"movf.l",  "X,Y,N",	0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		MX|SB1	},
-{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4_32	},
-{"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5_33	},
-{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4_32|IL2E|IL2F	},
-{"movnz",   "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		IL2E|IL2F|IL3A	},
-{"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
-{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4_32	},
-{"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
-{"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
-{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,		I4_32	},
-{"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I5_33	},
-{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,		I4_32	},
-{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		I4_32	},
-{"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		MX|SB1	},
-{"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		MX|SB1	},
-{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4_32	},
-{"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5_33	},
-{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4_32|IL2E|IL2F	},
-{"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
-{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4_32	},
-{"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
-{"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
-{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,		I4_32	},
-{"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I5_33	},
-{"msac",    "d,s,t",	0x000001d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"msacu",   "d,s,t",	0x000001d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"msachi",  "d,s,t",	0x000003d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"msachiu", "d,s,t",	0x000003d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
+{"li.d",    "t,F",	0,    (int) M_LI_D,	INSN_MACRO,		0,		I1 },
+{"li.d",    "T,L",	0,    (int) M_LI_DD,	INSN_MACRO,		0,		I1 },
+{"li.s",    "t,f",	0,    (int) M_LI_S,	INSN_MACRO,		0,		I1 },
+{"li.s",    "T,l",	0,    (int) M_LI_SS,	INSN_MACRO,		0,		I1 },
+{"ll",	    "t,o(b)",	0xc0000000, 0xfc000000, LDD|RD_b|WR_t,      0,      I2_R   },
+{"ll",	    "t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,         0,      I2_R   },
+{"lld",	    "t,o(b)",	0xd0000000, 0xfc000000, LDD|RD_b|WR_t,		0,		I3 },
+{"lld",     "t,A(b)",	0,    (int) M_LLD_AB,	INSN_MACRO,         0,		I3 },
+{"lui",     "t,u",	    0x3c000000, 0xffe00000,	WR_t,               0,		I1 },
+{"luxc1",   "D,t(b)",	0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	0,		I5 },
+{"lw",      "t,o(b)",	0x8c000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1 },
+{"lw",      "t,A(b)",	0,    (int) M_LW_AB,	INSN_MACRO,		0,		I1 },
+{"lwc0",    "E,o(b)",	0xc0000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1 },
+{"lwc0",    "E,A(b)",	0,    (int) M_LWC0_AB,	INSN_MACRO,		0,		I1 },
+{"lwc1",    "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1 },
+{"lwc1",    "E,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1 },
+{"lwc1",    "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		0,		I1 },
+{"lwc1",    "E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		0,		I1 },
+{"l.s",     "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1 }, /* lwc1 */
+{"l.s",     "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		0,		I1 },
+{"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1 },
+{"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		0,		I1 },
+{"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1 },
+{"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		0,		I1 },
+{"lwl",     "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1 },
+{"lwl",     "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I1 },
+{"lcache",  "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I2 }, /* same */
+{"lcache",  "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I2 }, /* as lwl */
+{"lwr",     "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1 },
+{"lwr",     "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I1 },
+{"flush",   "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I2 }, /* same */
+{"flush",   "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I2 }, /* as lwr */
+{"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I3 },
+{"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,		0,		I3 },
+{"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I4_33 },
+{"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		RALL },
+{"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		RALL },
+{"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I4_33 },
+{"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,		I4_33 },
+{"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I5 },
+{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32},
+{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32},
+{"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,		0,		I1   },
+{"mfc0",    "t,G,#H",   0x40000000, 0xffe007c0, LCD|WR_t|RD_C0, 	0,		RT   },
+{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I32  },
+{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I32  },
+{"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,	0,		I1   },
+{"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,	0,		I1   },
+{"mfc1",    "t,G,#H",   0x44000000, 0xffe007c0,	LCD|WR_t|RD_S|FP_S,	0,		RT   },
+{"mfhc1",   "t,S",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,	0,		I33	 },
+{"mfhc1",   "t,G",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,	0,		I33	 },
+{"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,       0,	I1	 },
+{"mfc2",    "t,G,#H",   0x48000000, 0xffe007c0,	LCD|WR_t|RD_C2,       0,	RT   },
+{"mfc2",    "t,G,H",    0x48000000, 0xffe007f8,	LCD|WR_t|RD_C2,       0,	I32	 },
+{"mfhc2",   "t,i",      0x48600000, 0xffe00000,	LCD|WR_t|RD_C2,       0,	I33	 },
+{"mfc3",    "t,G",  	0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,		0,		I1	 },
+{"mfc3",    "t,G,#H",   0x4c000000, 0xffe007c0, LCD|WR_t|RD_C3, 	0,		RT   },
+{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 	0,		I32  },
+{"mfhi",    "d",	0x00000010, 0xffff07ff, WR_d|RD_HI,		0,		I1 },
+{"mflo",    "d",	0x00000012, 0xffff07ff, WR_d|RD_LO,		0,		I1 },
+{"mov.d",   "D,S",	0x46200006, 0xffff003f, WR_D|RD_S|FP_D,		0,		I1 },
+{"mov.s",   "D,S",	0x46000006, 0xffff003f, WR_D|RD_S|FP_S,		0,		I1 },
+{"mov.ps",  "D,S",	0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,		0,		I5 },
+{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,	I4_32  },
+{"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		I4_32 },
+{"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4_32 },
+{"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5 },
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	    0,		I4_32 },
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	    0,		RUDI  },
+{"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4_32 },
+{"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,		I4_32 },
+{"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I5 },
+{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,	I4_32 },
+{"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		I4_32 },
+{"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4_32 },
+{"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5 },
+
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,			0,		I4_32 },
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,			0,		RUDI  },
+{"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4_32 },
+{"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,		I4_32 },
+{"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I5 },
 /* move is at the top of the table.  */
-{"msgn.qh", "X,Y,Q",	0x78200000, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"msgsnd",  "t",	0,    (int) M_MSGSND,	INSN_MACRO,		0,             XLR	},
-{"msgld",   "", 	0,    (int) M_MSGLD,	INSN_MACRO,		0,             XLR	},
-{"msgld",   "t",	0,    (int) M_MSGLD_T,	INSN_MACRO,		0,             XLR	},
-{"msgwait", "", 	0,    (int) M_MSGWAIT,	INSN_MACRO,		0,             XLR	},
-{"msgwait", "t",	0,    (int) M_MSGWAIT_T,INSN_MACRO,		0,             XLR	},
-{"msub.d",  "D,R,S,T",	0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4_33	},
-{"msub.d",	"D,S,T",	0x46200019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"msub.d",	"D,S,T",	0x72200019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
-{"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4_33	},
-{"msub.s",	"D,S,T",	0x46000019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"msub.s",	"D,S,T",	0x72000019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
-{"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5_33	},
-{"msub.ps",	"D,S,T",	0x45600019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"msub.ps",	"D,S,T",	0x71600019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
-{"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1    	},
-{"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55 },
-{"msub",    "7,s,t",	0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32	},
-{"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1	},
-{"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55	},
-{"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32	},
-{"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
-{"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
-{"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	0,		I1|IOCT	},
-{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I32|IOCT},
-{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I32|IOCT},
-{"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	0,		I1	},
-{"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	0,		I1	},
-{"mthc1",   "t,S",	0x44e00000, 0xffe007ff,	COD|RD_t|WR_S|FP_D,	0,		I33	},
-{"mthc1",   "t,G",	0x44e00000, 0xffe007ff,	COD|RD_t|WR_S|FP_D,	0,		I33	},
-/* mtc2 is at the bottom of the table.  */
-/* mthc2 is at the bottom of the table.  */
-/* mtc3 is at the bottom of the table.  */
-{"mtdr",    "t,G",	0x7080003d, 0xffe007ff,	COD|RD_t|WR_C0,		0,		N5	},
-{"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,		0,		I1	},
-{"mthi",    "s,7",	0x00000011, 0xfc1fe7ff, RD_s|WR_HI,		0,		D32	},
-{"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,		0,		I1	},
-{"mtlo",    "s,7",	0x00000013, 0xfc1fe7ff, RD_s|WR_LO,		0,		D32	},
-{"mtlhx",   "s",	0x00000053, 0xfc1fffff,	RD_s|MOD_HILO,		0,		SMT	},
-{"mtcr",    "t,s",      0x70000019, 0xfc00ffff, RD_t,			0,		XLR	},
-{"mtm0",    "s",	0x70000008, 0xfc1fffff, RD_s,			0,		IOCT	},
-{"mtm1",    "s",	0x7000000c, 0xfc1fffff, RD_s,			0,		IOCT	},
-{"mtm2",    "s",	0x7000000d, 0xfc1fffff, RD_s,			0,		IOCT	},
-{"mtp0",    "s",	0x70000009, 0xfc1fffff, RD_s,			0,		IOCT	},
-{"mtp1",    "s",	0x7000000a, 0xfc1fffff, RD_s,			0,		IOCT	},
-{"mtp2",    "s",	0x7000000b, 0xfc1fffff, RD_s,			0,		IOCT	},
-{"mttc0",   "t,G",	0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
-{"mttc0",   "t,+D",	0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
-{"mttc0",   "t,G,H",	0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
-{"mttc1",   "t,S",	0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,		MT32	},
-{"mttc1",   "t,G",	0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,		MT32	},
-{"mttc2",   "t,g",	0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,		MT32	},
-{"mttacx",  "t",	0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,		0,		MT32	},
-{"mttacx",  "t,&",	0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,		0,		MT32	},
-{"mttdsp",  "t",	0x41808021, 0xffe0ffff, TRAP|RD_t,		0,		MT32	},
-{"mttgpr",  "t,d",	0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,		0,		MT32	},
-{"mtthc1",  "t,S",	0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,		MT32	},
-{"mtthc1",  "t,G",	0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,		MT32	},
-{"mtthc2",  "t,g",	0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,		MT32	},
-{"mtthi",   "t",	0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,		0,		MT32	},
-{"mtthi",   "t,&",	0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,		0,		MT32	},
-{"mttlo",   "t",	0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,		0,		MT32	},
-{"mttlo",   "t,&",	0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,		0,		MT32	},
-{"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,		0,		MT32	},
-{"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
-{"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
-{"mul.ob",  "X,Y,Q",	0x78000030, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"mul.ob",  "D,S,T",	0x4ac00030, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"mul.ob",  "D,S,T[e]",	0x48000030, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"mul.ob",  "D,S,k",	0x4bc00030, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33|IL2F	},
-{"mul.ps",  "D,V,T",	0x45600002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		IL2E	},
-{"mul.qh",  "X,Y,Q",	0x78200030, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		I32|P3|N55},
-{"mul",     "d,s,t",	0x00000058, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N54	},
-{"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,		0,		I1	},
-{"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,		0,		I1	},
-{"mula.ob", "Y,Q",	0x78000033, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
-{"mula.ob", "S,T",	0x4ac00033, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mula.ob", "S,T[e]",	0x48000033, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mula.ob", "S,k",	0x4bc00033, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mula.qh", "Y,Q",	0x78200033, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"mulhi",   "d,s,t",	0x00000258, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"mulhiu",  "d,s,t",	0x00000259, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"mull.ob", "Y,Q",	0x78000433, 0xfc2007ff,	RD_S|RD_T|FP_D, 	WR_MACC,	MX|SB1	},
-{"mull.ob", "S,T",	0x4ac00433, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mull.ob", "S,T[e]",	0x48000433, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mull.ob", "S,k",	0x4bc00433, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mull.qh", "Y,Q",	0x78200433, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,		0,		I1	},
-{"mulo",    "d,v,I",	0,    (int) M_MULO_I,	INSN_MACRO,		0,		I1	},
-{"mulou",   "d,v,t",	0,    (int) M_MULOU,	INSN_MACRO,		0,		I1	},
-{"mulou",   "d,v,I",	0,    (int) M_MULOU_I,	INSN_MACRO,		0,		I1	},
-{"mulr.ps", "D,S,T",	0x46c0001a, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		M3D	},
-{"muls",    "d,s,t",	0x000000d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"mulsu",   "d,s,t",	0x000000d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"mulshi",  "d,s,t",	0x000002d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"mulshiu", "d,s,t",	0x000002d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"muls.ob", "Y,Q",	0x78000032, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
-{"muls.ob", "S,T",	0x4ac00032, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"muls.ob", "S,T[e]",	0x48000032, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"muls.ob", "S,k",	0x4bc00032, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"muls.qh", "Y,Q",	0x78200032, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"mulsl.ob", "Y,Q",	0x78000432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
-{"mulsl.ob", "S,T",	0x4ac00432, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mulsl.ob", "S,T[e]",	0x48000432, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mulsl.ob", "S,k",	0x4bc00432, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
-{"mulsl.qh", "Y,Q",	0x78200432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
-{"mult",    "7,s,t",	0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32	},
-{"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
-{"multp",   "s,t",	0x00000459, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		SMT	},
-{"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
-{"multu",   "7,s,t",	0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32	},
-{"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
-{"mulu",    "d,s,t",	0x00000059, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
-{"neg",     "d,w",	0x00000022, 0xffe007ff,	WR_d|RD_t,		0,		I1	}, /* sub 0 */
-{"negu",    "d,w",	0x00000023, 0xffe007ff,	WR_d|RD_t,		0,		I1	}, /* subu 0 */
-{"neg.d",   "D,V",	0x46200007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
-{"neg.s",   "D,V",	0x46000007, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
-{"neg.ps",  "D,V",	0x46c00007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5_33|IL2F	},
-{"neg.ps",  "D,V",	0x45600007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		IL2E	},
-{"nmadd.d", "D,R,S,T",	0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4_33	},
-{"nmadd.d",	"D,S,T",	0x4620001a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"nmadd.d",	"D,S,T",	0x7220001a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
-{"nmadd.s", "D,R,S,T",	0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4_33	},
-{"nmadd.s",	"D,S,T",	0x4600001a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"nmadd.s",	"D,S,T",	0x7200001a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
-{"nmadd.ps","D,R,S,T",	0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5_33	},
-{"nmadd.ps",	"D,S,T",	0x4560001a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"nmadd.ps",	"D,S,T",	0x7160001a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
-{"nmsub.d", "D,R,S,T",	0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4_33	},
-{"nmsub.d",	"D,S,T",	0x4620001b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"nmsub.d",	"D,S,T",	0x7220001b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
-{"nmsub.s", "D,R,S,T",	0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4_33	},
-{"nmsub.s",	"D,S,T",	0x4600001b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"nmsub.s",	"D,S,T",	0x7200001b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
-{"nmsub.ps","D,R,S,T",	0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5_33	},
-{"nmsub.ps",	"D,S,T",	0x4560001b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"nmsub.ps",	"D,S,T",	0x7160001b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4_33 },
+{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4_33 },
+{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5 },
+{"msub",    "s,t",    0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,  I32_R    },
+{"msubu",   "s,t",    0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,  I32_R    },
+{"mtc0",    "t,G",    0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,  I1       },
+{"mtc0",    "t,G,#H", 0x40800000, 0xffe007c0, COD|RD_t|WR_C0|WR_CC,   0,  RT       },
+{"mtc0",    "t,+D",   0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,  I32      },
+{"mtc0",    "t,G,H",  0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,  I32      },
+{"mtc1",    "t,S",    0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,  I1       },
+{"mtc1",    "t,G",    0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,  I1       },
+{"mtc1",    "t,G,#H", 0x44800000, 0xffe007c0, COD|RD_t|WR_S|FP_S,     0,  RT       },
+{"mthc1",   "t,S",    0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,  I33      },
+{"mthc1",   "t,G",    0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,  I33      },
+{"mtc2",    "t,G",    0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,  I1       },
+{"mtc2",    "t,G,#H", 0x48800000, 0xffe007c0, COD|RD_t|WR_C2|WR_CC,   0,  RT       },
+{"mtc2",    "t,G,H",  0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,  I32      },
+{"mthc2",   "t,i",    0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,  I33      },
+{"mtc3",    "t,G",    0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,  I1       },
+{"mtc3",    "t,G,#H", 0x4c800000, 0xffe007c0, COD|RD_t|WR_C3|WR_CC,   0,  RT       },
+{"mtc3",    "t,G,H",  0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,  I32      },
+{"mthi",    "s",      0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,  I1       },
+{"mtlo",    "s",      0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,  I1       },
+{"mul.d",   "D,V,T",  0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,  I1       },
+{"mul.s",   "D,V,T",  0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,  I1       },
+{"mul.ps",  "D,V,T",  0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,  I5       },
+{"mul",     "d,v,t",  0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,  I32      },
+{"mul",     "d,v,t",  0,    (int) M_MUL,	INSN_MACRO,		0,		I1 },
+{"mul",     "d,v,I",  0,    (int) M_MUL_I,	INSN_MACRO,		0,		I1 },
+{"mulo",    "d,v,t",  0,    (int) M_MULO,	INSN_MACRO,		0,		I1 },
+{"mulo",    "d,v,I",  0,    (int) M_MULO_I,	INSN_MACRO,		0,		I1 },
+{"mulou",   "d,v,t",  0,    (int) M_MULOU,	INSN_MACRO,		0,		I1 },
+{"mulou",   "d,v,I",  0,    (int) M_MULOU_I,	INSN_MACRO,		0,		I1 },
+{"mult",    "s,t",    0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1 },
+{"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1 },
+{"neg",     "d,w",	0x00000022, 0xffe007ff, WR_d|RD_t,		0,		I1 }, /* sub 0 */
+{"negu",    "d,w",	0x00000023, 0xffe007ff, WR_d|RD_t,		0,		I1 }, /* subu 0 */
+{"neg.d",   "D,V",	0x46200007, 0xffff003f, WR_D|RD_S|FP_D,		0,		I1 },
+{"neg.s",   "D,V",	0x46000007, 0xffff003f, WR_D|RD_S|FP_S,		0,		I1 },
+{"neg.ps",  "D,V",	0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,		0,		I5 },
+{"nmadd.d", "D,R,S,T",	0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4_33 },
+{"nmadd.s", "D,R,S,T",	0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4_33 },
+{"nmadd.ps","D,R,S,T",	0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5 },
+{"nmsub.d", "D,R,S,T",	0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4_33 },
+{"nmsub.s", "D,R,S,T",	0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4_33 },
+{"nmsub.ps","D,R,S,T",	0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5 },
 /* nop is at the start of the table.  */
-{"nor",     "d,v,t",	0x00000027, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"nor",     "t,r,I",	0,    (int) M_NOR_I,	INSN_MACRO,		0,		I1	},
-{"nor",	"D,S,T",	0x47a00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"nor",	"D,S,T",	0x4ba00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"nor.ob",  "X,Y,Q",	0x7800000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"nor.ob",  "D,S,T",	0x4ac0000f, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"nor.ob",  "D,S,T[e]",	0x4800000f, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"nor.ob",  "D,S,k",	0x4bc0000f, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"nor.qh",  "X,Y,Q",	0x7820000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"not",     "d,v",	0x00000027, 0xfc1f07ff,	WR_d|RD_s|RD_t,		0,		I1	},/*nor d,s,0*/
-{"or",      "d,v,t",	0x00000025, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"or",      "t,r,I",	0,    (int) M_OR_I,	INSN_MACRO,		0,		I1	},
-{"or",	"D,S,T",	0x45a00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"or",	"D,S,T",	0x4b20000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"or.ob",   "X,Y,Q",	0x7800000e, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"or.ob",   "D,S,T",	0x4ac0000e, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"or.ob",   "D,S,T[e]",	0x4800000e, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"or.ob",   "D,S,k",	0x4bc0000e, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"or.qh",   "X,Y,Q",	0x7820000e, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"ori",     "t,r,i",	0x34000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
-{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1	},
-{"pabsdiffc.ob", "Y,Q",	0x78000035, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	SB1	},
-{"pavg.ob", "X,Y,Q",	0x78000008, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1	},
-{"pickf.ob", "X,Y,Q",	0x78000002, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"pickf.ob", "D,S,T",	0x4ac00002, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"pickf.ob", "D,S,k",	0x4bc00002, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"pickf.qh", "X,Y,Q",	0x78200002, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"pickt.ob", "X,Y,Q",	0x78000003, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"pickt.ob", "D,S,T",	0x4ac00003, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"pickt.ob", "D,S,k",	0x4bc00003, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"pickt.qh", "X,Y,Q",	0x78200003, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"pll.ps",  "D,V,T",	0x46c0002c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
-{"plu.ps",  "D,V,T",	0x46c0002d, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
-{"pop",     "d,v",	0x7000002c, 0xfc1f07ff, WR_d|RD_s,		0,		IOCT	},
+{"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I1 },
+{"nor",     "t,r,I",    0,    (int) M_NOR_I,	INSN_MACRO,		0,		I1 },
+{"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,		0,		I1 },/*nor d,s,0*/
+{"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I1 },
+{"or",      "t,r,I",    0,    (int) M_OR_I,	INSN_MACRO,		0,		I1 },
+{"ori",     "t,r,i",    0x34000000, 0xfc000000,	WR_t|RD_s,		0,		I1 },
+{"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		I5 },
+{"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		I5 },
   /* pref and prefx are at the start of the table.  */
-{"pul.ps",  "D,V,T",	0x46c0002e, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
-{"puu.ps",  "D,V,T",	0x46c0002f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
-{"pperm",   "s,t",	0x70000481, 0xfc00ffff,	MOD_HILO|RD_s|RD_t,	0,		SMT	},
-{"rach.ob", "X",	0x7a00003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX|SB1	},
-{"rach.ob", "D",	0x4a00003f, 0xfffff83f,	WR_D,			0,		N54	},
-{"rach.qh", "X",	0x7a20003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX	},
-{"racl.ob", "X",	0x7800003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX|SB1	},
-{"racl.ob", "D",	0x4800003f, 0xfffff83f,	WR_D,			0,		N54	},
-{"racl.qh", "X",	0x7820003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX	},
-{"racm.ob", "X",	0x7900003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX|SB1	},
-{"racm.ob", "D",	0x4900003f, 0xfffff83f,	WR_D,			0,		N54	},
-{"racm.qh", "X",	0x7920003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX	},
-{"recip.d", "D,S",	0x46200015, 0xffff003f, WR_D|RD_S|FP_D,		0,		I4_33	},
-{"recip.ps","D,S",	0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1	},
-{"recip.s", "D,S",	0x46000015, 0xffff003f, WR_D|RD_S|FP_S,		0,		I4_33	},
-{"recip1.d",  "D,S",	0x4620001d, 0xffff003f,	WR_D|RD_S|FP_D,		0,		M3D	},
-{"recip1.ps", "D,S",	0x46c0001d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
-{"recip1.s",  "D,S",	0x4600001d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
-{"recip2.d",  "D,S,T",	0x4620001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		M3D	},
-{"recip2.ps", "D,S,T",	0x46c0001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		M3D	},
-{"recip2.s",  "D,S,T",	0x4600001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		M3D	},
-{"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1	},
-{"rem",     "d,v,t",	0,    (int) M_REM_3,	INSN_MACRO,		0,		I1	},
-{"rem",     "d,v,I",	0,    (int) M_REM_3I,	INSN_MACRO,		0,		I1	},
-{"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1	},
-{"remu",    "d,v,t",	0,    (int) M_REMU_3,	INSN_MACRO,		0,		I1	},
-{"remu",    "d,v,I",	0,    (int) M_REMU_3I,	INSN_MACRO,		0,		I1	},
-{"rdhwr",   "t,K",	0x7c00003b, 0xffe007ff, WR_t,			0,		I33	},
-{"rdpgpr",  "d,w",	0x41400000, 0xffe007ff, WR_d,			0,		I33	},
-{"rfe",     "",		0x42000010, 0xffffffff,	0,			0,		I1|T3	},
-{"rnas.qh", "X,Q",	0x78200025, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
-{"rnau.ob", "X,Q",	0x78000021, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX|SB1	},
-{"rnau.qh", "X,Q",	0x78200021, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
-{"rnes.qh", "X,Q",	0x78200026, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
-{"rneu.ob", "X,Q",	0x78000022, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX|SB1	},
-{"rneu.qh", "X,Q",	0x78200022, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
-{"rol",     "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		0,		I1	},
-{"rol",     "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,		I1	},
-{"ror",     "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,		I1	},
-{"ror",     "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,		I1	},
-{"ror",	    "d,w,<",	0x00200002, 0xffe0003f,	WR_d|RD_t,		0,		N5|I33|SMT },
-{"rorv",    "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		N5|I33|SMT },
-{"rotl",    "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		0,		I33|SMT	},
-{"rotl",    "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,		I33|SMT	},
-{"rotr",    "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,		I33|SMT	},
-{"rotr",    "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,		I33|SMT	},
-{"rotrv",   "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		I33|SMT	},
-{"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33	},
-{"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
-{"round.w.s", "D,S",	0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
-{"rsqrt.d", "D,S",	0x46200016, 0xffff003f, WR_D|RD_S|FP_D,		0,		I4_33	},
-{"rsqrt.ps","D,S",	0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1	},
-{"rsqrt.s", "D,S",	0x46000016, 0xffff003f, WR_D|RD_S|FP_S,		0,		I4_33	},
-{"rsqrt1.d",  "D,S",	0x4620001e, 0xffff003f,	WR_D|RD_S|FP_D,		0,		M3D	},
-{"rsqrt1.ps", "D,S",	0x46c0001e, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
-{"rsqrt1.s",  "D,S",	0x4600001e, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
-{"rsqrt2.d",  "D,S,T",	0x4620001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		M3D	},
-{"rsqrt2.ps", "D,S,T",	0x46c0001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		M3D	},
-{"rsqrt2.s",  "D,S,T",	0x4600001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		M3D	},
-{"rzs.qh",  "X,Q",	0x78200024, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
-{"rzu.ob",  "X,Q",	0x78000020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX|SB1	},
-{"rzu.ob",  "D,k",	0x4bc00020, 0xffe0f83f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"rzu.qh",  "X,Q",	0x78200020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
-{"sb",      "t,o(b)",	0xa0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
-{"sb",      "t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO,		0,		I1	},
-{"sc",	    "t,o(b)",	0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	0,		I2	},
-{"sc",	    "t,A(b)",	0,    (int) M_SC_AB,	INSN_MACRO,		0,		I2	},
-{"scd",	    "t,o(b)",	0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	0,		I3	},
-{"scd",	    "t,A(b)",	0,    (int) M_SCD_AB,	INSN_MACRO,		0,		I3	},
-/* The macro has to be first to handle o32 correctly.  */
-{"sd",      "t,o(b)",	0,    (int) M_SD_OB,	INSN_MACRO,		0,		I1	},
-{"sd",      "t,o(b)",	0xfc000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
-{"sd",      "t,A(b)",	0,    (int) M_SD_AB,	INSN_MACRO,		0,		I1	},
-{"sdbbp",   "",		0x0000000e, 0xffffffff,	TRAP,           	0,		G2	},
-{"sdbbp",   "c",	0x0000000e, 0xfc00ffff,	TRAP,			0,		G2	},
-{"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,			0,		G2	},
-{"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,           	0,		I32     },
-{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           	0,		I32     },
-{"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
-{"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
-{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000, SM|RD_C2|RD_b,		0,		I2	},
-{"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		0,		I2	},
-{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000, SM|RD_C3|RD_b,		0,		I2	},
-{"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		0,		I2	},
-{"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
-{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		INSN2_M_FP_D,	I1	},
-{"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
-{"sdl",     "t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,		0,		I3	},
-{"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
-{"sdr",     "t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		0,		I3	},
-{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,	0,		I4_33	},
-{"seb",     "d,w",	0x7c000420, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
-{"seh",     "d,w",	0x7c000620, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
-{"selsl",   "d,v,t",	0x00000005, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		L1	},
-{"selsr",   "d,v,t",	0x00000001, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		L1	},
-{"seq",	    "d,v,t",	0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT	},
-{"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,		0,		I1	},
-{"seq",     "d,v,I",	0,    (int) M_SEQ_I,	INSN_MACRO,		0,		I1	},
-{"seq",	"S,T",		0x46a00032,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"seq",	"S,T",		0x4ba0000c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
-{"seqi",    "t,r,+Q",	0x7000002e, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
-{"sge",     "d,v,t",	0,    (int) M_SGE,	INSN_MACRO,		0,		I1	},
-{"sge",     "d,v,I",	0,    (int) M_SGE_I,	INSN_MACRO,		0,		I1	},
-{"sgeu",    "d,v,t",	0,    (int) M_SGEU,	INSN_MACRO,		0,		I1	},
-{"sgeu",    "d,v,I",	0,    (int) M_SGEU_I,	INSN_MACRO,		0,		I1	},
-{"sgt",     "d,v,t",	0,    (int) M_SGT,	INSN_MACRO,		0,		I1	},
-{"sgt",     "d,v,I",	0,    (int) M_SGT_I,	INSN_MACRO,		0,		I1	},
-{"sgtu",    "d,v,t",	0,    (int) M_SGTU,	INSN_MACRO,		0,		I1	},
-{"sgtu",    "d,v,I",	0,    (int) M_SGTU_I,	INSN_MACRO,		0,		I1	},
-{"sh",      "t,o(b)",	0xa4000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
-{"sh",      "t,A(b)",	0,    (int) M_SH_AB,	INSN_MACRO,		0,		I1	},
-{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54	},
-{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54	},
-{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54	},
-{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54	},
-{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"sle",     "d,v,t",	0,    (int) M_SLE,	INSN_MACRO,		0,		I1	},
-{"sle",     "d,v,I",	0,    (int) M_SLE_I,	INSN_MACRO,		0,		I1	},
-{"sle",	"S,T",		0x46a0003e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"sle",	"S,T",		0x4ba0000e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
-{"sleu",    "d,v,t",	0,    (int) M_SLEU,	INSN_MACRO,		0,		I1	},
-{"sleu",    "d,v,I",	0,    (int) M_SLEU_I,	INSN_MACRO,		0,		I1	},
-{"sleu",	"S,T",		0x4680003e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"sleu",	"S,T",		0x4b80000e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
-{"sllv",    "d,t,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
-{"sll",     "d,w,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* sllv */
-{"sll",     "d,w,<",	0x00000000, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
-{"sll",	"D,S,T",	0x45800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"sll",	"D,S,T",	0x4b00000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"sll.ob",  "X,Y,Q",	0x78000010, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"sll.ob",  "D,S,T[e]",	0x48000010, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"sll.ob",  "D,S,k",	0x4bc00010, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"sll.qh",  "X,Y,Q",	0x78200010, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"slt",     "d,v,t",	0x0000002a, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"slt",     "d,v,I",	0,    (int) M_SLT_I,	INSN_MACRO,		0,		I1	},
-{"slt",	"S,T",		0x46a0003c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"slt",	"S,T",		0x4ba0000d,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
-{"slti",    "t,r,j",	0x28000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
-{"sltiu",   "t,r,j",	0x2c000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
-{"sltu",    "d,v,t",	0x0000002b, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"sltu",    "d,v,I",	0,    (int) M_SLTU_I,	INSN_MACRO,		0,		I1	},
-{"sltu",	"S,T",		0x4680003c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"sltu",	"S,T",		0x4b80000d,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
-{"sne",	    "d,v,t",	0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT	},
-{"sne",     "d,v,t",	0,    (int) M_SNE,	INSN_MACRO,		0,		I1	},
-{"sne",     "d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO,		0,		I1	},
-{"snei",    "t,r,+Q",	0x7000002f, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
-{"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|FP_D,		0,		I2	},
-{"sqrt.s",  "D,S",	0x46000004, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
-{"sqrt.ps", "D,S",	0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1	},
-{"srav",    "d,t,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
-{"sra",     "d,w,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* srav */
-{"sra",     "d,w,<",	0x00000003, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
-{"sra",	"D,S,T",	0x45c00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"sra",	"D,S,T",	0x4b40000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"sra.qh",  "X,Y,Q",	0x78200013, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"srlv",    "d,t,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
-{"srl",     "d,w,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* srlv */
-{"srl",     "d,w,<",	0x00000002, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
-{"srl",	"D,S,T",	0x45800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"srl",	"D,S,T",	0x4b00000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"srl.ob",  "X,Y,Q",	0x78000012, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"srl.ob",  "D,S,T[e]",	0x48000012, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"srl.ob",  "D,S,k",	0x4bc00012, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"srl.qh",  "X,Y,Q",	0x78200012, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
+{"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		I5 },
+{"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		I5 },
+{"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,		0,		I4_33 },
+{"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,		0,		I4_33 },
+{"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1 },
+{"rem",     "d,v,t",    0,    (int) M_REM_3,	INSN_MACRO,		0,		I1 },
+{"rem",     "d,v,I",    0,    (int) M_REM_3I,	INSN_MACRO,		0,		I1 },
+{"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1 },
+{"remu",    "d,v,t",    0,    (int) M_REMU_3,	INSN_MACRO,		0,		I1 },
+{"remu",    "d,v,I",    0,    (int) M_REMU_3I,	INSN_MACRO,		0,		I1 },
+{"rdhwr",   "t,K",      0x7c00003b, 0xffe007ff, WR_t,			0,		I33 },
+{"rdpgpr",  "d,w",      0x41400000, 0xffe007ff, WR_d,			0,		I33 },
+{"rfe",     "",         0x42000010, 0xffffffff, 0,			0,		I1 },
+{"rol",     "d,v,t",    0,    (int) M_ROL,	INSN_MACRO,		0,		I1 },
+{"rol",     "d,v,I",    0,    (int) M_ROL_I,	INSN_MACRO,		0,		I1 },
+{"ror",     "d,v,t",    0,    (int) M_ROR,	INSN_MACRO,		0,		I1 },
+{"ror",     "d,v,I",    0,    (int) M_ROR_I,	INSN_MACRO,		0,		I1 },
+{"ror",	    "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,		0,		I33 },
+{"rorv",    "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,		0,		I33 },
+{"rotl",    "d,v,t",    0,    (int) M_ROL,	INSN_MACRO,		0,		I33 },
+{"rotl",    "d,v,I",    0,    (int) M_ROL_I,	INSN_MACRO,		0,		I33 },
+{"rotr",    "d,v,t",    0,    (int) M_ROR,	INSN_MACRO,		0,		I33 },
+{"rotr",    "d,v,I",    0,    (int) M_ROR_I,	INSN_MACRO,		0,		I33 },
+{"rotrv",   "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,		0,		I33 },
+{"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33 },
+{"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3 },
+{"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2 },
+{"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2 },
+{"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,		0,		I4_33 },
+{"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,		0,		I4_33 },
+{"sb",      "t,o(b)",   0xa0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1 },
+{"sb",      "t,A(b)",   0,    (int) M_SB_AB,	INSN_MACRO,         0,		I1 },
+{"sc",	    "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	0,		I2_R },
+{"sc",	    "t,A(b)",   0,    (int) M_SC_AB,	INSN_MACRO,         0,		I2_R },
+{"scd",	    "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	0,		I3 },
+{"scd",	    "t,A(b)",   0,    (int) M_SCD_AB,	INSN_MACRO,         0,		I3 },
+{"sd",	    "t,o(b)",   0xfc000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3 },
+{"sd",      "t,o(b)",   0,    (int) M_SD_OB,	INSN_MACRO,         0,		I1 },
+{"sd",      "t,A(b)",   0,    (int) M_SD_AB,	INSN_MACRO,         0,      I1 },
+{"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,           	0,		I32_R },
+{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           	0,		I32_R },
+{"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2 },
+{"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2 },
+{"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		0,		I2 },
+{"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		0,		I2 },
+{"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000, SM|RD_C2|RD_b,		0,		I2 },
+{"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		0,		I2 },
+{"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000, SM|RD_C3|RD_b,		0,		I2 },
+{"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		0,		I2 },
+{"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2 },
+{"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,		0,		I1 },
+{"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		0,		I1 },
+{"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3 },
+{"sdl",     "t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,		0,		I3 },
+{"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3 },
+{"sdr",     "t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		0,		I3 },
+{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,	0,		I4_33 },
+{"seb",     "d,w",      0x7c000420, 0xffe007ff, WR_d|RD_t,		0,		I33 },
+{"seh",     "d,w",      0x7c000620, 0xffe007ff, WR_d|RD_t,		0,		I33 },
+{"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,		0,		I1 },
+{"seq",     "d,v,I",	0,    (int) M_SEQ_I,	INSN_MACRO,		0,		I1 },
+{"sge",     "d,v,t",	0,    (int) M_SGE,	INSN_MACRO,		0,		I1 },
+{"sge",     "d,v,I",	0,    (int) M_SGE_I,	INSN_MACRO,		0,		I1 },
+{"sgeu",    "d,v,t",	0,    (int) M_SGEU,	INSN_MACRO,		0,		I1 },
+{"sgeu",    "d,v,I",	0,    (int) M_SGEU_I,	INSN_MACRO,		0,		I1 },
+{"sgt",     "d,v,t",	0,    (int) M_SGT,	INSN_MACRO,		0,		I1 },
+{"sgt",     "d,v,I",	0,    (int) M_SGT_I,	INSN_MACRO,		0,		I1 },
+{"sgtu",    "d,v,t",	0,    (int) M_SGTU,	INSN_MACRO,		0,		I1 },
+{"sgtu",    "d,v,I",	0,    (int) M_SGTU_I,	INSN_MACRO,		0,		I1 },
+{"sh",      "t,o(b)",	0xa4000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1 },
+{"sh",      "t,A(b)",	0,    (int) M_SH_AB,	INSN_MACRO,		0,		I1 },
+{"sle",     "d,v,t",	0,    (int) M_SLE,	INSN_MACRO,		0,		I1 },
+{"sle",     "d,v,I",	0,    (int) M_SLE_I,	INSN_MACRO,		0,		I1 },
+{"sleu",    "d,v,t",	0,    (int) M_SLEU,	INSN_MACRO,		0,		I1 },
+{"sleu",    "d,v,I",	0,    (int) M_SLEU_I,	INSN_MACRO,		0,		I1 },
+{"sllv",    "d,t,s",	0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,		0,		I1 },
+{"sll",     "d,w,s",	0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,		0,		I1 }, /* sllv */
+{"sll",     "d,w,<",	0x00000000, 0xffe0003f, WR_d|RD_t,		0,		I1 },
+{"slt",     "d,v,t",	0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I1 },
+{"slt",     "d,v,I",	0,    (int) M_SLT_I,	INSN_MACRO,		0,		I1 },
+{"slti",    "t,r,j",	0x28000000, 0xfc000000,	WR_t|RD_s,		0,		I1 },
+{"sltiu",   "t,r,j",	0x2c000000, 0xfc000000,	WR_t|RD_s,		0,		I1 },
+{"sltu",    "d,v,t",	0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I1 },
+{"sltu",    "d,v,I",	0,    (int) M_SLTU_I,	INSN_MACRO,		0,		I1 },
+{"sne",     "d,v,t",	0,    (int) M_SNE,	INSN_MACRO,		0,		I1 },
+{"sne",     "d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO,		0,		I1 },
+{"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,		0,		I2 },
+{"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2 },
+{"srav",    "d,t,s",	0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,		0,		I1 },
+{"sra",     "d,w,s",	0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,		0,		I1 }, /* srav */
+{"sra",     "d,w,<",	0x00000003, 0xffe0003f, WR_d|RD_t,		0,		I1 },
+{"srlv",    "d,t,s",	0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,		0,		I1 },
+{"srl",     "d,w,s",	0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,		0,		I1 }, /* srlv */
+{"srl",     "d,w,<",	0x00000002, 0xffe0003f, WR_d|RD_t,		0,		I1 },
 /* ssnop is at the start of the table.  */
-{"standby", "",         0x42000021, 0xffffffff,	0,			0,		V1	},
-{"sub",     "d,v,t",	0x00000022, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"sub",     "d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,		I1	},
-{"sub",	"D,S,T",	0x45c00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"sub",	"D,S,T",	0x4b40000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
-{"sub.d",   "D,V,T",	0x46200001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
-{"sub.s",   "D,V,T",	0x46000001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
-{"sub.ob",  "X,Y,Q",	0x7800000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"sub.ob",  "D,S,T",	0x4ac0000a, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"sub.ob",  "D,S,T[e]",	0x4800000a, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"sub.ob",  "D,S,k",	0x4bc0000a, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"sub.ps",  "D,V,T",	0x46c00001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33|IL2F	},
-{"sub.ps",  "D,V,T",	0x45600001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		IL2E	},
-{"sub.qh",  "X,Y,Q",	0x7820000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"suba.ob", "Y,Q",	0x78000036, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
-{"suba.qh", "Y,Q",	0x78200036, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"subl.ob", "Y,Q",	0x78000436, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
-{"subl.qh", "Y,Q",	0x78200436, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"subu",    "d,v,t",	0x00000023, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"subu",    "d,v,I",	0,    (int) M_SUBU_I,	INSN_MACRO,		0,		I1	},
-{"subu",	"D,S,T",	0x45800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"subu",	"D,S,T",	0x4b00000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
-{"suspend", "",         0x42000022, 0xffffffff,	0,			0,		V1	},
-{"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,	0,		I5_33|N55},
-{"sw",      "t,o(b)",	0xac000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
-{"sw",      "t,A(b)",	0,    (int) M_SW_AB,	INSN_MACRO,		0,		I1	},
-{"swapw",   "t,b",	0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b,	0,		XLR	},
-{"swapwu",  "t,b",	0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b,	0,		XLR	},
-{"swapd",   "t,b",	0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b,	0,		XLR	},
-{"swc0",    "E,o(b)",	0xe0000000, 0xfc000000,	SM|RD_C0|RD_b,		0,		I1	},
-{"swc0",    "E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,		0,		I1	},
-{"swc1",    "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	},
-{"swc1",    "E,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	},
-{"swc1",    "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"swc1",    "E,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"s.s",     "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	}, /* swc1 */
-{"s.s",     "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I1	},
-{"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		0,		I1	},
-{"swc3",    "E,o(b)",	0xec000000, 0xfc000000,	SM|RD_C3|RD_b,		0,		I1	},
-{"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		0,		I1	},
-{"swl",     "t,o(b)",	0xa8000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
-{"swl",     "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I1	},
-{"scache",  "t,o(b)",	0xa8000000, 0xfc000000,	RD_t|RD_b,		0,		I2	}, /* same */
-{"scache",  "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I2	}, /* as swl */
-{"swr",     "t,o(b)",	0xb8000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
-{"swr",     "t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I1	},
-{"invalidate", "t,o(b)",0xb8000000, 0xfc000000,	RD_t|RD_b,		0,		I2	}, /* same */
-{"invalidate", "t,A(b)",0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I2	}, /* as swr */
-{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,	0,		I4_33	},
-{"synciobdma", "",	0x0000008f, 0xffffffff,	NODS,			0,		IOCT	},
-{"syncs",   "",		0x0000018f, 0xffffffff,	NODS,			0,		IOCT	},
-{"syncw",   "",		0x0000010f, 0xffffffff,	NODS,			0,		IOCT	},
-{"syncws",  "",		0x0000014f, 0xffffffff,	NODS,			0,		IOCT	},
-{"sync_acquire", "",	0x0000044f, 0xffffffff,	NODS,			0,		I33	},
-{"sync_mb", "",		0x0000040f, 0xffffffff,	NODS,			0,		I33	},
-{"sync_release", "",	0x0000048f, 0xffffffff,	NODS,			0,		I33	},
-{"sync_rmb", "",	0x000004cf, 0xffffffff,	NODS,			0,		I33	},
-{"sync_wmb", "",	0x0000010f, 0xffffffff,	NODS,			0,		I33	},
-{"sync",    "",		0x0000000f, 0xffffffff,	NODS,			0,		I2|G1	},
-{"sync",    "1",	0x0000000f, 0xfffff83f,	NODS,			0,		I32	},
-{"sync.p",  "",		0x0000040f, 0xffffffff,	NODS,			0,		I2	},
-{"sync.l",  "",		0x0000000f, 0xffffffff,	NODS,			0,		I2	},
-{"synci",   "o(b)",	0x041f0000, 0xfc1f0000,	SM|RD_b,		0,		I33	},
-{"syscall", "",		0x0000000c, 0xffffffff,	TRAP,			0,		I1	},
-{"syscall", "B",	0x0000000c, 0xfc00003f,	TRAP,			0,		I1	},
-{"teqi",    "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
-{"teq",	    "s,t",	0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
-{"teq",	    "s,t,q",	0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
-{"teq",     "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* teqi */
-{"teq",     "s,I",	0,    (int) M_TEQ_I,	INSN_MACRO,		0,		I2	},
-{"tgei",    "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
-{"tge",	    "s,t",	0x00000030, 0xfc00ffff,	RD_s|RD_t|TRAP,		0,		I2	},
-{"tge",	    "s,t,q",	0x00000030, 0xfc00003f,	RD_s|RD_t|TRAP,		0,		I2	},
-{"tge",     "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* tgei */
-{"tge",	    "s,I",	0,    (int) M_TGE_I,    INSN_MACRO,		0,		I2	},
-{"tgeiu",   "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
-{"tgeu",    "s,t",	0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
-{"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
-{"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* tgeiu */
-{"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,		0,		I2	},
-{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,       	0,		I1   	},
-{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,       	0,		I1   	},
-{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,       	0,		I1   	},
-{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,       	0,		I1   	},
-{"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,		0,		I2	},
-{"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
-{"tlt",     "s,t,q",	0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
-{"tlt",     "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,		0,		I2	}, /* tlti */
-{"tlt",     "s,I",	0,    (int) M_TLT_I,	INSN_MACRO,		0,		I2	},
-{"tltiu",   "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
-{"tltu",    "s,t",	0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
-{"tltu",    "s,t,q",	0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
-{"tltu",    "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* tltiu */
-{"tltu",    "s,I",	0,    (int) M_TLTU_I,	INSN_MACRO,		0,		I2	},
-{"tnei",    "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
-{"tne",     "s,t",	0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
-{"tne",     "s,t,q",	0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
-{"tne",     "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* tnei */
-{"tne",     "s,I",	0,    (int) M_TNE_I,	INSN_MACRO,		0,		I2	},
-{"trunc.l.d", "D,S",	0x46200009, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33	},
-{"trunc.l.s", "D,S",	0x46000009, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3_33	},
-{"trunc.w.d", "D,S",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
-{"trunc.w.d", "D,S,x",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
-{"trunc.w.d", "D,S,t",	0,    (int) M_TRUNCWD,	INSN_MACRO,		INSN2_M_FP_S|INSN2_M_FP_D, I1 },
-{"trunc.w.s", "D,S",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I2	},
-{"trunc.w.s", "D,S,x",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I2	},
-{"trunc.w.s", "D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"uld",     "t,o(b)",	0,    (int) M_ULD,	INSN_MACRO,		0,		I3	},
-{"uld",     "t,A(b)",	0,    (int) M_ULD_A,	INSN_MACRO,		0,		I3	},
-{"ulh",     "t,o(b)",	0,    (int) M_ULH,	INSN_MACRO,		0,		I1	},
-{"ulh",     "t,A(b)",	0,    (int) M_ULH_A,	INSN_MACRO,		0,		I1	},
-{"ulhu",    "t,o(b)",	0,    (int) M_ULHU,	INSN_MACRO,		0,		I1	},
-{"ulhu",    "t,A(b)",	0,    (int) M_ULHU_A,	INSN_MACRO,		0,		I1	},
-{"ulw",     "t,o(b)",	0,    (int) M_ULW,	INSN_MACRO,		0,		I1	},
-{"ulw",     "t,A(b)",	0,    (int) M_ULW_A,	INSN_MACRO,		0,		I1	},
-{"usd",     "t,o(b)",	0,    (int) M_USD,	INSN_MACRO,		0,		I3	},
-{"usd",     "t,A(b)",	0,    (int) M_USD_A,	INSN_MACRO,		0,		I3	},
-{"ush",     "t,o(b)",	0,    (int) M_USH,	INSN_MACRO,		0,		I1	},
-{"ush",     "t,A(b)",	0,    (int) M_USH_A,	INSN_MACRO,		0,		I1	},
-{"usw",     "t,o(b)",	0,    (int) M_USW,	INSN_MACRO,		0,		I1	},
-{"usw",     "t,A(b)",	0,    (int) M_USW_A,	INSN_MACRO,		0,		I1	},
-{"v3mulu",  "d,v,t",	0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT	},
-{"vmm0",    "d,v,t",	0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT	},
-{"vmulu",   "d,v,t",	0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT	},
-{"wach.ob", "Y",	0x7a00003e, 0xffff07ff,	RD_S|FP_D,		WR_MACC,	MX|SB1	},
-{"wach.ob", "S",	0x4a00003e, 0xffff07ff,	RD_S,			0,		N54	},
-{"wach.qh", "Y",	0x7a20003e, 0xffff07ff,	RD_S|FP_D,		WR_MACC,	MX	},
-{"wacl.ob", "Y,Z",	0x7800003e, 0xffe007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
-{"wacl.ob", "S,T",	0x4800003e, 0xffe007ff,	RD_S|RD_T,		0,		N54	},
-{"wacl.qh", "Y,Z",	0x7820003e, 0xffe007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
-{"wait",    "",         0x42000020, 0xffffffff, NODS,   		0,		I3_32	},
-{"wait",    "J",        0x42000020, 0xfe00003f, NODS,   		0,		I32|N55	},
-{"waiti",   "",		0x42000020, 0xffffffff,	NODS,			0,		L1	},
-{"wrpgpr",  "d,w",	0x41c00000, 0xffe007ff, RD_t,			0,		I33	},
-{"wsbh",    "d,w",	0x7c0000a0, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
-{"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
-{"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		0,		I1	},
-{"xor",	"D,S,T",	0x47800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"xor",	"D,S,T",	0x4b800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"xor.ob",  "X,Y,Q",	0x7800000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
-{"xor.ob",  "D,S,T",	0x4ac0000d, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"xor.ob",  "D,S,T[e]",	0x4800000d, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"xor.ob",  "D,S,k",	0x4bc0000d, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
-{"xor.qh",  "X,Y,Q",	0x7820000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
-{"yield",   "s",	0x7c000009, 0xfc1fffff, NODS|RD_s,		0,		MT32	},
-{"yield",   "d,s",	0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s,		0,		MT32	},
-
-/* User Defined Instruction.  */
-{"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi0",     "s,t,+2",	0x70000010, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi0",     "s,+3",	0x70000010, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi0",     "+4",	0x70000010, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi1",     "s,t,+2",	0x70000011, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi1",     "s,+3",	0x70000011, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi1",     "+4",	0x70000011, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi2",     "s,t,+2",	0x70000012, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi2",     "s,+3",	0x70000012, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi2",     "+4",	0x70000012, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi3",     "s,t,+2",	0x70000013, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi3",     "s,+3",	0x70000013, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi3",     "+4",	0x70000013, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi4",     "s,t,+2",	0x70000014, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi4",     "s,+3",	0x70000014, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi4",     "+4",	0x70000014, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi5",     "s,t,+2",	0x70000015, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi5",     "s,+3",	0x70000015, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi5",     "+4",	0x70000015, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi6",     "s,t,+2",	0x70000016, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi6",     "s,+3",	0x70000016, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi6",     "+4",	0x70000016, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi7",     "s,t,+2",	0x70000017, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi7",     "s,+3",	0x70000017, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi7",     "+4",	0x70000017, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi8",     "s,t,+2",	0x70000018, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi8",     "s,+3",	0x70000018, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi8",     "+4",	0x70000018, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi9",      "s,t,+2",	0x70000019, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi9",     "s,+3",	0x70000019, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi9",     "+4",	0x70000019, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi10",    "s,t,+2",	0x7000001a, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi10",    "s,+3",	0x7000001a, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi10",    "+4",	0x7000001a, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi11",    "s,t,+2",	0x7000001b, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi11",    "s,+3",	0x7000001b, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi11",    "+4",	0x7000001b, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi12",    "s,t,+2",	0x7000001c, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi12",    "s,+3",	0x7000001c, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi12",    "+4",	0x7000001c, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi13",    "s,t,+2",	0x7000001d, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi13",    "s,+3",	0x7000001d, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi13",    "+4",	0x7000001d, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi14",    "s,t,+2",	0x7000001e, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi14",    "s,+3",	0x7000001e, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi14",    "+4",	0x7000001e, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi15",    "s,t,+2",	0x7000001f, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi15",    "s,+3",	0x7000001f, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-{"udi15",    "+4",	0x7000001f, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
-
-/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
-   instructions so they are here for the latters to take precedence.  */
-{"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		0,		I1	},
-{"bc2f",    "N,p",	0x49000000, 0xffe30000,	CBD|RD_CC,		0,		I32	},
-{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3	},
-{"bc2fl",   "N,p",	0x49020000, 0xffe30000,	CBL|RD_CC,		0,		I32	},
-{"bc2t",    "p",	0x49010000, 0xffff0000,	CBD|RD_CC,		0,		I1	},
-{"bc2t",    "N,p",	0x49010000, 0xffe30000,	CBD|RD_CC,		0,		I32	},
-{"bc2tl",   "p",	0x49030000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3	},
-{"bc2tl",   "N,p",	0x49030000, 0xffe30000,	CBL|RD_CC,		0,		I32	},
-{"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I1	},
-{"ctc2",    "t,G",	0x48c00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1	},
-{"dmfc2",   "t,i",	0x48200000, 0xffe00000,	LCD|WR_t|RD_C2,		0,		IOCT	},
-{"dmfc2",   "t,G",	0x48200000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I3	},
-{"dmfc2",   "t,G,H",	0x48200000, 0xffe007f8,	LCD|WR_t|RD_C2,		0,		I64	},
-{"dmtc2",   "t,i",	0x48a00000, 0xffe00000,	COD|RD_t|WR_C2|WR_CC,	0,		IOCT	},
-{"dmtc2",   "t,G",	0x48a00000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	0,		I3	},
-{"dmtc2",   "t,G,H",	0x48a00000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	0,		I64	},
-{"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I1	},
-{"mfc2",    "t,G,H",	0x48000000, 0xffe007f8,	LCD|WR_t|RD_C2,		0,		I32	},
-{"mfhc2",   "t,G",	0x48600000, 0xffe007ff,	LCD|WR_t|RD_C2,		0,		I33	},
-{"mfhc2",   "t,G,H",	0x48600000, 0xffe007f8,	LCD|WR_t|RD_C2,		0,		I33	},
-{"mfhc2",   "t,i",	0x48600000, 0xffe00000,	LCD|WR_t|RD_C2,		0,		I33	},
-{"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	0,		I1	},
-{"mtc2",    "t,G,H",	0x48800000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	0,		I32	},
-{"mthc2",   "t,G",	0x48e00000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	0,		I33	},
-{"mthc2",   "t,G,H",	0x48e00000, 0xffe007f8,	COD|RD_t|WR_C2|WR_CC,	0,		I33	},
-{"mthc2",   "t,i",	0x48e00000, 0xffe00000,	COD|RD_t|WR_C2|WR_CC,	0,		I33	},
-
-/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
-   instructions, so they are here for the latters to take precedence.  */
-{"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC,		0,		I1	},
-{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3	},
-{"bc3t",    "p",	0x4d010000, 0xffff0000,	CBD|RD_CC,		0,		I1	},
-{"bc3tl",   "p",	0x4d030000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3	},
-{"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I1	},
-{"ctc3",    "t,G",	0x4cc00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1	},
-{"dmfc3",   "t,G",	0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 	0,		I3	},
-{"dmtc3",   "t,G",	0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,	0,		I3	},
-{"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,		0,		I1	},
-{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 	0,		I32     },
-{"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	0,		I1	},
-{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,		I32     },
-
-  /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
-     4010 any more, so move this insn out of the way.  If the object
-     format gave us more info, we could do this right.  */
-{"addciu",  "t,r,j",	0x70000000, 0xfc000000,	WR_t|RD_s,		0,		L1	},
-/* MIPS DSP ASE */
-{"absq_s.ph", "d,t",	0x7c000252, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"absq_s.pw", "d,t",	0x7c000456, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"absq_s.qh", "d,t",	0x7c000256, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"absq_s.w", "d,t",	0x7c000452, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"addq.ph", "d,s,t",	0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"addq.pw", "d,s,t",	0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"addq.qh", "d,s,t",	0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"addq_s.ph", "d,s,t",	0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"addq_s.pw", "d,s,t",	0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"addq_s.qh", "d,s,t",	0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"addq_s.w", "d,s,t",	0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"addsc",   "d,s,t",	0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"addu.ob", "d,s,t",	0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"addu.qb", "d,s,t",	0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"addu_s.ob", "d,s,t",	0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"addu_s.qb", "d,s,t",	0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"addwc",   "d,s,t",	0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"bitrev",  "d,t",	0x7c0006d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"bposge32", "p",	0x041c0000, 0xffff0000, CBD,			0,		D32	},
-{"bposge64", "p",	0x041d0000, 0xffff0000, CBD,			0,		D64	},
-{"cmp.eq.ph", "s,t",	0x7c000211, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
-{"cmp.eq.pw", "s,t",	0x7c000415, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmp.eq.qh", "s,t",	0x7c000215, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
-{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
-{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
-{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
-{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
-{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
-{"cmp.le.ph", "s,t",	0x7c000291, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
-{"cmp.le.pw", "s,t",	0x7c000495, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmp.le.qh", "s,t",	0x7c000295, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmp.lt.ph", "s,t",	0x7c000251, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
-{"cmp.lt.pw", "s,t",	0x7c000455, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmp.lt.qh", "s,t",	0x7c000255, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmpu.eq.ob", "s,t",	0x7c000015, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmpu.eq.qb", "s,t",	0x7c000011, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
-{"cmpu.le.ob", "s,t",	0x7c000095, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmpu.le.qb", "s,t",	0x7c000091, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
-{"cmpu.lt.ob", "s,t",	0x7c000055, 0xfc00ffff, RD_s|RD_t,		0,		D64	},
-{"cmpu.lt.qb", "s,t",	0x7c000051, 0xfc00ffff, RD_s|RD_t,		0,		D32	},
-{"dextpdp", "t,7,6",	0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,	0,		D64	},
-{"dextpdpv", "t,7,s",	0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,		D64	},
-{"dextp",   "t,7,6",	0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
-{"dextpv",  "t,7,s",	0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
-{"dextr.l", "t,7,6",	0x7c00043c, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
-{"dextr_r.l", "t,7,6",	0x7c00053c, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
-{"dextr_rs.l", "t,7,6",	0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
-{"dextr_rs.w", "t,7,6",	0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
-{"dextr_r.w", "t,7,6",	0x7c00013c, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
-{"dextr_s.h", "t,7,6",	0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
-{"dextrv.l", "t,7,s",	0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
-{"dextrv_r.l", "t,7,s",	0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
-{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,	0,		D64	},
-{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,	0,		D64	},
-{"dextrv_r.w", "t,7,s",	0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
-{"dextrv_s.h", "t,7,s",	0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
-{"dextrv.w", "t,7,s",	0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D64	},
-{"dextr.w", "t,7,6",	0x7c00003c, 0xfc00e7ff, WR_t|RD_a,		0,		D64	},
-{"dinsv",   "t,s",	0x7c00000d, 0xfc00ffff, WR_t|RD_s,		0,		D64	},
-{"dmadd",   "7,s,t",	0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dmaddu",  "7,s,t",	0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dmsub",   "7,s,t",	0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dmsubu",  "7,s,t",	0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dmthlip", "s,7",	0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,	0,		D64	},
-{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dpau.h.obl", "7,s,t",	0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dpau.h.obr", "7,s,t",	0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dpau.h.qbl", "7,s,t",	0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"dpau.h.qbr", "7,s,t",	0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dpsu.h.obl", "7,s,t",	0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dpsu.h.obr", "7,s,t",	0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"dpsu.h.qbl", "7,s,t",	0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"dpsu.h.qbr", "7,s,t",	0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"dshilo",  "7,:",	0x7c0006bc, 0xfc07e7ff, MOD_a,			0,		D64	},
-{"dshilov", "7,s",	0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,		0,		D64	},
-{"extpdp",  "t,7,6",	0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,	0,		D32	},
-{"extpdpv", "t,7,s",	0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,		D32	},
-{"extp",    "t,7,6",	0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,		0,		D32	},
-{"extpv",   "t,7,s",	0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D32	},
-{"extr_rs.w", "t,7,6",	0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,		0,		D32	},
-{"extr_r.w", "t,7,6",	0x7c000138, 0xfc00e7ff, WR_t|RD_a,		0,		D32	},
-{"extr_s.h", "t,7,6",	0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,		0,		D32	},
-{"extrv_rs.w", "t,7,s",	0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D32	},
-{"extrv_r.w", "t,7,s",	0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D32	},
-{"extrv_s.h", "t,7,s",	0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D32	},
-{"extrv.w", "t,7,s",	0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,		0,		D32	},
-{"extr.w",  "t,7,6",	0x7c000038, 0xfc00e7ff, WR_t|RD_a,		0,		D32	},
-{"insv",    "t,s",	0x7c00000c, 0xfc00ffff, WR_t|RD_s,		0,		D32	},
-{"lbux",    "d,t(b)",	0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D32	},
-{"ldx",     "d,t(b)",	0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D64	},
-{"lhx",     "d,t(b)",	0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D32	},
-{"lwx",     "d,t(b)",	0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D32	},
-{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"modsub",  "d,s,t",	0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"mthlip",  "s,7",	0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,	0,		D32	},
-{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D64	},
-{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D64	},
-{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
-{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
-{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
-{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D32	},
-{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D64	},
-{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		D64	},
-{"mulq_rs.ph", "d,s,t",	0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		D32	},
-{"mulq_rs.qh", "d,s,t",	0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		D64	},
-{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D32	},
-{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,		D64	},
-{"packrl.ph", "d,s,t",	0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"packrl.pw", "d,s,t",	0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"pick.ob", "d,s,t",	0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"pick.ph", "d,s,t",	0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"pick.pw", "d,s,t",	0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"pick.qb", "d,s,t",	0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"pick.qh", "d,s,t",	0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceq.w.phl", "d,t",	0x7c000312, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"preceq.w.phr", "d,t",	0x7c000352, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
-{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
-{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
-{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
-{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
-{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
-{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
-{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D64	},
-{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,	0,		D32	},
-{"raddu.l.ob", "d,s",	0x7c000514, 0xfc1f07ff, WR_d|RD_s,		0,		D64	},
-{"raddu.w.qb", "d,s",	0x7c000510, 0xfc1f07ff, WR_d|RD_s,		0,		D32	},
-{"rddsp",   "d",	0x7fff04b8, 0xffff07ff, WR_d,			0,		D32	},
-{"rddsp",   "d,'",	0x7c0004b8, 0xffc007ff, WR_d,			0,		D32	},
-{"repl.ob", "d,5",	0x7c000096, 0xff0007ff, WR_d,			0,		D64	},
-{"repl.ph", "d,@",	0x7c000292, 0xfc0007ff, WR_d,			0,		D32	},
-{"repl.pw", "d,@",	0x7c000496, 0xfc0007ff, WR_d,			0,		D64	},
-{"repl.qb", "d,5",	0x7c000092, 0xff0007ff, WR_d,			0,		D32	},
-{"repl.qh", "d,@",	0x7c000296, 0xfc0007ff, WR_d,			0,		D64	},
-{"replv.ob", "d,t",	0x7c0000d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"replv.ph", "d,t",	0x7c0002d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"replv.pw", "d,t",	0x7c0004d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"replv.qb", "d,t",	0x7c0000d2, 0xffe007ff, WR_d|RD_t,		0,		D32	},
-{"replv.qh", "d,t",	0x7c0002d6, 0xffe007ff, WR_d|RD_t,		0,		D64	},
-{"shilo",   "7,0",	0x7c0006b8, 0xfc0fe7ff, MOD_a,			0,		D32	},
-{"shilov",  "7,s",	0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,		0,		D32	},
-{"shll.ob", "d,t,3",	0x7c000017, 0xff0007ff, WR_d|RD_t,		0,		D64	},
-{"shll.ph", "d,t,4",	0x7c000213, 0xfe0007ff, WR_d|RD_t,		0,		D32	},
-{"shll.pw", "d,t,6",	0x7c000417, 0xfc0007ff, WR_d|RD_t,		0,		D64	},
-{"shll.qb", "d,t,3",	0x7c000013, 0xff0007ff, WR_d|RD_t,		0,		D32	},
-{"shll.qh", "d,t,4",	0x7c000217, 0xfe0007ff, WR_d|RD_t,		0,		D64	},
-{"shll_s.ph", "d,t,4",	0x7c000313, 0xfe0007ff, WR_d|RD_t,		0,		D32	},
-{"shll_s.pw", "d,t,6",	0x7c000517, 0xfc0007ff, WR_d|RD_t,		0,		D64	},
-{"shll_s.qh", "d,t,4",	0x7c000317, 0xfe0007ff, WR_d|RD_t,		0,		D64	},
-{"shll_s.w", "d,t,6",	0x7c000513, 0xfc0007ff, WR_d|RD_t,		0,		D32	},
-{"shllv.ob", "d,t,s",	0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shllv.ph", "d,t,s",	0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"shllv.pw", "d,t,s",	0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shllv.qb", "d,t,s",	0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"shllv.qh", "d,t,s",	0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shllv_s.ph", "d,t,s",	0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"shllv_s.pw", "d,t,s",	0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shllv_s.qh", "d,t,s",	0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shllv_s.w", "d,t,s",	0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"shra.ph", "d,t,4",	0x7c000253, 0xfe0007ff, WR_d|RD_t,		0,		D32	},
-{"shra.pw", "d,t,6",	0x7c000457, 0xfc0007ff, WR_d|RD_t,		0,		D64	},
-{"shra.qh", "d,t,4",	0x7c000257, 0xfe0007ff, WR_d|RD_t,		0,		D64	},
-{"shra_r.ph", "d,t,4",	0x7c000353, 0xfe0007ff, WR_d|RD_t,		0,		D32	},
-{"shra_r.pw", "d,t,6",	0x7c000557, 0xfc0007ff, WR_d|RD_t,		0,		D64	},
-{"shra_r.qh", "d,t,4",	0x7c000357, 0xfe0007ff, WR_d|RD_t,		0,		D64	},
-{"shra_r.w", "d,t,6",	0x7c000553, 0xfc0007ff, WR_d|RD_t,		0,		D32	},
-{"shrav.ph", "d,t,s",	0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"shrav.pw", "d,t,s",	0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shrav.qh", "d,t,s",	0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shrav_r.ph", "d,t,s",	0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"shrav_r.pw", "d,t,s",	0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shrav_r.qh", "d,t,s",	0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shrav_r.w", "d,t,s",	0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"shrl.ob", "d,t,3",	0x7c000057, 0xff0007ff, WR_d|RD_t,		0,		D64	},
-{"shrl.qb", "d,t,3",	0x7c000053, 0xff0007ff, WR_d|RD_t,		0,		D32	},
-{"shrlv.ob", "d,t,s",	0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"shrlv.qb", "d,t,s",	0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"subq.ph", "d,s,t",	0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"subq.pw", "d,s,t",	0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"subq.qh", "d,s,t",	0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"subq_s.ph", "d,s,t",	0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"subq_s.pw", "d,s,t",	0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"subq_s.qh", "d,s,t",	0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"subq_s.w", "d,s,t",	0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"subu.ob", "d,s,t",	0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"subu.qb", "d,s,t",	0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"subu_s.ob", "d,s,t",	0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D64	},
-{"subu_s.qb", "d,s,t",	0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		D32	},
-{"wrdsp",   "s",	0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,		0,		D32	},
-{"wrdsp",   "s,8",	0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,		0,		D32	},
-/* MIPS DSP ASE Rev2 */
-{"absq_s.qb", "d,t",	0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33	},
-{"addu.ph", "d,s,t",	0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"addu_s.ph", "d,s,t",	0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"adduh.qb", "d,s,t",	0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"adduh_r.qb", "d,s,t",	0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"append",  "t,s,h",	0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33	},
-{"balign",  "t,s,I",	0,    (int) M_BALIGN,	INSN_MACRO,             0,              D33	},
-{"balign",  "t,s,2",	0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33	},
-{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33	},
-{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33	},
-{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33	},
-{"dpa.w.ph", "7,s,t",	0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
-{"dps.w.ph", "7,s,t",	0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
-{"mul.ph",  "d,s,t",	0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33	},
-{"mul_s.ph", "d,s,t",	0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33	},
-{"mulq_rs.w", "d,s,t",	0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33	},
-{"mulq_s.ph", "d,s,t",	0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33	},
-{"mulq_s.w", "d,s,t",	0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33	},
-{"mulsa.w.ph", "7,s,t",	0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
-{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33	},
-{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33	},
-{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33	},
-{"prepend", "t,s,h",	0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33	},
-{"shra.qb", "d,t,3",	0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33	},
-{"shra_r.qb", "d,t,3",	0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33	},
-{"shrav.qb", "d,t,s",	0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"shrav_r.qb", "d,t,s",	0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"shrl.ph", "d,t,4",	0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33	},
-{"shrlv.ph", "d,t,s",	0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"subu.ph", "d,s,t",	0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"subu_s.ph", "d,s,t",	0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"subuh.qb", "d,s,t",	0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"subuh_r.qb", "d,s,t",	0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33	},
-{"addqh.ph", "d,s,t",	0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,		0,              D33	},
-{"addqh_r.ph", "d,s,t",	0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,		0,              D33	},
-{"addqh.w", "d,s,t",	0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,		0,              D33	},
-{"addqh_r.w", "d,s,t",	0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,		0,              D33	},
-{"subqh.ph", "d,s,t",	0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,		0,              D33	},
-{"subqh_r.ph", "d,s,t",	0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,              D33	},
-{"subqh.w", "d,s,t",	0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,		0,              D33	},
-{"subqh_r.w", "d,s,t",	0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,		0,              D33	},
-{"dpax.w.ph", "7,s,t",	0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,              D33	},
-{"dpsx.w.ph", "7,s,t",	0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,              D33	},
-{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,              D33	},
-{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,              D33	},
-{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,              D33	},
-{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,	0,              D33	},
-/* Move bc0* after mftr and mttr to avoid opcode collision.  */
-{"bc0f",    "p",	0x41000000, 0xffff0000,	CBD|RD_CC,		0,		I1	},
-{"bc0fl",   "p",	0x41020000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3	},
-{"bc0t",    "p",	0x41010000, 0xffff0000,	CBD|RD_CC,		0,		I1	},
-{"bc0tl",   "p",	0x41030000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3	},
-/* ST Microelectronics Loongson-2E and -2F.  */
-{"mult.g",	"d,s,t",	0x7c000018,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"mult.g",	"d,s,t",	0x70000010,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsmult",	"d,s,t",	0x70000010,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"multu.g",	"d,s,t",	0x7c000019,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"multu.g",	"d,s,t",	0x70000012,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsmultu",	"d,s,t",	0x70000012,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"dmult.g",	"d,s,t",	0x7c00001c,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"dmult.g",	"d,s,t",	0x70000011,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsdmult",	"d,s,t",	0x70000011,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"dmultu.g",	"d,s,t",	0x7c00001d,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"dmultu.g",	"d,s,t",	0x70000013,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsdmultu",	"d,s,t",	0x70000013,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"div.g",	"d,s,t",	0x7c00001a,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"div.g",	"d,s,t",	0x70000014,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsdiv",	"d,s,t",	0x70000014,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"divu.g",	"d,s,t",	0x7c00001b,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"divu.g",	"d,s,t",	0x70000016,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsdivu",	"d,s,t",	0x70000016,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"ddiv.g",	"d,s,t",	0x7c00001e,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"ddiv.g",	"d,s,t",	0x70000015,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsddiv",	"d,s,t",	0x70000015,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"ddivu.g",	"d,s,t",	0x7c00001f,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"ddivu.g",	"d,s,t",	0x70000017,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsddivu",	"d,s,t",	0x70000017,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"mod.g",	"d,s,t",	0x7c000022,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"mod.g",	"d,s,t",	0x7000001c,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsmod",	"d,s,t",	0x7000001c,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"modu.g",	"d,s,t",	0x7c000023,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"modu.g",	"d,s,t",	0x7000001e,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsmodu",	"d,s,t",	0x7000001e,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"dmod.g",	"d,s,t",	0x7c000026,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"dmod.g",	"d,s,t",	0x7000001d,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsdmod",	"d,s,t",	0x7000001d,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"dmodu.g",	"d,s,t",	0x7c000027,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
-{"dmodu.g",	"d,s,t",	0x7000001f,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
-{"gsdmodu",	"d,s,t",	0x7000001f,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
-{"packsshb",	"D,S,T",	0x47400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"packsshb",	"D,S,T",	0x4b400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"packsswh",	"D,S,T",	0x47200002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"packsswh",	"D,S,T",	0x4b200002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"packushb",	"D,S,T",	0x47600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"packushb",	"D,S,T",	0x4b600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"paddb",	"D,S,T",	0x47c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddb",	"D,S,T",	0x4bc00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"paddh",	"D,S,T",	0x47400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddh",	"D,S,T",	0x4b400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"paddw",	"D,S,T",	0x47600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddw",	"D,S,T",	0x4b600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"paddd",	"D,S,T",	0x47e00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddd",	"D,S,T",	0x4be00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"paddsb",	"D,S,T",	0x47800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddsb",	"D,S,T",	0x4b800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"paddsh",	"D,S,T",	0x47000000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddsh",	"D,S,T",	0x4b000000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"paddusb",	"D,S,T",	0x47a00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddusb",	"D,S,T",	0x4ba00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"paddush",	"D,S,T",	0x47200000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddush",	"D,S,T",	0x4b200000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pandn",	"D,S,T",	0x47e00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pandn",	"D,S,T",	0x4be00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pavgb",	"D,S,T",	0x46600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pavgb",	"D,S,T",	0x4b200008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pavgh",	"D,S,T",	0x46400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pavgh",	"D,S,T",	0x4b000008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pcmpeqb",	"D,S,T",	0x46c00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpeqb",	"D,S,T",	0x4b800009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pcmpeqh",	"D,S,T",	0x46800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpeqh",	"D,S,T",	0x4b400009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pcmpeqw",	"D,S,T",	0x46400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpeqw",	"D,S,T",	0x4b000009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pcmpgtb",	"D,S,T",	0x46e00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpgtb",	"D,S,T",	0x4ba00009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pcmpgth",	"D,S,T",	0x46a00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpgth",	"D,S,T",	0x4b600009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pcmpgtw",	"D,S,T",	0x46600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpgtw",	"D,S,T",	0x4b200009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pextrh",	"D,S,T",	0x45c00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pextrh",	"D,S,T",	0x4b40000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pinsrh_0",	"D,S,T",	0x47800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pinsrh_0",	"D,S,T",	0x4b800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pinsrh_1",	"D,S,T",	0x47a00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pinsrh_1",	"D,S,T",	0x4ba00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pinsrh_2",	"D,S,T",	0x47c00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pinsrh_2",	"D,S,T",	0x4bc00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pinsrh_3",	"D,S,T",	0x47e00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pinsrh_3",	"D,S,T",	0x4be00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pmaddhw",	"D,S,T",	0x45e00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmaddhw",	"D,S,T",	0x4b60000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pmaxsh",	"D,S,T",	0x46800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmaxsh",	"D,S,T",	0x4b400008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pmaxub",	"D,S,T",	0x46c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmaxub",	"D,S,T",	0x4b800008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pminsh",	"D,S,T",	0x46a00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pminsh",	"D,S,T",	0x4b600008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pminub",	"D,S,T",	0x46e00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pminub",	"D,S,T",	0x4ba00008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pmovmskb",	"D,S",		0x46a00005,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2E	},
-{"pmovmskb",	"D,S",		0x4ba0000f,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pmulhuh",	"D,S,T",	0x46e00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmulhuh",	"D,S,T",	0x4ba0000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pmulhh",	"D,S,T",	0x46a00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmulhh",	"D,S,T",	0x4b60000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pmullh",	"D,S,T",	0x46800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmullh",	"D,S,T",	0x4b40000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pmuluw",	"D,S,T",	0x46c00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmuluw",	"D,S,T",	0x4b80000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pasubub",	"D,S,T",	0x45a00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pasubub",	"D,S,T",	0x4b20000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"biadd",	"D,S",		0x46800005,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2E	},
-{"biadd",	"D,S",		0x4b80000f,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"pshufh",	"D,S,T",	0x47000002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pshufh",	"D,S,T",	0x4b000002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psllh",	"D,S,T",	0x46600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psllh",	"D,S,T",	0x4b20000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psllw",	"D,S,T",	0x46400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psllw",	"D,S,T",	0x4b00000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psrah",	"D,S,T",	0x46a00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psrah",	"D,S,T",	0x4b60000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psraw",	"D,S,T",	0x46800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psraw",	"D,S,T",	0x4b40000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psrlh",	"D,S,T",	0x46600003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psrlh",	"D,S,T",	0x4b20000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psrlw",	"D,S,T",	0x46400003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psrlw",	"D,S,T",	0x4b00000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psubb",	"D,S,T",	0x47c00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubb",	"D,S,T",	0x4bc00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psubh",	"D,S,T",	0x47400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubh",	"D,S,T",	0x4b400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psubw",	"D,S,T",	0x47600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubw",	"D,S,T",	0x4b600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psubd",	"D,S,T",	0x47e00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubd",	"D,S,T",	0x4be00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psubsb",	"D,S,T",	0x47800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubsb",	"D,S,T",	0x4b800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psubsh",	"D,S,T",	0x47000001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubsh",	"D,S,T",	0x4b000001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psubusb",	"D,S,T",	0x47a00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubusb",	"D,S,T",	0x4ba00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"psubush",	"D,S,T",	0x47200001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubush",	"D,S,T",	0x4b200001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"punpckhbh",	"D,S,T",	0x47600003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpckhbh",	"D,S,T",	0x4b600003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"punpckhhw",	"D,S,T",	0x47200003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpckhhw",	"D,S,T",	0x4b200003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"punpckhwd",	"D,S,T",	0x46e00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpckhwd",	"D,S,T",	0x4ba0000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"punpcklbh",	"D,S,T",	0x47400003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpcklbh",	"D,S,T",	0x4b400003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"punpcklhw",	"D,S,T",	0x47000003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpcklhw",	"D,S,T",	0x4b000003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"punpcklwd",	"D,S,T",	0x46c00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpcklwd",	"D,S,T",	0x4b80000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
-{"sequ",	"S,T",		0x46800032,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"sequ",	"S,T",		0x4b80000c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
+{"sub",     "d,v,t",	0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I1 },
+{"sub",     "d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,		I1 },
+{"sub.d",   "D,V,T",	0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		I1 },
+{"sub.s",   "D,V,T",	0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,	0,		I1 },
+{"sub.ps",  "D,V,T",	0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		I5 },
+{"subu",    "d,v,t",	0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I1 },
+{"subu",    "d,v,I",	0,    (int) M_SUBU_I,	INSN_MACRO,		0,		I1 },
+{"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,	0,		I5 },
+{"sw",      "t,o(b)",	0xac000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1 },
+{"sw",      "t,A(b)",	0,    (int) M_SW_AB,	INSN_MACRO,		0,		I1 },
+{"swc0",    "E,o(b)",	0xe0000000, 0xfc000000,	SM|RD_C0|RD_b,		0,		I1 },
+{"swc0",    "E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,		0,		I1 },
+{"swc1",    "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1 },
+{"swc1",    "E,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1 },
+{"swc1",    "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		0,		I1 },
+{"swc1",    "E,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		0,		I1 },
+{"s.s",     "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1 }, /* swc1 */
+{"s.s",     "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		0,		I1 },
+{"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I1 },
+{"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		0,		I1 },
+{"swc3",    "E,o(b)",	0xec000000, 0xfc000000,	SM|RD_C3|RD_b,		0,		I1 },
+{"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		0,		I1 },
+{"swl",     "t,o(b)",	0xa8000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1 },
+{"swl",     "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I1 },
+{"scache",  "t,o(b)",	0xa8000000, 0xfc000000,	RD_t|RD_b,		0,		I2 }, /* same */
+{"scache",  "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I2 }, /* as swl */
+{"swr",     "t,o(b)",	0xb8000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1 },
+{"swr",     "t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I1 },
+{"invalidate", "t,o(b)",0xb8000000, 0xfc000000,	RD_t|RD_b,		0,		I2 }, /* same */
+{"invalidate", "t,A(b)",0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I2 }, /* as swr */
+{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,	0,		I4_33 },
+{"sync",    "",		0x0000000f, 0xffffffff,	NODS,		0,		I2_R	},
+{"sync",    "1",	0x0000000f, 0xfffff83f,	NODS,		0,		I2_R	},
+{"sync.p",  "",         0x0000040f, 0xffffffff, NODS,		0,		I2 },
+{"sync.l",  "",         0x0000000f, 0xffffffff, NODS,		0,		I2 },
+{"synci",   "o(b)",     0x041f0000, 0xfc1f0000,	SM|RD_b,		0,		I33 },
+{"syscall", "",         0x0000000c, 0xffffffff, TRAP,			0,		I1 },
+{"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,			0,		I1 },
+{"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,		0,		I2 },
+{"teq",	    "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2 },
+{"teq",	    "s,t,q",	0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2 },
+{"teq",     "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		0,	 	I2 }, /* teqi */
+{"teq",     "s,I",	0,    (int) M_TEQ_I,	INSN_MACRO,		0,		I2 },
+{"tgei",    "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,		0,		I2 },
+{"tge",	    "s,t",	0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2 },
+{"tge",	    "s,t,q",	0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2 },
+{"tge",     "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,		0,		I2 }, /* tgei */
+{"tge",	    "s,I",	0,    (int) M_TGE_I,    INSN_MACRO,		0,		I2 },
+{"tgeiu",   "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,		0,		I2 },
+{"tgeu",    "s,t",	0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2 },
+{"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2 },
+{"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,		0,		I2 }, /* tgeiu */
+{"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,		0,		I2 },
+{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,       	0,		I1    },
+{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,       	0,		I1    },
+{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,       	0,		I1    },
+{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,       	0,		I1    },
+{"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,		0,		I2 },
+{"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2 },
+{"tlt",     "s,t,q",	0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2 },
+{"tlt",     "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,		0,		I2 }, /* tlti */
+{"tlt",     "s,I",	0,    (int) M_TLT_I,	INSN_MACRO,		0,		I2 },
+{"tltiu",   "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,		0,		I2 },
+{"tltu",    "s,t",	0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2 },
+{"tltu",    "s,t,q",	0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2 },
+{"tltu",    "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,		0,		I2 }, /* tltiu */
+{"tltu",    "s,I",	0,    (int) M_TLTU_I,	INSN_MACRO,		0,		I2 },
+{"tnei",    "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,		0,		I2 },
+{"tne",     "s,t",	0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2 },
+{"tne",     "s,t,q",	0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2 },
+{"tne",     "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,		0,		I2 }, /* tnei */
+{"tne",     "s,I",	0,    (int) M_TNE_I,	INSN_MACRO,		0,		I2 },
+{"trunc.l.d", "D,S",	0x46200009, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3_33 },
+{"trunc.l.s", "D,S",	0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3_33 },
+{"trunc.w.d", "D,S",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2 },
+{"trunc.w.d", "D,S,x",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2 },
+{"trunc.w.d", "D,S,t",	0,    (int) M_TRUNCWD,	INSN_MACRO,		0,		I1 },
+{"trunc.w.s", "D,S",	0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,	0,		I2 },
+{"trunc.w.s", "D,S,x",	0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,	0,		I2 },
+{"trunc.w.s", "D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO,		0,		I1 },
+{"uld",     "t,o(b)",	0,    (int) M_ULD,	INSN_MACRO,		    0,		I3 },
+{"uld",     "t,A(b)",	0,    (int) M_ULD_A,	INSN_MACRO,		0,		I3 },
+{"ulh",     "t,o(b)",	0,    (int) M_ULH,	INSN_MACRO,		    0,		I1 },
+{"ulh",     "t,A(b)",	0,    (int) M_ULH_A,	INSN_MACRO,		0,		I1 },
+{"ulhu",    "t,o(b)",	0,    (int) M_ULHU,	INSN_MACRO,		0,		I1 },
+{"ulhu",    "t,A(b)",	0,    (int) M_ULHU_A,	INSN_MACRO,		0,		I1 },
+{"ulw",     "t,o(b)",	0,    (int) M_ULW,	INSN_MACRO,		0,		I1 },
+{"ulw",     "t,A(b)",	0,    (int) M_ULW_A,	INSN_MACRO,		0,		I1 },
+{"usd",     "t,o(b)",	0,    (int) M_USD,	INSN_MACRO,		0,		I3 },
+{"usd",     "t,A(b)",	0,    (int) M_USD_A,	INSN_MACRO,		0,		I3 },
+{"ush",     "t,o(b)",	0,    (int) M_USH,	INSN_MACRO,		0,		I1 },
+{"ush",     "t,A(b)",	0,    (int) M_USH_A,	INSN_MACRO,		0,		I1 },
+{"usw",     "t,o(b)",	0,    (int) M_USW,	INSN_MACRO,		0,		I1 },
+{"usw",     "t,A(b)",	0,    (int) M_USW_A,	INSN_MACRO,		0,		I1 },
+{"wait",    "",         0x42000020, 0xffffffff, TRAP,   		0,		I3_32 },
+{"wait",    "J",        0x42000020, 0xfe00003f, TRAP,   		0,		I32 },
+{"wrpgpr",  "d,w",	0x41c00000, 0xffe007ff, RD_t,			0,		I33 },
+{"wsbh",    "d,w",	0x7c0000a0, 0xffe007ff, WR_d|RD_t,		0,		I33 },
+{"xor",     "d,v,t",	0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I1 },
+{"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		0,		I1 },
+{"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,		0,		I1 },
+
+/* dbb: modified for supporting radiax instructions */
+/*   d1: m0(3), m1(7), m2(11), m3(15) */
+/*   d2: m0l, m0h, m0 ~ m3l, m3h, m3 */
+/*   d3: m0l, m0h, ~ m3l, m3h */
+/*   d4: LXC0 */
+{"mta2",        "s,#d2",       0x7C00005D, 0xFC1F07ff, RD_s|WRAD_d,      0, RAD1 },
+{"mta2.g",      "s,#d2",       0x7C00015D, 0xFC1F07ff, RD_s|WRAD_d,      0, RAD1 },
+{"mfa",         "d,#t3",       0x7C00001C, 0xFFE007FF, WR_d|RRAD_t,      0, RAD1 },
+{"mfa",         "d,#t3,##",    0x7C00001C, 0xFFE0007F, WR_d|RRAD_t,      0, RAD1 },
+{"mfa2",        "d,#t1",       0x7C00005C, 0xFFE007FF, WR_d|RRAD_t,      0, RAD1 },
+{"mfa2",        "d,#t1,##",    0x7C00005C, 0xFFE0007F, WR_d|RRAD_t,      0, RAD1 },
+{"diva",        "#d1,s,t",     0x7C00001A, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"divau",       "#d1,s,t",     0x7C00021A, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"multa",       "#d1,s,t",     0x7C000112, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"multau",      "#d1,s,t",     0x7C000312, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imulta",      "#d1,s,t",     0x7C000102, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"imultau",     "#d1,s,t",     0x7C000302, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmulta",      "#d1,s,t",     0x7C000502, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"multa2",      "#d2,s,t",     0x7C000152, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imulta2",     "#d2,s,t",     0x7C000142, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmulta2",     "#d2,s,t",     0x7C000542, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"mulna2",      "#d2,s,t",     0x7C000153, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imulna2",     "#d2,s,t",     0x7C000143, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmulna2",     "#d2,s,t",     0x7C000543, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"cmulta",      "#d1,s,t",     0x7C00001B, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"icmulta",     "#d1,s,t",     0x7C00011B, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qcmulta",     "#d1,s,t",     0x7C00051B, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"madda",       "#d1,s,t",     0x7C000012, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"maddau",      "#d1,s,t",     0x7C000212, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imadda",      "#d1,s,t",     0x7C000002, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"imaddau",     "#d1,s,t",     0x7C000202, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmadda",      "#d1,s,t",     0x7C000402, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"madda2",      "#d2,s,t",     0x7C000052, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imadda2",     "#d2,s,t",     0x7C000042, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmadda2",     "#d2,s,t",     0x7C000442, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"madda2.s",    "#d2,s,t",     0x7C0000D2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imadda2.s32", "#d2,s,t",     0x7C0000C2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmadda2.s32", "#d2,s,t",     0x7C0004C2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"imadda2.s40", "#d2,s,t",     0x7C0001C2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmadda2.s40", "#d2,s,t",     0x7C0005C2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"msuba",       "#d1,s,t",     0x7C000013, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"msubau",      "#d1,s,t",     0x7C000213, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imsuba",      "#d1,s,t",     0x7C000003, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"imsubau",     "#d1,s,t",     0x7C000203, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmsuba",      "#d1,s,t",     0x7C000403, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"msuba2",      "#d2,s,t",     0x7C000053, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imsuba2",     "#d2,s,t",     0x7C000043, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmsuba2",     "#d2,s,t",     0x7C000443, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"msuba2.s",    "#d2,s,t",     0x7C0000D3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 },
+{"imsuba2.s32", "#d2,s,t",     0x7C0000C3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmsuba2.s32", "#d2,s,t",     0x7C0004C3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"imsuba2.s40", "#d2,s,t",     0x7C0001C3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"qmsuba2.s40", "#d2,s,t",     0x7C0005C3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 },
+{"addma",       "#d3,#s3,#t3", 0x7C00001E, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD1 },
+{"addma.s",     "#d3,#s3,#t3", 0x7C00009E, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD1 },
+{"addma.s32",   "#d3,#s3,#t3", 0x7C00041E, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD2 },
+{"addma.s40",   "#d3,#s3,#t3", 0x7C00049E, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD2 },
+{"subma",       "#d3,#s3,#t3", 0x7C00001F, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD1 },
+{"subma.s",     "#d3,#s3,#t3", 0x7C00009F, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD1 },
+{"subma.s32",   "#d3,#s3,#t3", 0x7C00041F, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD2 },
+{"subma.s40",   "#d3,#s3,#t3", 0x7C00049F, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD2 },
+{"rnda2",       "#t2",         0x7C000056, 0xFFE0FFFF, WRAD_t,          0, RAD1 },
+{"rnda2",       "#t2,##",      0x7C000056, 0xFFE0F87F, WRAD_t,          0, RAD1 },
+{"lt",          "#`,#@(b)",    0x7C000036, 0xFC00003F, LDD|RD_b|WR_t,   0, RAD1 },
+{"st",          "#`,#@(b)",    0x7C00003E, 0xFC00003F, SM|RD_t|RD_b,    0, RAD1 },
+{"ltp",         "#`,(b)#~",    0x7C0000f2, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"ltp.c0",      "#`,(b)#~",    0x7C000032, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"ltp.c1",      "#`,(b)#~",    0x7C000072, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"ltp.c2",      "#`,(b)#~",    0x7C0000b2, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lwp",         "t,(b)#~",     0x7C0000f3, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lwp.c0",      "t,(b)#~",     0x7C000033, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lwp.c1",      "t,(b)#~",     0x7C000073, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lwp.c2",      "t,(b)#~",     0x7C0000b3, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lhp",         "t,(b)#~",     0x7C0000f1, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lhp.c0",      "t,(b)#~",     0x7C000031, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lhp.c1",      "t,(b)#~",     0x7C000071, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lhp.c2",      "t,(b)#~",     0x7C0000b1, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lhpu",        "t,(b)#~",     0x7C0000f5, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lhpu.c0",     "t,(b)#~",     0x7C000035, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lhpu.c1",     "t,(b)#~",     0x7C000075, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lhpu.c2",     "t,(b)#~",     0x7C0000b5, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lbp",         "t,(b)#~",     0x7C0000f0, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lbp.c0",      "t,(b)#~",     0x7C000030, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lbp.c1",      "t,(b)#~",     0x7C000070, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lbp.c2",      "t,(b)#~",     0x7C0000b0, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lbpu",        "t,(b)#~",     0x7C0000f4, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lbpu.c0",     "t,(b)#~",     0x7C000034, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lbpu.c1",     "t,(b)#~",     0x7C000074, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"lbpu.c2",     "t,(b)#~",     0x7C0000b4, 0xFC0000FF, LDD|WR_t|RD_b,   0, RAD1 },
+{"stp",         "#`,(b)#~",    0x7C0000fa, 0xFC0000FF, WR_t|RD_b,       0, RAD1 },
+{"stp.c0",      "#`,(b)#~",    0x7C00003a, 0xFC0000FF, WR_t|RD_b,       0, RAD1 },
+{"stp.c1",      "#`,(b)#~",    0x7C00007a, 0xFC0000FF, WR_t|RD_b,       0, RAD1 },
+{"stp.c2",      "#`,(b)#~",    0x7C0000ba, 0xFC0000FF, WR_t|RD_b,       0, RAD1 },
+{"swp",         "t,(b)#~",     0x7C0000fb, 0xFC0000FF, WR_t|RD_b,       0, RAD1 },
+{"swp.c0",      "t,(b)#~",     0x7C00003b, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"swp.c1",      "t,(b)#~",     0x7C00007b, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"swp.c2",      "t,(b)#~",     0x7C0000bb, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"shp",         "t,(b)#~",     0x7C0000f9, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"shp.c0",      "t,(b)#~",     0x7C000039, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"shp.c1",      "t,(b)#~",     0x7C000079, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"shp.c2",      "t,(b)#~",     0x7C0000b9, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"sbp",         "t,(b)#~",     0x7C0000f8, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"sbp.c0",      "t,(b)#~",     0x7C000038, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"sbp.c1",      "t,(b)#~",     0x7C000078, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"sbp.c2",      "t,(b)#~",     0x7C0000b8, 0xFC0000FF, WR_t|RD_b,        0, RAD1 },
+{"mtru",        "t,#u",        0x7C000025, 0xFFE007FF, RD_t|WRAD_d,      0, RAD1 },
+{"mfru",        "t,#u",        0x7C000024, 0xFFE007FF, RD_t|WRAD_d,      0, RAD1 },
+{"mtrk",        "t,#k",        0x7C0000A5, 0xFFE007FF, RD_t|WRAD_d,      0, RAD1 },
+{"mfrk",        "t,#k",        0x7C0000A4, 0xFFE007FF, RD_t|WRAD_d,      0, RAD1 },
+{"sllv2",       "d,t,s",       0x7C000044, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"srlv2",       "d,t,s",       0x7C000046, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"srav2",       "d,t,s",       0x7C000047, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"addr",        "d,s,t",       0x7C000021, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"addr.s",      "d,s,t",       0x7C0000A1, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"addr2",       "d,s,t",       0x7C000061, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"addr2.s",     "d,s,t",       0x7C0000E1, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"subr",        "d,s,t",       0x7C000023, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"subr.s",      "d,s,t",       0x7C0000A3, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"subr2",       "d,s,t",       0x7C000063, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"subr2.s",     "d,s,t",       0x7C0000E3, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"sltr2",       "d,s,t",       0x7C00006A, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"min",         "d,s,t",       0x7C000028, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"min2",        "d,s,t",       0x7C000068, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"max",         "d,s,t",       0x7C000029, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"max2",        "d,s,t",       0x7C000069, 0xFC0007FF, RD_t|RD_s|WR_d,   0, RAD1 },
+{"absr",        "d,t",         0x7C00000F, 0xFFE007FF, RD_t|WR_d,        0, RAD1 },
+{"absr.s",      "d,t",         0x7C00008F, 0xFFE007FF, RD_t|WR_d,        0, RAD1 },
+{"absr2",       "d,t",         0x7C00004F, 0xFFE007FF, RD_t|WR_d,        0, RAD1 },
+{"absr2.s",     "d,t",         0x7C0000CF, 0xFFE007FF, RD_t|WR_d,        0, RAD1 },
+{"mux2.hh",     "d,s,t",       0x7C00064D, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"mux2.hl",     "d,s,t",       0x7C00044D, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"mux2.lh",     "d,s,t",       0x7C00024D, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"mux2.ll",     "d,s,t",       0x7C00004D, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"cls",         "d,t",         0x7C00000E, 0xFFE007FF, RD_t|WR_d,        0, RAD1 },
+{"bitrev",      "d,t,s",       0x7c00000c, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"cmveqz",      "d,s,t",       0x7C000001, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"cmveqz.h",    "d,s,t",       0x7C000081, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"cmveqz.l",    "d,s,t",       0x7C000101, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"cmvnez",      "d,s,t",       0x7C000041, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"cmvnez.h",    "d,s,t",       0x7C0000c1, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+{"cmvnez.l",    "d,s,t",       0x7C000141, 0xFC0007FF, RD_s|RD_t|WR_d,   0, RAD1 },
+/* modified for supporting radiax instructions */
+
+{"mflxc0", "t,#d4",    0x40600000, 0xFFE007FF, LCD|WR_t|RD_LXC0, 0,       RUDI },
+{"mflxc0", "t,#d4,#H", 0x40600000, 0xFFE007C0, LCD|WR_t|RD_LXC0, 0,       RT   },
+{"mtlxc0", "t,#d4",    0x40E00000, 0xFFE007FF, COD|RD_t|WR_LXC0|WR_CC, 0, RUDI },
+{"mtlxc0", "t,#d4,#H", 0x40E00000, 0xFFE007C0, COD|RD_t|WR_LXC0|WR_CC, 0, RT   },
+
+/* MAC-DIV instructions */
+{"sleep", "",   0x42000038, 0xffffffff, 0,         0, RALL },
+{"sleep", "1",  0x42000038, 0xfffff83f, 0,         0, RT   },
+{"madh", "s,t", 0xF0000000, 0xFC00FFFF, RD_s|RD_t, 0, RALL },
+{"madl", "s,t", 0xF0000002, 0xFC00FFFF, RD_s|RD_t, 0, RALL },
+{"mazh", "s,t", 0xF0000004, 0xFC00FFFF, RD_s|RD_t, 0, RALL },
+{"mazl", "s,t", 0xF0000006, 0xFC00FFFF, RD_s|RD_t, 0, RALL },
+{"msbh", "s,t", 0xF0000010, 0xFC00FFFF, RD_s|RD_t, 0, RALL },
+{"msbl", "s,t", 0xF0000012, 0xFC00FFFF, RD_s|RD_t, 0, RALL },
+{"mszh", "s,t", 0xF0000014, 0xFC00FFFF, RD_s|RD_t, 0, RALL },
+{"mszl", "s,t", 0xF0000016, 0xFC00FFFF, RD_s|RD_t, 0, RALL },
+{"ltw",  "#`,#-(b)", 0x7800003C, 0xFC00003F, LDD|RD_b|WR_t, 0, INSN_RLX4181 | INSN_RLX4281 },
+
+/* dbb:  modified for supporting 4181 instructions */
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
    disassembler recognizes more specific versions first.  */
-{"c0",      "C",	0x42000000, 0xfe000000,	CP,			0,		I1	},
-{"c1",      "C",	0x46000000, 0xfe000000,	FP_S,			0,		I1	},
-{"c2",      "C",	0x4a000000, 0xfe000000,	CP,			0,		I1	},
-{"c3",      "C",	0x4e000000, 0xfe000000,	CP,			0,		I1	},
-{"cop0",     "C",	0,    (int) M_COP0,	INSN_MACRO,		0,		I1	},
-{"cop1",     "C",	0,    (int) M_COP1,	INSN_MACRO,		INSN2_M_FP_S,	I1	},
-{"cop2",     "C",	0,    (int) M_COP2,	INSN_MACRO,		0,		I1	},
-{"cop3",     "C",	0,    (int) M_COP3,	INSN_MACRO,		0,		I1	}
+{"c0",   "C",	0x42000000, 0xfe000000,	0,			0,		I1 },
+{"c1",   "C",	0x46000000, 0xfe000000,	0,			0,		I1 },
+{"c2",   "C",	0x4a000000, 0xfe000000,	0,			0,		I1 },
+{"c3",   "C",	0x4e000000, 0xfe000000,	0,			0,		I1 },
+{"cop0", "C",	0,    (int) M_COP0,	INSN_MACRO,		0,		I1 },
+{"cop1", "C",	0,    (int) M_COP1,	INSN_MACRO,		0,		I1 },
+{"cop2", "C",	0,    (int) M_COP2,	INSN_MACRO,		0,		I1 },
+{"cop3", "C",	0,    (int) M_COP3,	INSN_MACRO,		0,		I1 },
+/* Lexra opcode extensions. Register mode */
+{"udi0", "d,v,t", 0x00000038,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI },
+{"udi1", "d,v,t", 0x0000003a,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI },
+{"udi2", "d,v,t", 0x0000003b,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI },
+{"udi3", "d,v,t", 0x0000003c,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI },
+{"udi4", "d,v,t", 0x0000003e,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI },
+{"udi5", "d,v,t", 0x0000003f,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI },
+
+/* Lexra opcode extensions. Immediate mode */
+{"udi0i", "t,r,j", 0x60000000, 0xfc000000, WR_t | RD_s, 0, RUDI },
+{"udi1i", "t,r,j", 0x64000000, 0xfc000000, WR_t | RD_s, 0, RUDI },
+{"udi2i", "t,r,j", 0x68000000, 0xfc000000, WR_t | RD_s, 0, RUDI },
+{"udi3i", "t,r,j", 0x6c000000, 0xfc000000, WR_t | RD_s, 0, RUDI },
 };
 
 #define MIPS_NUM_OPCODES \