summaryrefslogtreecommitdiffstats
path: root/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
blob: 711a109697a9534e0ba0fbb9544bb413e998a491 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
/*
 *  Atheros AR71xx PCI host controller driver
 *
 *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/resource.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/pci.h>
#include <linux/pci_regs.h>

#include <asm/mach-ar71xx/ar71xx.h>
#include <asm/mach-ar71xx/pci.h>

#undef DEBUG
#ifdef DEBUG
#define DBG(fmt, args...)	printk(KERN_DEBUG fmt, ## args)
#else
#define DBG(fmt, args...)
#endif

#define AR71XX_PCI_DELAY	100 /* msecs */

#if 0
#define PCI_IDSEL_BASE	PCI_IDSEL_ADL_START
#else
#define PCI_IDSEL_BASE	0
#endif

static void __iomem *ar71xx_pcicfg_base;
static DEFINE_SPINLOCK(ar71xx_pci_lock);

static inline void ar71xx_pci_delay(void)
{
	mdelay(AR71XX_PCI_DELAY);
}

static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
{
	return __raw_readl(ar71xx_pcicfg_base + reg);
}

static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
{
	__raw_writel(val, ar71xx_pcicfg_base + reg);
}

/* Byte lane enable bits */
static u8 ble_table[4][4] = {
	{0x0, 0xf, 0xf, 0xf},
	{0xe, 0xd, 0xb, 0x7},
	{0xc, 0xf, 0x3, 0xf},
	{0xf, 0xf, 0xf, 0xf},
};

static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{
	u32 t;

	t = ble_table[size & 3][where & 3];
	BUG_ON(t == 0xf);
	t <<= (local) ? 20 : 4;
	return t;
}

static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
					int where)
{
	u32 ret;

	if (!bus->number) {
		/* type 0 */
		ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
		    | (PCI_FUNC(devfn) << 8) | (where & ~3);
	} else {
		/* type 1 */
		ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
		    | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
	}

	return ret;
}

int ar71xx_pci_be_handler(int is_fixup)
{
	u32 pci_err;
	u32 ahb_err;

	pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
	if (pci_err) {
		if (!is_fixup)
			printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
				pci_err,
				ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));

		ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
	}

	ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
	if (ahb_err) {
		if (!is_fixup)
			printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
				ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));

		ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
	}

	return ((ahb_err | pci_err) ? 1 : 0);
}

static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 cmd)
{
	u32 addr;

	addr = ar71xx_pci_bus_addr(bus, devfn, where);

	DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
		bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
		where, size, addr);

	ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
	ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
			cmd | ar71xx_pci_get_ble(where, size, 0));

	return ar71xx_pci_be_handler(1);
}

static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
				  int where, int size, u32 *value)
{
	static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
	unsigned long flags;
	u32 data;
	int ret;

	ret = PCIBIOS_SUCCESSFUL;

	DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
			PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);

	spin_lock_irqsave(&ar71xx_pci_lock, flags);

	if (bus->number == 0 && devfn == 0) {
		u32 t;

		t = PCI_CRP_CMD_READ | (where & ~3);

		ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
		data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);

		DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);

	} else {
		int err;

		err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
						PCI_CFG_CMD_READ);

		if (err == 0) {
			data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
		} else {
			ret = PCIBIOS_DEVICE_NOT_FOUND;
			data = ~0;
		}
	}

	spin_unlock_irqrestore(&ar71xx_pci_lock, flags);

	DBG("PCI: read config: data=%08x raw=%08x\n",
		(data >> (8 * (where & 3))) & mask[size & 7], data);

	*value = (data >> (8 * (where & 3))) & mask[size & 7];

	return ret;
}

static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
				   int where, int size, u32 value)
{
	unsigned long flags;
	int ret;

	DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
		bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
		where, size, value);

	value = value << (8 * (where & 3));
	ret = PCIBIOS_SUCCESSFUL;

	spin_lock_irqsave(&ar71xx_pci_lock, flags);
	if (bus->number == 0 && devfn == 0) {
		u32 t;

		t = PCI_CRP_CMD_WRITE | (where & ~3);
		t |= ar71xx_pci_get_ble(where, size, 1);

		DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);

		ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
		ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
	} else {
		int err;

		err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
						PCI_CFG_CMD_WRITE);

		if (err == 0)
			ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
		else
			ret = PCIBIOS_DEVICE_NOT_FOUND;
	}
	spin_unlock_irqrestore(&ar71xx_pci_lock, flags);

	return ret;
}

static void ar71xx_pci_fixup(struct pci_dev *dev)
{
	u32 t;

	if (dev->bus->number != 0 || dev->devfn != 0)
		return;

	DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
		dev->vendor, dev->device);

	/* setup COMMAND register */
	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;

	pci_write_config_word(dev, PCI_COMMAND, t);
}
DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);

int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
				  uint8_t pin)
{
	int irq = -1;
	int i;

	slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;

	for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
		struct ar71xx_pci_irq *entry;

		entry = &ar71xx_pci_irq_map[i];
		if (entry->slot == slot && entry->pin == pin) {
			irq = entry->irq;
			break;
		}
	}

	if (irq < 0) {
		printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
				pin, pci_name((struct pci_dev *)dev));
	} else {
		printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
				irq, pin, pci_name((struct pci_dev *)dev));
	}

	return irq;
}

static struct pci_ops ar71xx_pci_ops = {
	.read	= ar71xx_pci_read_config,
	.write	= ar71xx_pci_write_config,
};

static struct resource ar71xx_pci_io_resource = {
	.name		= "PCI IO space",
	.start		= 0,
	.end		= 0,
	.flags		= IORESOURCE_IO,
};

static struct resource ar71xx_pci_mem_resource = {
	.name		= "PCI memory space",
	.start		= AR71XX_PCI_MEM_BASE,
	.end		= AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
	.flags		= IORESOURCE_MEM
};

static struct pci_controller ar71xx_pci_controller = {
	.pci_ops	= &ar71xx_pci_ops,
	.mem_resource	= &ar71xx_pci_mem_resource,
	.io_resource	= &ar71xx_pci_io_resource,
};

int __init ar71xx_pcibios_init(void)
{
	ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
	ar71xx_pci_delay();

	ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
	ar71xx_pci_delay();

	ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
						AR71XX_PCI_CFG_SIZE);

	ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
	ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
	ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
	ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
	ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
	ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
	ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
	ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);

	ar71xx_pci_delay();

	/* clear bus errors */
	(void)ar71xx_pci_be_handler(1);

	register_pci_controller(&ar71xx_pci_controller);

	return 0;
}