| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ar71xx: introduce global ar724x_pci_ctrl_base variable | juhosg | 2010-03-18 | 1 | -20/+14 |
| * | ar71xx: add error handling to ar724x_pcibios_init | juhosg | 2010-03-18 | 1 | -2/+13 |
| * | ar71xx: move ar724x_pci_* helpers to ar724x-pci.c | juhosg | 2010-03-18 | 1 | -0/+30 |
| * | ar71xx: move PCI intterupt handling code to pci-ar7{1xx,24x}.c | juhosg | 2010-03-18 | 2 | -1/+149 |
| * | ar71xx: update AR7240 PCI code | juhosg | 2009-12-20 | 1 | -13/+57 |
| * | ar71xx: add PCI Host Controller fixup for ar724x | juhosg | 2009-10-01 | 1 | -0/+23 |
| * | ar71xx: use ar71xx_pci_fixup on ar71xx SoCs only | juhosg | 2009-10-01 | 1 | -0/+5 |
| * | ar71xx: fix a typo in the ar724x PCI code | juhosg | 2009-10-01 | 1 | -1/+1 |
| * | [ar71xx] add AR7240 specific PCI code | juhosg | 2009-07-05 | 1 | -0/+201 |
| * | [ar71xx] reorganize PCI code | juhosg | 2009-07-05 | 1 | -27/+7 |
| * | [ar71xx] rename DDR registers | juhosg | 2008-11-26 | 1 | -8/+8 |
| * | [ar71xx] fix the PCI byte lane enable generation code, based on a patch by Ch... | juhosg | 2008-09-17 | 1 | -5/+6 |
| * | surprise :p | juhosg | 2008-07-21 | 1 | -0/+346 |
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index : rtl819xx | |
| Realtek rtl819xx port to OpenWrt | Roman |
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