diff options
Diffstat (limited to 'target/linux/realtek/files/drivers/net/wireless/rtl8192cd/8192d_hw.c')
| -rw-r--r-- | target/linux/realtek/files/drivers/net/wireless/rtl8192cd/8192d_hw.c | 816 |
1 files changed, 5 insertions, 811 deletions
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/8192d_hw.c b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/8192d_hw.c index 11d448ffc..eb1bde12b 100644 --- a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/8192d_hw.c +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/8192d_hw.c @@ -22,15 +22,13 @@ #include <bsp/bspchip.h>
#endif
-#ifndef REG32
- #define REG32(reg) (*(volatile unsigned int *)(reg))
-#endif
-
+#if defined(CONFIG_RTL865X_WTDOG) || defined(CONFIG_RTL_WTDOG)
#ifdef CONFIG_NET_PCI
#ifndef CONFIG_RTL_8198B
#define BSP_WDTCNR 0xB800311C
#endif
#endif
+#endif
#ifndef USE_OUT_SRC
#define IQK_ADDA_REG_NUM 16
@@ -190,8 +188,7 @@ void SetSYN_para(struct rtl8192cd_priv *priv, unsigned char channel) idx = 0;
else
idx = 1;
- }
- else if (channel==149 || channel==155 || channel==161)
+ } else if (channel == 149 || channel == 155 || channel == 161)
idx = 2;
else if (channel==151 || channel==153 || channel==163 || channel==165)
idx = 3;
@@ -505,11 +502,13 @@ int Load_92D_Firmware(struct rtl8192cd_priv *priv) }
}
+#if defined(CONFIG_RTL865X_WTDOG) || defined(CONFIG_RTL_WTDOG)
#if defined(CONFIG_RTL_8198) || defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E)
REG32(BSP_WDTCNR) |= 1 << 23;
#elif defined(CONFIG_RTL_8198B)
REG32(BSP_WDTCNTRR) |= BSP_WDT_KICK;
#endif
+#endif
RTL_W8(TCR+3, 0x7f);
RTL_W8(MCUFWDL, (RTL_R8(MCUFWDL) & 0xfe) | MCUFWDL_RDY);
@@ -881,811 +880,6 @@ void clnt_92D_2T_AGSwitch(struct rtl8192cd_priv * priv, int target) #endif
-
-
-#ifdef SMART_CONCURRENT_92D
-/*
- * mode - 0: 2x2A0->1x1A0G1 (w. IQK)
- * 1: 2x2G1->1x1A0G1 (w/o IQK)
- */
-int smcc_92D_enable1x1_5G(struct rtl8192cd_priv * priv, int mode)
-{
- unsigned int flags, i;
- //int rtStatus = 0;
- unsigned char temp_0522, temp_0550, temp_0551, temp_0800;
- unsigned char temp_1522, temp_1550, temp_1551;
- struct rtl8192cd_priv * priv0=(struct rtl8192cd_priv *)if_priv[0];
- unsigned char reg;
- reg = MAC_PHY_CTRL_MP;
-
- SAVE_INT_AND_CLI(flags);
-
- printk("%s\n",__FUNCTION__);
- priv0->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY;
- if (mode==1){
- priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY;
- }
- priv0->pmib->dot11RFEntry.phyBandSelect = PHY_BAND_5G;
- priv0->pshare->phw->MIMO_TR_hw_support = MIMO_1T1R;
-
- /*
- * Save MAC default value
- */
- temp_0522 = DMDP_RTL_R8(0, 0x522);
- temp_0550 = DMDP_RTL_R8(0, 0x550);
- temp_0551 = DMDP_RTL_R8(0, 0x551);
- if (mode==1){
- temp_1522 = DMDP_RTL_R8(1, 0x522);
- temp_1550 = DMDP_RTL_R8(1, 0x550);
- temp_1551 = DMDP_RTL_R8(1, 0x551);
- }
-
- /*
- * MAC register setting
- */
- DMDP_RTL_W8(0, 0x522, 0x3f);
- DMDP_RTL_W8(0, 0x550, temp_0550& (~BIT(3)));
- DMDP_RTL_W8(0, 0x551, temp_0551& (~BIT(3)));
- if (mode==1){
- DMDP_RTL_W8(1, 0x522, 0x3f);
- DMDP_RTL_W8(1, 0x550, temp_1550& (~BIT(3)));
- DMDP_RTL_W8(1, 0x551, temp_1551& (~BIT(3)));
- }
-
- // Set Dual-PHY mode
- DMDP_RTL_W8(0, reg, RTL_R8(reg) | BIT(1));
-
- // stop BB
- DMDP_PHY_SetBBReg(0, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
- if (mode==1){
- DMDP_PHY_SetBBReg(1, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
- //temp_0800 = DMDP_PHY_QueryBBReg(0, rFPGA0_RFMOD, 0x0f000000);
- //DMDP_PHY_SetBBReg(0, rFPGA0_RFMOD, 0x0f000000, 0);
- }
-
- // Set as 1R
- DMDP_PHY_SetBBReg(0, 0xc04, bMaskByte0, 0x11);
- DMDP_PHY_SetBBReg(0, 0xd04, 0xf, 0x1);
- // Set ad/da clock 1
- DMDP_PHY_SetBBReg(0, 0x888, BIT(13)|BIT(12), 3);
- // Set RF as 1T1R mode
- if (mode==0){
- DMDP_PHY_SetBBReg(0, 0xc80, bMaskDWord, 0x20000080);
- DMDP_PHY_SetBBReg(0, 0xc94, 0xf0000000, 0);
- DMDP_PHY_SetBBReg(0, 0xc4c, bMaskByte3, 0);
- DMDP_PHY_SetBBReg(0, 0xc14, bMaskDWord, 0x40000100);
- DMDP_PHY_SetBBReg(0, 0xca0, 0xf0000000, 0);
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x08, bMask20Bits, 0x84000);
- // IQK
-#ifdef DFS
- if (!((priv->pshare->rf_ft_var.dfsdelayiqk) &&
- (OPMODE & WIFI_AP_STATE) &&
- !priv->pmib->dot11DFSEntry.disable_DFS &&
- (timer_pending(&priv->ch_avail_chk_timer) ||
- priv->pmib->dot11DFSEntry.disable_tx)))
-#endif
-
- IQK_92D_5G_phy0_n(priv);
-
- }else{
- // 5G_PAPE Select & extenal PA power on
- DMDP_PHY_SetBBReg(0, 0x878, BIT(0), 1);
- DMDP_PHY_SetBBReg(0, 0x878, BIT(15), 1);
- DMDP_PHY_SetBBReg(0, 0x878, BIT(16), 1);
-
- // RSSI Table Select
- DMDP_PHY_SetBBReg(0, 0xc78, BIT(7)|BIT(6), 1);
- // fc_area
- DMDP_PHY_SetBBReg(0, 0xd2c, BIT(14)|BIT(13), (priv0->MAC_info->bb_reg[17]>>13)&0x03);
- // cck_enable
- DMDP_PHY_SetBBReg(1, rFPGA0_RFMOD, bCCKEn, 1);
- DMDP_PHY_SetBBReg(0, rFPGA0_RFMOD, bCCKEn, 0);
- // 5G LNA_On
- DMDP_PHY_SetBBReg(0, 0xb30, 0x00f00000, 0);
- // LDO_DIV
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x28, BIT(7)|BIT(6), 1);
- // MOD_AG // Set channel number
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x18, bMask20Bits, priv0->MAC_info->rfA_reg[1]);
- // CLOAD for path_A
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0xB, bMask20Bits, priv0->MAC_info->rfA_reg[0]);
-
- // IMR
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x00, bMask20Bits, 0x70000);
- for (i=0;i<11;i++) {
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, (0x2f+i), bMask20Bits, priv0->MAC_info->imr[i]);
- }
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x00, bMask20Bits, priv0->MAC_info->imr[i]);
- // Enable BB
- //DMDP_PHY_SetBBReg(0, rFPGA0_RFMOD, 0x0f000000, temp_0800);
-
- // IQC Setting
- DMDP_PHY_SetBBReg(0, 0xc80, bMaskDWord, priv0->MAC_info->diqc_c80_b31b0);
- DMDP_PHY_SetBBReg(0, 0xc94, bMaskByte3, priv0->MAC_info->diqc_c94_b31b24);
- DMDP_PHY_SetBBReg(0, 0xc4c, 0xf0000000, priv0->MAC_info->diqc_c4c_b31b28);
- DMDP_PHY_SetBBReg(0, 0xc14, bMaskDWord, priv0->MAC_info->diqc_c14_b31b0);
- DMDP_PHY_SetBBReg(0, 0xca0, bMaskByte3, priv0->MAC_info->diqc_ca0_b31b24);
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x08, bMask20Bits, priv0->MAC_info->loft_0A);
- //Set related registers for BW config
- DMDP_PHY_SetBBReg(0, 0x800, BIT(0), priv0->MAC_info->bb_reg[0]& BIT(0));
- DMDP_PHY_SetBBReg(0, 0x900, BIT(0), priv0->MAC_info->bb_reg[6]& BIT(0));
- DMDP_PHY_SetBBReg(0, 0xa00, BIT(4), (priv0->MAC_info->bb_reg[7]& BIT(4))>>4);
- DMDP_PHY_SetBBReg(0, 0xd00, BIT(11)|BIT(10), (priv0->MAC_info->bb_reg[15]&(BIT(11)|BIT(10)))>>10);
- DMDP_PHY_SetBBReg(0, 0x818, BIT(27)|BIT(26), (priv0->MAC_info->bb_reg[1]&(BIT(27)|BIT(26)))>>26);
- DMDP_PHY_SetBBReg(0, 0x884, BIT(11) | BIT(10), (priv0->MAC_info->bb_reg[3]&(BIT(11) | BIT(10)))>>10);
- }
-
-
- if (mode==1){
- priv0->pmib->dot11RFEntry.macPhyMode = DUALMAC_SINGLEPHY;
- priv0->pshare->phw->MIMO_TR_hw_support = MIMO_2T2R;
- priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_SINGLEPHY;
- priv->pshare->phw->MIMO_TR_hw_support = MIMO_2T2R;
- }
-
- DMDP_PHY_SetBBReg(0, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
- if (mode==1){
- DMDP_PHY_SetBBReg(1, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
- }
-
- /*
- * Reload MAC default value
- */
- DMDP_RTL_W8(0, 0x550, temp_0550);
- DMDP_RTL_W8(0, 0x551, temp_0551);
- DMDP_RTL_W8(0, 0x522, temp_0522);
- if (mode==1){
- DMDP_RTL_W8(1, 0x550, temp_1550);
- DMDP_RTL_W8(1, 0x551, temp_1551);
- DMDP_RTL_W8(1, 0x522, temp_1522);
- }
-
- RESTORE_INT(flags);
- return 0;
-}
-
-
-int smcc_92D_enable2x2_2G(struct rtl8192cd_priv * priv)
-{
- unsigned int flags, i;
- int rtStatus = 0;
- unsigned char temp_0522, temp_0550, temp_0551, temp_0800;
- unsigned char temp_1522, temp_1550, temp_1551, temp_1800;
- unsigned char reg;
- struct rtl8192cd_priv * priv0=(struct rtl8192cd_priv *)if_priv[0];
- reg = MAC_PHY_CTRL_MP;
-
- SAVE_INT_AND_CLI(flags);
-
- printk("%s\n",__FUNCTION__);
- priv0->pmib->dot11RFEntry.macPhyMode = DUALMAC_SINGLEPHY;
- priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_SINGLEPHY;
- priv0->pmib->dot11RFEntry.phyBandSelect = PHY_BAND_2G;
-
- /*
- * Save MAC default value
- */
- temp_0522 = DMDP_RTL_R8(0, 0x522);
- temp_0550 = DMDP_RTL_R8(0, 0x550);
- temp_0551 = DMDP_RTL_R8(0, 0x551);
- temp_1522 = DMDP_RTL_R8(1, 0x522);
- temp_1550 = DMDP_RTL_R8(1, 0x550);
- temp_1551 = DMDP_RTL_R8(1, 0x551);
-
- /*
- * MAC register setting
- */
- DMDP_RTL_W8(0, 0x522, 0x3f);
- DMDP_RTL_W8(0, 0x550, temp_0550& (~BIT(3)));
- DMDP_RTL_W8(0, 0x551, temp_0551& (~BIT(3)));
- DMDP_RTL_W8(1, 0x522, 0x3f);
- DMDP_RTL_W8(1, 0x550, temp_1550& (~BIT(3)));
- DMDP_RTL_W8(1, 0x551, temp_1551& (~BIT(3)));
-
- // stop BB
- DMDP_PHY_SetBBReg(0, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
- DMDP_PHY_SetBBReg(1, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
- //temp_0800 = DMDP_PHY_QueryBBReg(0, rFPGA0_RFMOD, 0x0f000000);
- //DMDP_PHY_SetBBReg(0, rFPGA0_RFMOD, 0x0f000000, 0);
- //temp_1800 = DMDP_PHY_QueryBBReg(1, rFPGA0_RFMOD, 0x0f000000);
- //DMDP_PHY_SetBBReg(1, rFPGA0_RFMOD, 0x0f000000, 0);
-
- // Set Single-PHY mode
- DMDP_RTL_W8(0, reg, RTL_R8(reg) & (~BIT(1)));
- // Set as 2R
- DMDP_PHY_SetBBReg(0, 0xc04, bMaskByte0, 0x33);
- DMDP_PHY_SetBBReg(0, 0xd04, 0xf, 0x3);
- // Set ad/da clock 1
- DMDP_PHY_SetBBReg(0, 0x888, BIT(13)|BIT(12), 0);
- // 5G_PAPE Select & external PA power on
- DMDP_PHY_SetBBReg(0, 0x878, BIT(0), 0);
- DMDP_PHY_SetBBReg(0, 0x878, BIT(15), 0);
- DMDP_PHY_SetBBReg(0, 0x878, BIT(16), 0);
- DMDP_PHY_SetBBReg(0, 0x878, BIT(31), 0);
- // RSSI Table Select
- DMDP_PHY_SetBBReg(0, 0xc78, BIT(7)|BIT(6), 0);
- // fc_area
- DMDP_PHY_SetBBReg(0, 0xd2c, BIT(14)|BIT(13), 0);
- // cck_enable
- DMDP_PHY_SetBBReg(1, rFPGA0_RFMOD, bCCKEn, 0);
- DMDP_PHY_SetBBReg(0, rFPGA0_RFMOD, bCCKEn, 1);
- // 5G LNA_On
- DMDP_PHY_SetBBReg(0, 0xb30, 0x00f00000, 0xa);
- // LDO_DIV
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x28, BIT(7)|BIT(6), 0);
- // MOD_AG // Set channel number
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x18, bMask20Bits, priv->MAC_info->rfA_reg[1]);
- // CLOAD for path_A
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0xB, BIT(16)|BIT(15)|BIT(14), 0x7);
-
- // IMR
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x00, bMask20Bits, 0x70000);
- for (i=0;i<11;i++) {
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, (0x2f+i), bMask20Bits, priv->MAC_info->imr[i]);
- }
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x00, bMask20Bits, priv->MAC_info->imr[i]);
-
- // Enable BB
- //DMDP_PHY_SetBBReg(0, rFPGA0_RFMOD, 0x0f000000, temp_0800);
- //DMDP_PHY_SetBBReg(1, rFPGA0_RFMOD, 0x0f000000, temp_1800);
- // IQK
- DMDP_PHY_SetBBReg(0, 0xc80, bMaskDWord, 0x40000100);
- DMDP_PHY_SetBBReg(0, 0xc94, bMaskByte3, 0);
- DMDP_PHY_SetBBReg(0, 0xc4c, bMaskByte3, 0);
- DMDP_PHY_SetBBReg(0, 0xc88, bMaskDWord, 0x40000100);
- DMDP_PHY_SetBBReg(0, 0xc9c, bMaskByte3, 0);
- DMDP_PHY_SetBBReg(0, 0xc14, bMaskDWord, 0x40000100);
- DMDP_PHY_SetBBReg(0, 0xca0, bMaskByte3, 0);
- DMDP_PHY_SetBBReg(0, 0xc1c, bMaskDWord, 0x40000100);
- DMDP_PHY_SetBBReg(0, 0xc78, bMaskByte1, 0);
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x08, bMask20Bits, 0x84000);
- IQK_92D_2G(priv0);
- //Set related registers for BW config
- DMDP_PHY_SetBBReg(0, 0x800, BIT(0), priv->MAC_info->bb_reg[0]& BIT(0));
- DMDP_PHY_SetBBReg(0, 0x900, BIT(0), priv->MAC_info->bb_reg[6]& BIT(0));
- DMDP_PHY_SetBBReg(0, 0xa00, BIT(4), (priv->MAC_info->bb_reg[7]& BIT(4))>>4);
- DMDP_PHY_SetBBReg(0, 0xd00, BIT(11)|BIT(10), (priv->MAC_info->bb_reg[15]&(BIT(11)|BIT(10)))>>10);
- DMDP_PHY_SetBBReg(0, 0x818, BIT(27)|BIT(26), (priv->MAC_info->bb_reg[1]&(BIT(27)|BIT(26)))>>26);
- DMDP_PHY_SetBBReg(0, 0x884, BIT(11) | BIT(10), (priv->MAC_info->bb_reg[3]&(BIT(11) | BIT(10)))>>10);
-
- DMDP_PHY_SetBBReg(0, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
- DMDP_PHY_SetBBReg(1, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
-
- /*
- * Reload MAC default value
- */
- DMDP_RTL_W8(0, 0x550, temp_0550);
- DMDP_RTL_W8(0, 0x551, temp_0551);
- DMDP_RTL_W8(0, 0x522, temp_0522);
- DMDP_RTL_W8(1, 0x550, temp_1550);
- DMDP_RTL_W8(1, 0x551, temp_1551);
- DMDP_RTL_W8(1, 0x522, temp_1522);
-
- RESTORE_INT(flags);
- return 0;
-}
-
-#if 0
-int smcc_92D_enable2x2_5G(struct rtl8192cd_priv * priv)
-{
- unsigned int flags, val=0;
- //int rtStatus = 0;
- unsigned char temp_522, temp_550, temp_551;
- unsigned char reg;
- reg = MAC_PHY_CTRL_MP;
-
- SAVE_INT_AND_CLI(flags);
- priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_SINGLEPHY;
- priv->pshare->phw->MIMO_TR_hw_support = MIMO_2T2R;
-
- /*
- * Save MAC default value
- */
- temp_522 = RTL_R8(0x522);
- temp_550 = RTL_R8(0x550);
- temp_551 = RTL_R8(0x551);
-
- /*
- * MAC register setting
- */
- RTL_W8(0x522, 0x3f);
- RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3)));
- RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3)));
-
- // stop BB
- PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
-
- // Set Single-PHY mode
- RTL_W8(reg, RTL_R8(reg) & (~BIT(1)));
- // Set as 2R
- PHY_SetBBReg(priv, 0xc04, bMaskByte0, 0x33);
- PHY_SetBBReg(priv, 0xd04, 0xf, 0x3);
- // Set ad/da clock 1
- PHY_SetBBReg(priv, 0x888, BIT(13)|BIT(12), 0);
- // Set RF as 2T2R mode
- PHY_SetRFReg(priv, RF92CD_PATH_A, 0x38, BIT(12), 1);
- // Reload AGC table
- /*
- rtStatus = PHY_ConfigBBWithParaFile(priv, AGCTAB);
- if (rtStatus) {
- printk("phy_BB8192CD_Config_ParaFile(): Write BB AGC Table Fail!!\n");
- RESTORE_INT(flags);
- return -1;
- }
- */
- // 5G_PAPE Select & external PA power on
- PHY_SetBBReg(priv, 0x878, BIT(15), 1);
- PHY_SetBBReg(priv, 0x878, BIT(31), 1);
- // 1.5V_LDO
- RTL_W32(0x14, ((RTL_R32(0x14)&0xff0fffff)|0x00d00000));
- // LDO_DIV
- PHY_SetRFReg(priv, RF92CD_PATH_B, 0x28, BIT(7)|BIT(6), 1);
- // A/G mode LO buffer
- PHY_SetRFReg(priv, RF92CD_PATH_B, 0x38, BIT(16)|BIT(15)|BIT(14), 3);
- // MOD_AG
- // Set channel number
- val = PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x18, bMask20Bits, 1);
- PHY_SetRFReg(priv, RF92CD_PATH_B, 0x18, bMask20Bits, val);
- // IMR parameter for path_A/B
- SetIMR(priv, priv->pmib->dot11RFEntry.dot11channel);
- PHY_SetBBReg(priv, 0xc80, bMaskDWord, 0x20000080);
- PHY_SetBBReg(priv, 0xc94, 0xf0000000, 0);
- PHY_SetBBReg(priv, 0xc4c, bMaskByte3, 0);
- PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100);
- PHY_SetBBReg(priv, 0xca0, 0xf0000000, 0);
- PHY_SetBBReg(priv, 0xc88, bMaskDWord, 0x20000080);
- PHY_SetBBReg(priv, 0xc9c, 0xf0000000, 0);
- PHY_SetBBReg(priv, 0xc1c, bMaskDWord, 0x40000100);
- PHY_SetBBReg(priv, 0xc78, 0x0000f000, 0);
- PHY_SetBBReg(priv, 0xc78, BIT(7)|BIT(6), 1);
- PHY_SetRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 0x84000);
- PHY_SetRFReg(priv, RF92CD_PATH_B, 0x08, bMask20Bits, 0x84000);
-
- // IQK
- IQK_92D_5G_n(priv);
- //Set related registers for BW config
- SwBWMode(priv, priv->pshare->CurrentChannelBW, priv->pshare->offset_2nd_chan);
-
- // Enable BB
- PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
-
- /*
- * Reload MAC default value
- */
- RTL_W8(0x550, temp_550);
- RTL_W8(0x551, temp_551);
- RTL_W8(0x522, temp_522);
-
- RESTORE_INT(flags);
- return 0;
-}
-
-int smcc_92D_enable2x2_2G(struct rtl8192cd_priv * priv)
-{
- unsigned int flags;
- int rtStatus = 0;
- unsigned char temp_522, temp_550, temp_551;
- unsigned char reg;
- reg = MAC_PHY_CTRL_MP;
-
- SAVE_INT_AND_CLI(flags);
- priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_SINGLEPHY;
-
- /*
- * Save MAC default value
- */
- temp_522 = RTL_R8(0x522);
- temp_550 = RTL_R8(0x550);
- temp_551 = RTL_R8(0x551);
-
- /*
- * MAC register setting
- */
- RTL_W8(0x522, 0x3f);
- RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3)));
- RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3)));
-
- // stop BB
- PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
-
- // Set Single-PHY mode
- RTL_W8(reg, RTL_R8(reg) & (~BIT(1)));
- // Set as 2R
- PHY_SetBBReg(priv, 0xc04, bMaskByte0, 0x33);
- PHY_SetBBReg(priv, 0xd04, 0xf, 0x3);
- // Set ad/da clock 1
- PHY_SetBBReg(priv, 0x888, BIT(13)|BIT(12), 0);
- // Set RF as 2T2R mode
- PHY_SetRFReg(priv, RF92CD_PATH_A, 0x38, BIT(12), 1);
- // Reload AGC table
- rtStatus = PHY_ConfigBBWithParaFile(priv, AGCTAB);
- if (rtStatus) {
- printk("phy_BB8192CD_Config_ParaFile(): Write BB AGC Table Fail!!\n");
- RESTORE_INT(flags);
- return -1;
- }
- // 5G_PAPE Select & external PA power on
- PHY_SetBBReg(priv, 0x878, BIT(0), 0);
- PHY_SetBBReg(priv, 0x878, BIT(15), 0);
- PHY_SetBBReg(priv, 0x878, BIT(16), 0);
- PHY_SetBBReg(priv, 0x878, BIT(31), 0);
- // RSSI Table Select
- PHY_SetBBReg(priv, 0xc78, BIT(7)|BIT(6), 0);
- // fc_area
- PHY_SetBBReg(priv, 0xd2c, BIT(14)|BIT(13), 0);
- // cck_enable
- PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x1);;
- //AGC trsw threshold
- PHY_SetBBReg(priv, 0xc70, 0x007F0000, 0x7f);
- // 1.5V_LDO
- RTL_W32(0x14, ((RTL_R32(0x14)&0xff0fffff)|0x00700000));
- // LDO_DIV
- PHY_SetRFReg(priv, RF92CD_PATH_B, 0x28, BIT(7)|BIT(6), 1);
- // A/G mode LO buffer
- PHY_SetRFReg(priv, RF92CD_PATH_B, 0x38, BIT(16)|BIT(15)|BIT(14), 4);
- // MOD_AG
- // Set channel number
- SwBWMode(priv, priv->pshare->CurrentChannelBW, priv->pshare->offset_2nd_chan);
- SwChnl(priv, priv->pmib->dot11RFEntry.dot11channel, priv->pshare->offset_2nd_chan);
- // IQK
- IQK_92D_2G(priv);
- //Set related registers for BW config
-
-
- // Enable BB
- PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
-
- /*
- * Reload MAC default value
- */
- RTL_W8(0x550, temp_550);
- RTL_W8(0x551, temp_551);
- RTL_W8(0x522, temp_522);
-
- RESTORE_INT(flags);
- return 0;
-}
-
-int smcc_92D_enable1x1_2G(struct rtl8192cd_priv * priv)
-{
- struct rtl8192cd_priv *priv_phy0 = (struct rtl8192cd_priv *)if_priv[0];
- unsigned int flags;
- int rtStatus = 0;
- unsigned char temp_522, temp_550, temp_551;
- int i;
- unsigned char reg;
- reg = MAC_PHY_CTRL_MP;
-
- SAVE_INT_AND_CLI(flags);
- printk("%s %d %x\n",__FUNCTION__, __LINE__, PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x18, bMask20Bits,1));
- priv->pmib->dot11RFEntry.macPhyMode = DUALMAC_DUALPHY;
- priv->pshare->phw->MIMO_TR_hw_support = MIMO_1T1R;
-
- /*
- * Save MAC default value
- */
- temp_522 = RTL_R8(0x522);
- temp_550 = RTL_R8(0x550);
- temp_551 = RTL_R8(0x551);
-
- /*
- * MAC register setting
- */
- RTL_W8(0x522, 0x3f);
- RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3)));
- RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3)));
-
- // stop BB
- PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
-
- // Set Dual-PHY mode
- RTL_W8(reg, RTL_R8(reg) | BIT(1));
- // Set as 1R
- DMDP_PHY_SetBBReg(0, 0xc04, bMaskByte0, 0x11);
- DMDP_PHY_SetBBReg(0, 0xd04, 0xf, 0x1);
- // Set ad/da clock 1
- DMDP_PHY_SetBBReg(0, 0x888, BIT(13)|BIT(12), 3);
- // Set RF as 2T2R mode
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x38, BIT(12), 0);
- // Reload AGC table
- rtStatus = PHY_ConfigBBWithParaFile(priv_phy0, AGCTAB);
- if (rtStatus) {
- printk("phy_BB8192CD_Config_ParaFile(): Write BB AGC Table Fail!!\n");
- RESTORE_INT(flags);
- return -1;
- }
- // 5G_PAPE Select & extenal PA power on
- DMDP_PHY_SetBBReg(0, 0x878, BIT(0), 1);
- DMDP_PHY_SetBBReg(0, 0x878, BIT(15), 1);
- // RSSI Table Select
- DMDP_PHY_SetBBReg(0, 0xc78, BIT(7)|BIT(6), 1);
- // fc_area
- DMDP_PHY_SetBBReg(0, 0xd2c, BIT(14)|BIT(13), 1);
- // cck_enable
- DMDP_PHY_SetBBReg(0, rFPGA0_RFMOD, bCCKEn, 0);
- // AGC trsw threshold
- DMDP_PHY_SetBBReg(0, 0xc70, 0x007F0000, 0x4e);
- // 1.5V_LDO
- DMDP_RTL_W32(0, 0x14, (DMDP_RTL_R32(0, 0x14)&0xff0fffff)|0x00d00000);
- // LDO_DIV
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x28, BIT(7)|BIT(6), 1);
- PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, BIT(7)|BIT(6), 0);
- // A/G mode LO buffer
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x38, BIT(16)|BIT(15)|BIT(14), 3);
- PHY_SetRFReg(priv, RF92CD_PATH_A, 0x38, BIT(16)|BIT(15)|BIT(14), 4);
- // PHY0 MOD_AG //Set channel number
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, rRfChannel, bMask20Bits, priv_phy0->MAC_info->rfA_reg[0]);
- // PHY1 MOD_AG //Set channel number
- // PHY_SetRFReg(priv, RF92CD_PATH_A, rRfChannel, bMask20Bits, priv->MAC_info->rfA_reg[0]);
- // PHY0 IMR Path A
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x00, bMask20Bits, 0x72c15);
- for (i=0; i<10; i++) {
- if (i==8){
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, (0x30+i), bMask12Bits, priv_phy0->MAC_info->imr_rfA[i]);
- } else if (i==9) {
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, (0x30+i), bMask20Bits, priv_phy0->MAC_info->imr_rfA[i]);
- } else {
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, (0x2f+i), bMask20Bits, priv_phy0->MAC_info->imr_rfA[i]);
- }
- }
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x00, bMask20Bits, 0x32c15);
- // PHY1 IMR Path A
- //PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMask20Bits, 0x72c15);
- //for (i=0; i<10; i++) {
- // PHY_SetRFReg(priv, RF92CD_PATH_A, (0x2f+i), bMask20Bits, priv->MAC_info->imr_rfA[i]);
- //}
- //PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMask20Bits, 0x32c15);
- // PHY0 IQC
- DMDP_PHY_SetBBReg(0, 0xc80, bMaskDWord, priv_phy0->MAC_info->diqc_c80_b31b0);
- DMDP_PHY_SetBBReg(0, 0xc94, 0xf0000000, priv_phy0->MAC_info->diqc_c94_b31b24);
- DMDP_PHY_SetBBReg(0, 0xc4c, bMaskByte3, priv_phy0->MAC_info->diqc_c4c_b31b28);
- DMDP_PHY_SetBBReg(0, 0xc14, bMaskDWord, priv_phy0->MAC_info->diqc_c14_b31b0);
- DMDP_PHY_SetBBReg(0, 0xca0, 0xf0000000, priv_phy0->MAC_info->diqc_ca0_b31b24);
- DMDP_PHY_SetRFReg(0, RF92CD_PATH_A, 0x08, bMask20Bits, priv_phy0->MAC_info->loft_0A);
- // PHY0 BB Enable
- DMDP_PHY_SetBBReg(0, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
- /*
- * Reload PHY0 MAC default value
- */
- DMDP_RTL_W8(0, 0x550, temp_550);
- DMDP_RTL_W8(0, 0x551, temp_551);
- DMDP_RTL_W8(0, 0x522, temp_522);
-
- // PHY1 IQK
- PHY_SetBBReg(priv, 0xc80, bMaskDWord, 0x40000100);
- PHY_SetBBReg(priv, 0xc94, 0xf0000000, 0);
- PHY_SetBBReg(priv, 0xc4c, bMaskByte3, 0);
- PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100);
- PHY_SetBBReg(priv, 0xca0, 0xf0000000, 0);
- PHY_SetRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 0x84000);
-
- IQK_92D_2G_phy1(priv);
-
- PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
-
- /*
- * Reload MAC default value
- */
- RTL_W8(0x550, temp_550);
- RTL_W8(0x551, temp_551);
- RTL_W8(0x522, temp_522);
-
- printk("%s %d %x\n",__FUNCTION__, __LINE__, PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x18, bMask20Bits,1));
-
- RESTORE_INT(flags);
- return 0;
-}
-
-#endif
-
-void smcc_92D_fill_MAC_info(struct rtl8192cd_priv * priv, struct SMCC_MAC_Info_Tbl *info_tbl)
-{
- int i, val, imr_idx = 0;
-
- unsigned int BB_IDX[18] = {0x800, 0x818, 0x878, 0x884, 0x888, 0x88C, 0x900, 0xA00, 0xC04,
- 0xC4C, 0xC70, 0xC78, 0xC94, 0xC9C, 0xCA0, 0xD00, 0xD04, 0xD2C};
- unsigned int RF_IDX[3] = {0x0B, 0x18, 0x28};
-
- info_tbl->channel = PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x18, bMaskByte0, 1);;
- info_tbl->bandwidth = priv->pshare->CurrentChannelBW==HT_CHANNEL_WIDTH_20_40 ? 1 : 0;
- if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
- if (priv->pshare->offset_2nd_chan == 1)
- info_tbl->bandwidth |= BIT(2); // control upper, 2nd below
- else
- info_tbl->bandwidth |= BIT(1); // control lower, 2nd upper
- }
- if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) {
- // Single PHY IQC Byte 2~22
- info_tbl->siqc_c80_b31b0 = DMDP_PHY_QueryBBReg(0, 0xc80, bMaskDWord);
- info_tbl->siqc_c94_b31b24 = DMDP_PHY_QueryBBReg(0, 0xc94, bMaskByte3);
- info_tbl->siqc_c4c_b31b24 = DMDP_PHY_QueryBBReg(0, 0xc4c, bMaskByte3);
- info_tbl->siqc_c88_b31b0 = DMDP_PHY_QueryBBReg(0, 0xc88, bMaskDWord);
- info_tbl->siqc_c9c_b31b24 = DMDP_PHY_QueryBBReg(0, 0xc9c, bMaskByte3);
- info_tbl->siqc_c14_b31b0 = DMDP_PHY_QueryBBReg(0, 0xc14, bMaskDWord);
- info_tbl->siqc_ca0_b31b24 = DMDP_PHY_QueryBBReg(0, 0xca0, bMaskByte3);
- info_tbl->siqc_c1c_b31b0 = DMDP_PHY_QueryBBReg(0, 0xc1c, bMaskDWord);
- info_tbl->siqc_c78_b15b8 = DMDP_PHY_QueryBBReg(0, 0xc78, bMaskByte1);
- }else{
- // Dual PHY IQC Byte 23~33
- info_tbl->diqc_c80_b31b0 = PHY_QueryBBReg(priv, 0xc80, bMaskDWord);
- info_tbl->diqc_c94_b31b24 = PHY_QueryBBReg(priv, 0xc94, bMaskByte3);
- info_tbl->diqc_c4c_b31b28 = PHY_QueryBBReg(priv, 0xc4c, 0xf0000000);
- info_tbl->diqc_c14_b31b0 = PHY_QueryBBReg(priv, 0xc14, bMaskDWord);
- info_tbl->diqc_ca0_b31b24 = PHY_QueryBBReg(priv, 0xca0, bMaskByte3);
- }
-
- if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY) {
- // 0_B LOFT Byte 115
- info_tbl->loft_0B = DMDP_PHY_QueryRFReg(0, RF92CD_PATH_B, 0x08, bMask20Bits, 1);
- // RF_reg Byte 206~217
- for (i = 0; i<3; i++)
- info_tbl->rfB_reg[i] = DMDP_PHY_QueryRFReg(0, RF92CD_PATH_B, RF_IDX[i], bMask20Bits, 1);
- //
- } else {
- val = info_tbl->channel;
- if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G)
- imr_idx = 0;
- else {
- if (val>=36 && val <=64)
- imr_idx = 1;
- else
- imr_idx = 2;
- }
- // IMR Byte 34~73
- for (i = 0; i<11; i++)
- info_tbl->imr[i] = IMR_SET_N[imr_idx][i];
- if (imr_idx==0)
- info_tbl->imr[11] = 0x32fff;
- else
- info_tbl->imr[11] = 0x32c9a;
-
- // 0_A LOFT Byte 114
- info_tbl->loft_0A = PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 1);
- // BB_reg Byte 122~193
- for (i = 0; i<18; i++)
- info_tbl->bb_reg[i] = PHY_QueryBBReg(priv, BB_IDX[i], bMaskDWord);
- // RF_reg Byte 194~205
- for (i = 0; i<3; i++)
- info_tbl->rfA_reg[i] = PHY_QueryRFReg(priv, RF92CD_PATH_A, RF_IDX[i], bMask20Bits, 1);
- }
-}
-
-void smcc_dump_MAC_info(struct rtl8192cd_priv * priv, struct SMCC_MAC_Info_Tbl *info_tbl)
-{
- int i, flags;
-
- unsigned int BB_IDX[18] = {0x800, 0x818, 0x878, 0x884, 0x888, 0x88C, 0x900, 0xA00, 0xC04,
- 0xC4C, 0xC70, 0xC78, 0xC94, 0xC9C, 0xCA0, 0xD00, 0xD04, 0xD2C};
- unsigned int RF_IDX[3] = {0x0B, 0x18, 0x28};
-
- SAVE_INT_AND_CLI(flags);
-
- printk("info_tbl->channel = %d \n", info_tbl->channel);
- printk("info_tbl->bandwidth = %x \n", info_tbl->bandwidth);
- printk("info_tbl->siqc_c80_b31b0 = %x \n", info_tbl->siqc_c80_b31b0);
- printk("info_tbl->siqc_c94_b31b24 = %x \n", info_tbl->siqc_c94_b31b24);
- printk("info_tbl->siqc_c4c_b31b24 = %x \n", info_tbl->siqc_c4c_b31b24);
- printk("info_tbl->siqc_c88_b31b0 = %x \n", info_tbl->siqc_c88_b31b0);
- printk("info_tbl->siqc_c9c_b31b24 = %x \n", info_tbl->siqc_c9c_b31b24);
- printk("info_tbl->siqc_c14_b31b0 = %x \n", info_tbl->siqc_c14_b31b0);
- printk("info_tbl->siqc_ca0_b31b24 = %x \n", info_tbl->siqc_ca0_b31b24);
- printk("info_tbl->siqc_c1c_b31b0 = %x \n", info_tbl->siqc_c1c_b31b0);
- printk("info_tbl->siqc_c78_b15b8 = %x \n", info_tbl->siqc_c78_b15b8);
- printk("info_tbl->diqc_c80_b31b0 = %x \n", info_tbl->diqc_c80_b31b0);
- printk("info_tbl->diqc_c94_b31b24 = %x \n", info_tbl->diqc_c94_b31b24);
- printk("info_tbl->diqc_c4c_b31b28 = %x \n", info_tbl->diqc_c4c_b31b28);
- printk("info_tbl->diqc_c14_b31b0 = %x \n", info_tbl->diqc_c14_b31b0);
- printk("info_tbl->diqc_ca0_b31b24 = %x \n", info_tbl->diqc_ca0_b31b24);
-
- for (i = 0; i<12; i++)
- printk("info_tbl->imr[%d] = %x \n", i, info_tbl->imr[i]);
-
- printk("info_tbl->loft_0A = %x \n", info_tbl->loft_0A);
- printk("info_tbl->loft_0B = %x \n", info_tbl->loft_0B);
-
- for (i = 0; i<18; i++)
- printk("info_tbl->bb_reg[%d](0x%2x) = %x \n", i, BB_IDX[i], info_tbl->bb_reg[i]);
- for (i = 0; i<3; i++)
- printk("info_tbl->rfA_reg[%d](0x%2x) = %x \n", i, RF_IDX[i], info_tbl->rfA_reg[i]);
- for (i = 0; i<3; i++)
- printk("info_tbl->rfB_reg[%d](0x%2x) = %x \n", i, RF_IDX[i], info_tbl->rfB_reg[i]);
-
-
- RESTORE_INT(flags);
-}
-
-void smcc_signin_MAC_info(struct rtl8192cd_priv * priv, struct SMCC_MAC_Info_Tbl *info_tbl)
-{
- unsigned long flags;
- unsigned int content = 0, info_idx;
- int count = 10;
-
- SAVE_INT_AND_CLI(flags);
-
- RTL_W8(0x422, RTL_R8(0x422)&(~BIT(6)));
- RTL_W8(0x662, RTL_R8(0x662)&(~BIT(0)));
-
- signin_beacon_desc(priv, (unsigned int *)info_tbl, sizeof(struct SMCC_MAC_Info_Tbl));
-
- /*
- * BCN_HEAD
- */
- content |= (RTL_R16(TDECTRL)>>8)<<16;
-
- /*
- * Info_idx: Test chip = 0; MP chip = 1
- */
- info_idx = 0;
- content |= info_idx << 8;
-
- /*
- * set cmd id
- */
- content |= H2C_CMD_INFO_PKT;
-
- signin_h2c_cmd(priv, content, 0);
-
- while (count > 0){
- if (RTL_R8(0x662) & BIT(0)) {
- RTL_W8(0x422, RTL_R8(0x422)|BIT(6));
- printk("SMCC signin MAC info success!\n");
- break;
- }
- count--;
- delay_ms(5);
- }
-
- if (count <= 0)
- printk("SMCC signin MAC info FAIL!\n");
-
- #if 0
- /*
- * MAC register setting
- */
- RTL_W8(0x522, 0x3f);
- RTL_W8(0x550, RTL_R8(0x550)& (~BIT(3)));
- RTL_W8(0x551, RTL_R8(0x551)& (~BIT(3)));
-
- // stop BB
- PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
- #endif
-
- RESTORE_INT(flags);
-}
-
-/*
- En : 1 for enable, 0 for disable
- DMDP_Duration : valid while Mode = 1. The unit is 4ms.
- MODE : 00b for static mode , 01b for preserve mode, 10b and 11b are reserved
- PSV : valid while mode = 1. set 1 for RF resource preservation request
- AP / STA : 0 for AP, 1 for STA
- LINK_STATE : valid while Mode = 0. 0 for no any link, 1 for link exist
- */
-void smcc_signin_linkstate(struct rtl8192cd_priv * priv, unsigned char enable, unsigned char duration, unsigned char link_state)
-{
- unsigned long flags;
- unsigned int content = 0;
-
- printk(">>>> [wlan-%d] %s en=%d, du=%d, st=%d.\n", priv->pshare->wlandev_idx, __FUNCTION__, enable, duration, link_state);
-
- SAVE_INT_AND_CLI(flags);
-
- // Link State
- content |= (link_state & BIT(0))<< 21;
-
- // Enable
- content |= (enable & BIT(0)) << 16;
-
- // DMDP_Duration
- content |= duration << 8;
- // set cmd id
- content |= H2C_CMD_SMCC;
-
- signin_h2c_cmd(priv, content, 0);
-
- RESTORE_INT(flags);
-}
-
-#endif // SMART_CONCURRENT_92D
#endif //CONFIG_RTL_92D_DMDP
#endif // CONFIG_RTL_92D_SUPPORT
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