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-rw-r--r--target/linux/mvebu/patches-3.8/038-arm_mvebu_add_pcie_dt_axp.patch284
1 files changed, 284 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.8/038-arm_mvebu_add_pcie_dt_axp.patch b/target/linux/mvebu/patches-3.8/038-arm_mvebu_add_pcie_dt_axp.patch
new file mode 100644
index 000000000..647f1da5f
--- /dev/null
+++ b/target/linux/mvebu/patches-3.8/038-arm_mvebu_add_pcie_dt_axp.patch
@@ -0,0 +1,284 @@
+The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
+PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
+PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
+units (two 4x or quad 1x and two 4x/1x). We therefore add the
+necessary Device Tree informations to make those PCIe interfaces
+usable.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/boot/dts/armada-xp-mv78230.dtsi | 62 +++++++++++++++++
+ arch/arm/boot/dts/armada-xp-mv78260.dtsi | 72 +++++++++++++++++++
+ arch/arm/boot/dts/armada-xp-mv78460.dtsi | 112 ++++++++++++++++++++++++++++++
+ 3 files changed, 246 insertions(+)
+
+--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+@@ -76,5 +76,67 @@
+ #interrupts-cells = <2>;
+ interrupts = <87>, <88>, <89>;
+ };
++
++ /*
++ * MV78230 has 2 PCIe units Gen2.0: One unit can be
++ * configured as x4 or quad x1 lanes. One unit is
++ * x4/x1.
++ */
++ pcie-controller {
++ compatible = "marvell,armada-370-xp-pcie";
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
++ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
++ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
++ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
++ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */>;
++
++ pcie0.0@0xd0040000 {
++ reg = <0x0 0x2000>;
++ interrupts = <58>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++
++ pcie0.1@0xd0044000 {
++ reg = <0x4000 0x2000>;
++ interrupts = <59>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <1>;
++ status = "disabled";
++ };
++
++ pcie0.2@0xd0048000 {
++ reg = <0x8000 0x2000>;
++ interrupts = <60>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <2>;
++ status = "disabled";
++ };
++
++ pcie0.3@0xd004C000 {
++ reg = <0xC000 0x2000>;
++ interrupts = <61>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <3>;
++ status = "disabled";
++ };
++
++ pcie2@0xd0042000 {
++ reg = <0x2000 0x2000>;
++ interrupts = <99>;
++ clocks = <&gateclk 7>;
++ marvell,pcie-port = <2>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+@@ -96,5 +96,77 @@
+ clocks = <&gateclk 1>;
+ status = "disabled";
+ };
++
++ /*
++ * MV78260 has 3 PCIe units Gen2.0: Two units can be
++ * configured as x4 or quad x1 lanes. One unit is
++ * x4/x1.
++ */
++ pcie-controller {
++ compatible = "marvell,armada-370-xp-pcie";
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
++ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
++ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
++ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
++ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
++ 0x12000 0xd0082000 0x2000 /* port3x1_port0 */>;
++
++ pcie0.0@0xd0040000 {
++ reg = <0x0 0x2000>;
++ interrupts = <58>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++
++ pcie0.1@0xd0044000 {
++ reg = <0x4000 0x2000>;
++ interrupts = <59>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <1>;
++ status = "disabled";
++ };
++
++ pcie0.2@0xd0048000 {
++ reg = <0x8000 0x2000>;
++ interrupts = <60>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <2>;
++ status = "disabled";
++ };
++
++ pcie0.3@0xd004C000 {
++ reg = <0xC000 0x2000>;
++ interrupts = <61>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <3>;
++ status = "disabled";
++ };
++
++ pcie2@0xd0042000 {
++ reg = <0x2000 0x2000>;
++ interrupts = <99>;
++ clocks = <&gateclk 7>;
++ marvell,pcie-port = <2>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++
++ pcie3@0xd0082000 {
++ reg = <0x12000 0x2000>;
++ interrupts = <103>;
++ clocks = <&gateclk 8>;
++ marvell,pcie-port = <3>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+@@ -111,5 +111,117 @@
+ clocks = <&gateclk 1>;
+ status = "disabled";
+ };
++
++ /*
++ * MV78460 has 4 PCIe units Gen2.0: Two units can be
++ * configured as x4 or quad x1 lanes. Two units are
++ * x4/x1.
++ */
++ pcie-controller {
++ compatible = "marvell,armada-370-xp-pcie";
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
++ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
++ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
++ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
++ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
++ 0x10000 0xd0080000 0x2000 /* port1x1_port0 */
++ 0x12000 0xd0082000 0x2000 /* port3x1_port0 */
++ 0x14000 0xd0084000 0x2000 /* port1x1_port1 */
++ 0x18000 0xd0088000 0x2000 /* port1x1_port2 */
++ 0x1C000 0xd008C000 0x2000 /* port1x1_port3 */>;
++
++ pcie0.0@0xd0040000 {
++ reg = <0x0 0x2000>;
++ interrupts = <58>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++
++ pcie0.1@0xd0044000 {
++ reg = <0x4000 0x2000>;
++ interrupts = <59>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <1>;
++ status = "disabled";
++ };
++
++ pcie0.2@0xd0048000 {
++ reg = <0x8000 0x2000>;
++ interrupts = <60>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <2>;
++ status = "disabled";
++ };
++
++ pcie0.3@0xd004C000 {
++ reg = <0xC000 0x2000>;
++ interrupts = <61>;
++ clocks = <&gateclk 5>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <3>;
++ status = "disabled";
++ };
++
++ pcie1.0@0xd0040000 {
++ reg = <0x10000 0x2000>;
++ interrupts = <62>;
++ clocks = <&gateclk 6>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++
++ pcie1.1@0xd0044000 {
++ reg = <0x14000 0x2000>;
++ interrupts = <63>;
++ clocks = <&gateclk 6>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <1>;
++ status = "disabled";
++ };
++
++ pcie1.2@0xd0048000 {
++ reg = <0x18000 0x2000>;
++ interrupts = <64>;
++ clocks = <&gateclk 6>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <2>;
++ status = "disabled";
++ };
++
++ pcie1.3@0xd004C000 {
++ reg = <0x1C000 0x2000>;
++ interrupts = <65>;
++ clocks = <&gateclk 6>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <3>;
++ status = "disabled";
++ };
++
++ pcie2@0xd0042000 {
++ reg = <0x2000 0x2000>;
++ interrupts = <99>;
++ clocks = <&gateclk 7>;
++ marvell,pcie-port = <2>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++
++ pcie3@0xd0082000 {
++ reg = <0x12000 0x2000>;
++ interrupts = <103>;
++ clocks = <&gateclk 8>;
++ marvell,pcie-port = <3>;
++ marvell,pcie-lane = <0>;
++ status = "disabled";
++ };
++ };
+ };
+ };
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