diff options
Diffstat (limited to 'target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch deleted file mode 100644 index 49ff66310..000000000 --- a/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch +++ /dev/null @@ -1,35 +0,0 @@ -Index: linux-2.6.30.5/arch/mips/kernel/cevt-r4k.c -=================================================================== ---- linux-2.6.30.5.orig/arch/mips/kernel/cevt-r4k.c 2009-08-16 23:19:38.000000000 +0200 -+++ linux-2.6.30.5/arch/mips/kernel/cevt-r4k.c 2009-09-02 18:26:26.000000000 +0200 -@@ -21,6 +21,22 @@ - - #ifndef CONFIG_MIPS_MT_SMTC - -+/* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -30,6 +46,7 @@ - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } |