diff options
Diffstat (limited to 'target/linux/brcm63xx/patches-3.8/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.8/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.8/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch b/target/linux/brcm63xx/patches-3.8/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch new file mode 100644 index 000000000..094eaa88c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.8/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch @@ -0,0 +1,138 @@ +From b14de5c78d32f8f98535a99ea56bb924beb66810 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 25 Apr 2013 00:31:29 +0200 +Subject: [PATCH 07/13] MIPS: BCM63XX: populate irq_{stat,mask}_addr for + second CPU + +Populate it for all platforms with a BMIPS4350. + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 28 +++++++++++++++++++++++++++- + 1 file changed, 27 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -30,6 +30,8 @@ static void __internal_irq_unmask_64(uns + #ifdef CONFIG_BCM63XX_CPU_6328 + #define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0) + #define irq_mask_reg0 PERF_IRQMASK_6328_REG(0) ++#define irq_stat_reg1 PERF_IRQSTAT_6328_REG(1) ++#define irq_mask_reg1 PERF_IRQMASK_6328_REG(1) + #define irq_bits 64 + #define is_ext_irq_cascaded 1 + #define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE) +@@ -41,6 +43,8 @@ static void __internal_irq_unmask_64(uns + #ifdef CONFIG_BCM63XX_CPU_6338 + #define irq_stat_reg0 PERF_IRQSTAT_6338_REG + #define irq_mask_reg0 PERF_IRQMASK_6338_REG ++#define irq_stat_reg1 0 ++#define irq_mask_reg1 0 + #define irq_bits 32 + #define is_ext_irq_cascaded 0 + #define ext_irq_start 0 +@@ -52,6 +56,8 @@ static void __internal_irq_unmask_64(uns + #ifdef CONFIG_BCM63XX_CPU_6345 + #define irq_stat_reg0 PERF_IRQSTAT_6345_REG + #define irq_mask_reg0 PERF_IRQMASK_6345_REG ++#define irq_stat_reg1 0 ++#define irq_mask_reg1 0 + #define irq_bits 32 + #define is_ext_irq_cascaded 0 + #define ext_irq_start 0 +@@ -63,6 +69,8 @@ static void __internal_irq_unmask_64(uns + #ifdef CONFIG_BCM63XX_CPU_6348 + #define irq_stat_reg0 PERF_IRQSTAT_6348_REG + #define irq_mask_reg0 PERF_IRQMASK_6348_REG ++#define irq_stat_reg1 0 ++#define irq_mask_reg1 0 + #define irq_bits 32 + #define is_ext_irq_cascaded 0 + #define ext_irq_start 0 +@@ -74,6 +82,8 @@ static void __internal_irq_unmask_64(uns + #ifdef CONFIG_BCM63XX_CPU_6358 + #define irq_stat_reg0 PERF_IRQSTAT_6358_REG(0) + #define irq_mask_reg0 PERF_IRQMASK_6358_REG(0) ++#define irq_stat_reg1 PERF_IRQSTAT_6358_REG(1) ++#define irq_mask_reg1 PERF_IRQMASK_6358_REG(1) + #define irq_bits 32 + #define is_ext_irq_cascaded 1 + #define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE) +@@ -85,6 +95,8 @@ static void __internal_irq_unmask_64(uns + #ifdef CONFIG_BCM63XX_CPU_6362 + #define irq_stat_reg0 PERF_IRQSTAT_6362_REG(0) + #define irq_mask_reg0 PERF_IRQMASK_6362_REG(0) ++#define irq_stat_reg1 PERF_IRQSTAT_6362_REG(1) ++#define irq_mask_reg1 PERF_IRQMASK_6362_REG(1) + #define irq_bits 64 + #define is_ext_irq_cascaded 1 + #define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE) +@@ -96,6 +108,8 @@ static void __internal_irq_unmask_64(uns + #ifdef CONFIG_BCM63XX_CPU_6368 + #define irq_stat_reg0 PERF_IRQSTAT_6368_REG(0) + #define irq_mask_reg0 PERF_IRQMASK_6368_REG(0) ++#define irq_stat_reg1 PERF_IRQSTAT_6368_REG(1) ++#define irq_mask_reg1 PERF_IRQMASK_6368_REG(1) + #define irq_bits 64 + #define is_ext_irq_cascaded 1 + #define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE) +@@ -117,13 +131,15 @@ static void __internal_irq_unmask_64(uns + + #define irq_stat_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0) + #define irq_mask_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0) ++#define irq_stat_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg1) ++#define irq_mask_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg1) + + static inline void bcm63xx_init_irq(void) + { + } + #else /* ! BCMCPU_RUNTIME_DETECT */ + +-static u32 irq_stat_addr0, irq_mask_addr0; ++static u32 irq_stat_addr0, irq_mask_addr0, irq_stat_addr1, irq_mask_addr1; + static void (*dispatch_internal)(void); + static int is_ext_irq_cascaded; + static unsigned int ext_irq_count; +@@ -138,11 +154,15 @@ static void bcm63xx_init_irq(void) + + irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF); + irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF); ++ irq_stat_addr1 = bcm63xx_regset_address(RSET_PERF); ++ irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF); + + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0); + irq_mask_addr0 += PERF_IRQMASK_6328_REG(0); ++ irq_stat_addr1 += PERF_IRQSTAT_6328_REG(1); ++ irq_stat_addr1 += PERF_IRQMASK_6328_REG(1); + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -174,6 +194,8 @@ static void bcm63xx_init_irq(void) + case BCM6358_CPU_ID: + irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0); + irq_mask_addr0 += PERF_IRQMASK_6358_REG(0); ++ irq_stat_addr1 += PERF_IRQSTAT_6358_REG(1); ++ irq_mask_addr1 += PERF_IRQMASK_6358_REG(1); + irq_bits = 32; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -184,6 +206,8 @@ static void bcm63xx_init_irq(void) + case BCM6362_CPU_ID: + irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0); + irq_mask_addr0 += PERF_IRQMASK_6362_REG(0); ++ irq_stat_addr1 += PERF_IRQSTAT_6362_REG(1); ++ irq_mask_addr1 += PERF_IRQMASK_6362_REG(1); + irq_bits = 64; + ext_irq_count = 4; + is_ext_irq_cascaded = 1; +@@ -194,6 +218,8 @@ static void bcm63xx_init_irq(void) + case BCM6368_CPU_ID: + irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0); + irq_mask_addr0 += PERF_IRQMASK_6368_REG(0); ++ irq_stat_addr1 += PERF_IRQSTAT_6368_REG(1); ++ irq_mask_addr1 += PERF_IRQMASK_6368_REG(1); + irq_bits = 64; + ext_irq_count = 6; + is_ext_irq_cascaded = 1; |