diff options
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 0a3167862..ab00d19e1 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -75,10 +75,10 @@ #define AR71XX_CPU_IRQ_BASE 0 #define AR71XX_MISC_IRQ_BASE 8 -#define AR71XX_MISC_IRQ_COUNT 8 -#define AR71XX_GPIO_IRQ_BASE 16 +#define AR71XX_MISC_IRQ_COUNT 32 +#define AR71XX_GPIO_IRQ_BASE 40 #define AR71XX_GPIO_IRQ_COUNT 32 -#define AR71XX_PCI_IRQ_BASE 48 +#define AR71XX_PCI_IRQ_BASE 72 #define AR71XX_PCI_IRQ_COUNT 8 #define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) @@ -96,6 +96,11 @@ #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) +#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8) +#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9) +#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10) +#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11) +#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12) #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) @@ -465,6 +470,12 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear); #define AR91XX_DDR_REG_FLUSH_USB 0x84 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88 +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 + + #define PCI_WIN0_OFFS 0x10000000 #define PCI_WIN1_OFFS 0x11000000 #define PCI_WIN2_OFFS 0x12000000 @@ -564,6 +575,11 @@ void ar71xx_ddr_flush(u32 reg); #define WDOG_CTRL_ACTION_NMI 2 /* NMI */ #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ +#define MISC_INT_ENET_LINK BIT(12) +#define MISC_INT_DDR_PERF BIT(11) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) #define MISC_INT_DMA BIT(7) #define MISC_INT_OHCI BIT(6) #define MISC_INT_PERFC BIT(5) |