diff options
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/Makefile | 19 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/bspchip.h | 571 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/bspcpu.h | 54 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/bspinit.h | 18 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/dev_usb.c | 317 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/dev_usb.h | 38 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/irq.c | 380 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/kgdb.c | 81 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/pci.c | 1265 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/prom.c | 184 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/rlxhack.h | 21 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/serial.c | 94 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/setup.c | 196 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/timer.c | 146 | ||||
| -rw-r--r-- | target/linux/realtek/files/arch/rlx/bsp/vmlinux.lds.S | 296 |
15 files changed, 0 insertions, 3680 deletions
diff --git a/target/linux/realtek/files/arch/rlx/bsp/Makefile b/target/linux/realtek/files/arch/rlx/bsp/Makefile deleted file mode 100644 index 0406f03e0..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -include $(TOPDIR)/.config - -core-y += arch/rlx/bsp/ -cflags-y += -Iinclude/asm-rlx -Iarch/rlx/bsp/ -#load-y += 0xffffffff80000000 -load-y += 0x80000000 - -extra-y += vmlinux.lds - -obj-y := irq.o prom.o serial.o setup.o timer.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_ARCH_BUS_USB) += dev_usb.o - -EXTRA_AFLAGS := $(CFLAGS) -EXTRA_CFLAGS += -I$(TOPDIR)/drivers/net/rtl819x/AsicDriver -EXTRA_CFLAGS += -I$(TOPDIR)/drivers/net/rtl819x/common -ifdef CONFIG_RTL_819X_SWCORE -EXTRA_CFLAGS += -DCONFIG_RTL_819X_SWCORE -endif diff --git a/target/linux/realtek/files/arch/rlx/bsp/bspchip.h b/target/linux/realtek/files/arch/rlx/bsp/bspchip.h deleted file mode 100644 index 0df3f510e..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/bspchip.h +++ /dev/null @@ -1,571 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2006, Realtek Semiconductor Corp. - * Copyright (C) 2013, Artur Artamonov <artur@advem.lv> - */ - -#ifndef __LEXRA_BSP_H -#define __LEXRA_BSP_H - -#include <linux/autoconf.h> - -#include "rlxhack.h" - -#define PADDR(addr) ((addr) & 0x1FFFFFFF) - -/* - * IRQ Controller - */ -#define BSP_IRQ_CPU_BASE 0 -#define BSP_IRQ_CPU_NUM 8 - -#define BSP_IRQ_LOPI_BASE (BSP_IRQ_CPU_BASE + BSP_IRQ_CPU_NUM) -#define BSP_IRQ_LOPI_NUM 8 - -#define BSP_IRQ_ICTL_BASE (BSP_IRQ_LOPI_BASE + BSP_IRQ_LOPI_NUM) -#define BSP_IRQ_ICTL_NUM 32 - -/* - * ==================================== - * Platform Configurable Common Options - * ==================================== - */ - -#define BSP_SYS_CLK_RATE (200000000) //HS1 clock : 200 MHz -#define BSP_BAUDRATE 38400 // ex. 19200 or 38400 or 57600 or 115200 - //For Early Debug - -/* - * RTL8196b Interrupt Scheme (Subject to change) - * - * Source EXT_INT CPU INT LOPI IRQ - * -------- ------- ------- ------- ------ - * PCIB0TO 0 2 - 16+0 - * PCIB1TO 1 2 - 16+1 - * LBCTMOm0 2 2 - 16+2 - * LBCTMOm1 3 2 - 16+3 - * LBCTMOs 4 2 - 16+4 - * TIMER0 8 - 5 8+5 - * TIMER1 9 2 - 16+9 - * USB 10 - 1 8+1 - * UART0 12 2 - 16+12 - * UART1 13 2 - 16+13 - * VoIP 14 2 - 16+14 - * SWCORE 15 - 4 8+4 - * GPIO_ABCD 16 2 - 16+16 - * GPIO_EFGH 17 2 - 16+17 - * NFBI 18 - 6 8+6 - * PCM 19 - 7 8+7 - * CRYPTO 20 2 - 16+20 - * PCIE0 21 - 2 8+2 - * PCIE1 22 - 3 8+3 - * I2S 26 - 0 8+6 - */ - -/* - * IRQ Mapping - */ -#define BSP_ICTL_IRQ (BSP_IRQ_CPU_BASE + 2) //for irq cascade - -//---------------------------------------------------------------------- -#if defined(CONFIG_RTL_8196C) -#define BSP_ICTL_IRQ (BSP_IRQ_CPU_BASE + 2) //for irq cascade -#define BSP_TC0_IRQ (13) /* BSP_IRQ_LOPI_BASE + 5 */ -#define BSP_TC1_IRQ (BSP_IRQ_ICTL_BASE + 15) -#define BSP_USB_IRQ (10) /* BSP_IRQ_LOPI_BASE + 2 */ -//#define BSP_UART0_IRQ (BSP_IRQ_ICTL_BASE + 0) -#define BSP_UART0_IRQ (BSP_IRQ_ICTL_BASE + 7) /* BSP_IRQ_LOPI_BASE + 0 */ -#define BSP_SWCORE_IRQ (12) /* BSP_IRQ_LOPI_BASE + 4 */ -#define BSP_GPIO_ABCD_IRQ (BSP_IRQ_ICTL_BASE + 9) -#define BSP_PCIE_IRQ (11) /* BSP_IRQ_LOPI_BASE + 3 */ -#define BSP_NFBI_IRQ 15) /* BSP_IRQ_LOPI_BASE + 7 */ -//---------------------------------------------------------------------- - -//#elseif CONFIG_RTL_819XD -#elif defined(CONFIG_RTL_819XD) -#define BSP_PCIB0TMO_IRQ (BSP_IRQ_ICTL_BASE + 0) -#define BSP_PCIB1TMO_IRQ (BSP_IRQ_ICTL_BASE + 1) -#define BSP_LBCTMOm0_IRQ (BSP_IRQ_ICTL_BASE + 2) -#define BSP_LBCTMOm1_IRQ (BSP_IRQ_ICTL_BASE + 3) -#define BSP_LBCTMOs_IRQ (BSP_IRQ_ICTL_BASE + 4) -#define BSP_TC0_IRQ (13) /* BSP_IRQ_LOPI_BASE + 5 */ -#define BSP_TC1_IRQ (BSP_IRQ_ICTL_BASE + 9) -#define BSP_USB_IRQ (10) /* BSP_IRQ_LOPI_BASE + 2 */ -#define BSP_OTG_IRQ (15) //(BSP_IRQ_LOPI_BASE + 7) //wei add ,bit 15=8+7 -//#define BSP_UART0_IRQ (BSP_IRQ_ICTL_BASE + 0) -#define BSP_UART0_IRQ (8) /* BSP_IRQ_LOPI_BASE + 0 */ -#define BSP_UART1_IRQ (BSP_IRQ_ICTL_BASE + 13) -#define BSP_SWCORE_IRQ (12) /* BSP_IRQ_LOPI_BASE + 4 */ -#define BSP_GPIO_ABCD_IRQ (BSP_IRQ_ICTL_BASE + 16) -#define BSP_GPIO_EFGH_IRQ (BSP_IRQ_ICTL_BASE + 17) -#define BSP_NFBI_IRQ (15) /* BSP_IRQ_LOPI_BASE + 7 */ -#define BSP_PCM_IRQ (9) /* BSP_IRQ_LOPI_BASE + 1 */ -#define BSP_CRYPTO_IRQ (BSP_IRQ_ICTL_BASE + 20) -#define BSP_GDMA_IRQ (BSP_IRQ_ICTL_BASE + 23) -#define BSP_PCIE_IRQ (11) /* BSP_IRQ_LOPI_BASE + 3 */ -#define BSP_PCIE2_IRQ (14) /* BSP_IRQ_LOPI_BASE + 6 */ -//#define BSP_I2S_IRQ (BSP_IRQ_LOPI_BASE + 0) -//#define BSP_I2S_IRQ (BSP_IRQ_ICTL_BASE + 12) -#endif -/* - * Interrupt Routing Selection - */ -#define BSP_IRQ_CASCADE 2 -#define BSP_PTM_RS BSP_IRQ_CASCADE -#define BSP_LBCTMOs2_RS BSP_IRQ_CASCADE -#define BSP_LBCTMOs1_RS BSP_IRQ_CASCADE -#define BSP_PKT_RS BSP_IRQ_CASCADE -#define BSP_SPI_RS BSP_IRQ_CASCADE -#define BSP_NIC100_RS BSP_IRQ_CASCADE -#define BSP_SAR_RS BSP_IRQ_CASCADE -#define BSP_DMT_RS BSP_IRQ_CASCADE -#define BSP_PCIE_RS BSP_PCIE_IRQ -#define BSP_PCIE2_RS BSP_PCIE2_IRQ -#define BSP_GDMA_RS BSP_IRQ_CASCADE -#define BSP_SECURITY_RS BSP_IRQ_CASCADE -#if defined(CONFIG_RTL_8196C) - #define BSP_PCM_RS BSP_IRQ_CASCADE -#else - #define BSP_PCM_RS BSP_PCM_IRQ -#endif -#define BSP_NFBI_RS BSP_NFBI_IRQ -#define BSP_GPIO_EFGH_RS BSP_IRQ_CASCADE -#define BSP_GPIO_ABCD_RS BSP_IRQ_CASCADE -#define BSP_SW_RS BSP_SWCORE_IRQ -//#define BSP_UART0_RS BSP_UART0_IRQ -#define BSP_UART0_RS BSP_IRQ_CASCADE -#define BSP_UART1_RS BSP_IRQ_CASCADE -#define BSP_USB_D_RS BSP_IRQ_CASCADE -#define BSP_USB_H_RS BSP_USB_IRQ -#define BSP_OTG_RS BSP_OTG_IRQ -#define BSP_TC0_RS BSP_TC0_IRQ//13 -#define BSP_TC1_RS BSP_IRQ_CASCADE -#define BSP_LBCTMOm2_RS BSP_IRQ_CASCADE -#define BSP_LBCTMOm1_RS BSP_IRQ_CASCADE -#define BSP_SPEED_RS BSP_IRQ_CASCADE -#define BSP_LBCTMOs0_RS BSP_IRQ_CASCADE -#define BSP_LBCTMOm0_RS BSP_IRQ_CASCADE -#define BSP_OCPTMO_RS BSP_IRQ_CASCADE -#define BSP_PCIB0TO_RS BSP_IRQ_CASCADE -#define BSP_NONE BSP_IRQ_CASCADE -#define BSP_PCIB0TMO_RS BSP_IRQ_CASCADE -#define BSP_PCIB1TMO_RS BSP_IRQ_CASCADE -#define BSP_LBCTMOs_RS BSP_IRQ_CASCADE -#define BSP_CRYPTO_RS BSP_IRQ_CASCADE -//#define BSP_I2S_RS BSP_I2S_IRQ -//#define BSP_I2S_RS BSP_IRQ_CASCADE - -#if defined(CONFIG_RTL_8196C) - #define BSP_DIVISOR 1000 -#else - #define BSP_DIVISOR 8000 -#endif - -#if BSP_DIVISOR > (1 << 16) -#error "Exceed the Maximum Value of DivFactor" -#endif - -/* - * ========================== - * Platform Register Settings - * ========================== - */ - -/* - * CPU - */ - -#define BSP_IMEM_BASE 0x00C00000 -#define BSP_IMEM_TOP 0x00C03FFF - -#define BSP_DMEM_BASE 0x00C04000 -#define BSP_DMEM_TOP 0x00C05FFF - -/* - * Memory Controller - */ -#define BSP_MC_MCR 0xB8001000 -#define BSP_MC_MCR_VAL 0x92A28000 - -#define BSP_MC_MTCR0 0xB8001004 -#define BSP_MC_MTCR0_VAL 0x12120000 - -#define BSP_MC_MTCR1 0xB8001008 -#define BSP_MC_MTCR1_VAL 0x00000FEB - -#define BSP_MC_PFCR 0xB8001010 -#define BSP_MC_PFCR_VAL 0x00000101 - - -#define BSP_MC_BASE 0xB8001000 -#define BSP_NCR (BSP_MC_BASE + 0x100) -#define BSP_NSR (BSP_MC_BASE + 0x104) -#define BSP_NCAR (BSP_MC_BASE + 0x108) -#define BSP_NADDR (BSP_MC_BASE + 0x10C) -#define BSP_NDR (BSP_MC_BASE + 0x110) - -#define BSP_SFCR (BSP_MC_BASE + 0x200) -#define BSP_SFDR (BSP_MC_BASE + 0x204) - -/* -* UART -*/ -#define BSP_UART0_BASE 0xB8002000 -#define BSP_UART0_MAP_BASE 0x18002000 -#define BSP_UART0_RBR (BSP_UART0_BASE + 0x000) -#define BSP_UART0_THR (BSP_UART0_BASE + 0x000) -#define BSP_UART0_DLL (BSP_UART0_BASE + 0x000) -#define BSP_UART0_IER (BSP_UART0_BASE + 0x004) -#define BSP_UART0_DLM (BSP_UART0_BASE + 0x004) -#define BSP_UART0_IIR (BSP_UART0_BASE + 0x008) -#define BSP_UART0_FCR (BSP_UART0_BASE + 0x008) -#define BSP_UART0_LCR (BSP_UART0_BASE + 0x00C) -#define BSP_UART0_MCR (BSP_UART0_BASE + 0x010) -#define BSP_UART0_LSR (BSP_UART0_BASE + 0x014) - -#define BSP_UART1_BASE 0xB8002100 -#define BSP_UART1_MAP_BASE 0x18002100 -#define BSP_UART1_RBR (BSP_UART1_BASE + 0x000) -#define BSP_UART1_THR (BSP_UART1_BASE + 0x000) -#define BSP_UART1_DLL (BSP_UART1_BASE + 0x000) -#define BSP_UART1_IER (BSP_UART1_BASE + 0x004) -#define BSP_UART1_DLM (BSP_UART1_BASE + 0x004) -#define BSP_UART1_IIR (BSP_UART1_BASE + 0x008) -#define BSP_UART1_FCR (BSP_UART1_BASE + 0x008) -#define BSP_FCR_EN 0x01 -#define BSP_FCR_RXRST 0x02 -#define BSP_RXRST 0x02 -#define BSP_FCR_TXRST 0x04 -#define BSP_TXRST 0x04 -#define BSP_FCR_DMA 0x08 -#define BSP_FCR_RTRG 0xC0 -#define BSP_CHAR_TRIGGER_01 0x00 -#define BSP_CHAR_TRIGGER_04 0x40 -#define BSP_CHAR_TRIGGER_08 0x80 -#define BSP_CHAR_TRIGGER_14 0xC0 -#define BSP_UART1_LCR (BSP_UART1_BASE + 0x00C) -#define BSP_LCR_WLN 0x03 -#define BSP_CHAR_LEN_5 0x00 -#define BSP_CHAR_LEN_6 0x01 -#define BSP_CHAR_LEN_7 0x02 -#define BSP_CHAR_LEN_8 0x03 -#define BSP_LCR_STB 0x04 -#define BSP_ONE_STOP 0x00 -#define BSP_TWO_STOP 0x04 -#define BSP_LCR_PEN 0x08 -#define BSP_PARITY_ENABLE 0x01 -#define BSP_PARITY_DISABLE 0x00 -#define BSP_LCR_EPS 0x30 -#define BSP_PARITY_ODD 0x00 -#define BSP_PARITY_EVEN 0x10 -#define BSP_PARITY_MARK 0x20 -#define BSP_PARITY_SPACE 0x30 -#define BSP_LCR_BRK 0x40 -#define BSP_LCR_DLAB 0x80 -#define BSP_DLAB 0x80 -#define BSP_UART1_MCR (BSP_UART1_BASE + 0x010) -#define BSP_UART1_LSR (BSP_UART1_BASE + 0x014) -#define BSP_LSR_DR 0x01 -#define BSP_RxCHAR_AVAIL 0x01 -#define BSP_LSR_OE 0x02 -#define BSP_LSR_PE 0x04 -#define BSP_LSR_FE 0x08 -#define BSP_LSR_B 0x10 -#define BSP_LSR_THRE 0x20 -#define BSP_TxCHAR_AVAIL 0x00 -#define BSP_TxCHAR_EMPTY 0x20 -#define BSP_LSR_TEMT 0x40 -#define BSP_LSR_RFE 0x80 - -/* - * Interrupt Controller - */ -#define BSP_GIMR 0xB8003000 - -#if defined(CONFIG_RTL_8196C) - -#define BSP_USB_H_IE (1 << 16) -#define BSP_TC1_IE (1 << 15) -#define BSP_TC0_IE (1 << 14) -#define BSP_GDMA_IE (1 << 11) -#define BSP_PCIE_IE (1 << 10) // shall be 22 -#define BSP_PCI_IE (1 << 10) -#define BSP_GPIO_ABCD_IE 1 << 9) -#define BSP_SW_IE (1 << 8) -#define BSP_UART0_IE (1 << 7) - -#else - -#define BSP_I2S_IE (1 << 26) -#define BSP_GDMA_IE (1 << 23) -#define BSP_PCIE2_IE (1 << 22) -#define BSP_PCIE_IE (1 << 21) // shall be 22 -#define BSP_CRYPTO_IE (1 << 20) -#define BSP_PCM_IE (1 << 19) -#define BSP_NFBI_IE (1 << 18) -#define BSP_GPIO_EFGH_IE (1 << 17) -#define BSP_GPIO_ABCD_IE (1 << 16) -#define BSP_SW_IE (1 << 15) -#define BSP_PCI_IE (1 << 14) -#define BSP_UART1_IE (1 << 13) -#define BSP_UART0_IE (1 << 12) -#define BSP_OTG_IE (1 << 11) //wei add -#define BSP_USB_H_IE (1 << 10) -#define BSP_TC1_IE (1 << 9) -#define BSP_TC0_IE (1 << 8) -#define BSP_LBCTMOs_IE (1 << 4) -#define BSP_LBCTMOm1_IE (1 << 3) -#define BSP_LBCTMOm0_IE (1 << 2) -#define BSP_PCIB1TO_IE (1 << 1) -#define BSP_PCIB0TO_IE (1 << 0) -#endif - - -#define BSP_GISR 0xB8003004 - -#if defined(CONFIG_RTL_8196C) - -#define BSP_USB_H_IP (1 << 16) -#define BSP_TC1_IP (1 << 15) -#define BSP_TC0_IP (1 << 14) -#define BSP_GDMA_IP (1 << 11) -#define BSP_PCIE_IP (1 << 10) -#define BSP_PCI_IP (1 << 10) -#define BSP_GPIO_ABCD_IP (1 << 9) -#define BSP_SW_IP (1 << 8) -#define BSP_UART0_IP (1 << 7) - -#elif defined(CONFIG_RTL_819XD) - -#define BSP_I2S_IP (1 << 26) -#define BSP_GDMA_IP (1 << 23) -#define BSP_PCIE2_IP (1 << 21) -#define BSP_PCIE_IP (1 << 22) // shall be 22 -#define BSP_CRYPTO_IP (1 << 20) -#define BSP_PCM_IP (1 << 19) -#define BSP_NFBI_IP (1 << 18) -#define BSP_GPIO_EFGH_IP (1 << 17) -#define BSP_GPIO_ABCD_IP (1 << 16) -#define BSP_SW_IP (1 << 15) -#define BSP_PCI_IP (1 << 14) -#define BSP_UART1_IP (1 << 13) -#define BSP_UART0_IP (1 << 12) -#define BSP_OTG_IP (1 << 11)//wei add -#define BSP_USB_H_IP (1 << 10) -#define BSP_TC1_IP (1 << 9) -#define BSP_TC0_IP (1 << 8) -#define BSP_LBCTMOs_IP (1 << 4) -#define BSP_LBCTMOm1_IP (1 << 3) -#define BSP_LBCTMOm0_IP (1 << 2) -#define BSP_PCIB1TO_IP (1 << 1) -#define BSP_PCIB0TO_IP (1 << 0) - -#endif - -//---------------------------------------------------------------------- -#define BSP_IRR0 0xB8003008 -#if defined(CONFIG_RTL_8196C) - -#define BSP_IRR0_SETTING ((BSP_UART0_RS << 28) | \ - (BSP_NONE << 24) | \ - (BSP_NONE<< 20) | \ - (BSP_NONE << 16) | \ - (BSP_NONE << 12) | \ - (BSP_NONE << 8) | \ - (BSP_NONE<< 4) | \ - (BSP_NONE<< 0) \ -) - -#else - -#define BSP_IRR0_SETTING ((BSP_LBCTMOm2_RS << 28) | \ - (BSP_LBCTMOm1_RS << 24) | \ - (BSP_SPEED_RS<< 20) | \ - (BSP_LBCTMOs0_RS << 16) | \ - (BSP_LBCTMOm0_RS << 12) | \ - (BSP_OCPTMO_RS << 8) | \ - (BSP_NONE<< 4) | \ - (BSP_PCIB0TO_RS<< 0) \ -) - -#endif - - -#define BSP_IRR1 0xB800300C - -#if defined(CONFIG_RTL_8196C) - -#define BSP_IRR1_SETTING ((BSP_TC1_RS<<28) |\ - (BSP_TC0_RS<<24) |\ - (BSP_NONE<<20) |\ - (BSP_OCPTMO_RS<<16) |\ - (BSP_GDMA_RS<<12) |\ - (BSP_PCIE_RS<<8) |\ - (BSP_GPIO_ABCD_RS<<4) |\ - (BSP_SW_RS<<0) \ -) -#else - -#define BSP_IRR1_SETTING ((BSP_SW_RS<< 28) | \ - (BSP_NONE<< 24) | \ - (BSP_UART1_RS << 20) | \ - (BSP_UART0_RS << 16) | \ - (BSP_OTG_RS << 12) | \ - (BSP_USB_H_RS << 8) | \ - (BSP_TC1_RS << 4) | \ - (BSP_TC0_RS << 0) \ -) -#endif - - -#define BSP_IRR2 0xB8003010 - -#if defined(CONFIG_RTL_8196C) - -#define BSP_IRR2_SETTING ((BSP_NONE<< 28) | \ - (BSP_NONE << 24) | \ - (BSP_NONE<< 20) | \ - (BSP_NONE<< 16) | \ - (BSP_NONE << 12) | \ - (BSP_NONE<< 8) | \ - (BSP_PCM_RS << 4) | \ - (BSP_USB_H_RS << 0) \ -) - -#else - -#define BSP_IRR2_SETTING ((BSP_GDMA_RS<< 28) | \ - (BSP_PCIE2_RS << 24) | \ - (BSP_PCIE_RS<< 20) | \ - (BSP_SECURITY_RS<< 16) | \ - (BSP_PCM_RS << 12) | \ - (BSP_NFBI_RS<< 8) | \ - (BSP_GPIO_EFGH_RS << 4) | \ - (BSP_GPIO_ABCD_RS << 0) \ -) - -#endif - - -#define BSP_IRR3 0xB8003014 - -#if defined(CONFIG_RTL_8196C) - -#define BSP_IRR3_SETTING ((BSP_NONE<< 28) | \ - (BSP_NONE << 24) | \ - (BSP_NONE << 20) | \ - (BSP_NONE<< 16) | \ - (BSP_NONE<< 12) | \ - (BSP_NONE << 8) | \ - (BSP_NONE<< 4) | \ - (BSP_NONE<< 0) \ -) - -#else - -#define BSP_IRR3_SETTING ((BSP_PTM_RS<< 28) | \ - (BSP_LBCTMOs2_RS << 24) | \ - (BSP_LBCTMOs1_RS << 20) | \ - (BSP_PKT_RS<< 16) | \ - (BSP_SPI_RS<< 12) | \ - (BSP_SAR_RS<< 4) | \ - (BSP_DMT_RS<< 0) \ -) - -#endif - -/* - * Timer/Counter - */ -#define BSP_TC_BASE 0xB8003100 -#define BSP_TC0DATA (BSP_TC_BASE + 0x00) -#define BSP_TC1DATA (BSP_TC_BASE + 0x04) -#define BSP_TCD_OFFSET 8 -#define BSP_TC0CN (BSP_TC_BASE + 0x08) -#define BSP_TC1CNT (BSP_TC_BASE + 0x0C) -#define BSP_TCCNR (BSP_TC_BASE + 0x10) -#define BSP_TC0EN (1 << 31) -#define BSP_TC0MODE_TIMER (1 << 30) -#define BSP_TC1EN (1 << 29) -#define BSP_TC1MODE_TIMER (1 << 28) -#define BSP_TCIR (BSP_TC_BASE + 0x14) -#define BSP_TC0IE (1 << 31) -#define BSP_TC1IE (1 << 30) -#define BSP_TC0IP (1 << 29) -#define BSP_TC1IP (1 << 28) -#define BSP_CDBR (BSP_TC_BASE + 0x18) -#define BSP_DIVF_OFFSET 16 -#define BSP_WDTCNR (BSP_TC_BASE + 0x1C) - - -/* - * PCIE Host Controller - */ -#define BSP_PCIE0_H_CFG 0xB8B00000 -#define BSP_PCIE0_H_EXT 0xB8B01000 -#define BSP_PCIE0_H_MDIO (BSP_PCIE0_H_EXT + 0x00) -#define BSP_PCIE0_H_INTSTR (BSP_PCIE0_H_EXT + 0x04) -#define BSP_PCIE0_H_PWRCR (BSP_PCIE0_H_EXT + 0x08) -#define BSP_PCIE0_H_IPCFG (BSP_PCIE0_H_EXT + 0x0C) -#define BSP_PCIE0_H_MISC (BSP_PCIE0_H_EXT + 0x10) -#define BSP_PCIE0_D_CFG0 0xB8B10000 -#define BSP_PCIE0_D_CFG1 0xB8B11000 -#define BSP_PCIE0_D_MSG 0xB8B12000 - -#define BSP_PCIE1_H_CFG 0xB8B20000 -#define BSP_PCIE1_H_EXT 0xB8B21000 -#define BSP_PCIE1_H_MDIO (BSP_PCIE1_H_EXT + 0x00) -#define BSP_PCIE1_H_INTSTR (BSP_PCIE1_H_EXT + 0x04) -#define BSP_PCIE1_H_PWRCR (BSP_PCIE1_H_EXT + 0x08) -#define BSP_PCIE1_H_IPCFG (BSP_PCIE1_H_EXT + 0x0C) -#define BSP_PCIE1_H_MISC (BSP_PCIE1_H_EXT + 0x10) -#define BSP_PCIE1_D_CFG0 0xB8B30000 -#define BSP_PCIE1_D_CFG1 0xB8B31000 -#define BSP_PCIE1_D_MSG 0xB8B32000 - -#define BSP_PCIE0_D_IO 0xB8C00000 -#define BSP_PCIE1_D_IO 0xB8E00000 -#define BSP_PCIE_FUN_OFS 0xC00000 -#define BSP_PCIE0_D_MEM 0xB9000000 -#define BSP_PCIE0_F1_D_MEM (BSP_PCIE0_D_MEM + BSP_PCIE_FUN_OFS) -#define BSP_PCIE1_D_MEM 0xBA000000 -#define BSP_PCIE1_F1_D_MEM (BSP_PCIE1_D_MEM + BSP_PCIE_FUN_OFS) - - - -#define BSP_REVR 0xB8000000 -//becouse of -//drivers/net/wireless/rtl8192cd/8192cd_osdep.c: In function 'rtl8192cd_init_one': -//drivers/net/wireless/rtl8192cd/8192cd_osdep.c:5866:9: error: 'REVR' undeclared -#define REVR 0xB8000000 -#define BSP_RTL8198_REVISION_A 0xC0000000 -#define BSP_RTL8198_REVISION_B 0xC0000001 -#define BSP_RTL8197D 0x8197C000 -#define RTL8196C_REVISION_A 0x80000001 -#define RTL8196C_REVISION_B 0x80000002 - - - -#if defined(CONFIG_RTL_92D_SUPPORT) -#define BSP_CLK_MANAGE 0xb8000010 -#endif - - -#ifdef CONFIG_RTL_USB_IP_HOST_SPEEDUP -#define __IRAM_USB //__attribute__ ((section(".iram-rtkusb"))) -//? here was taftology check orig sources -#endif - - - - - - - - -#endif - diff --git a/target/linux/realtek/files/arch/rlx/bsp/bspcpu.h b/target/linux/realtek/files/arch/rlx/bsp/bspcpu.h deleted file mode 100644 index 2bcef4534..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/bspcpu.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2006, Realtek Semiconductor Corp. - * Copyright (C) 2013, Artur Artamonov (artur@advem.lv) - */ - -#ifndef __LEXRA_BSPCPU_H -#define __LEXRA_BSPCPU_H - -#if defined(CONFIG_RTL_8196C) - -#define cpu_scache_size 0 -#define cpu_dcache_size ( 8 << 10) -#define cpu_icache_size (16 << 10) -#define cpu_scache_line 0 -#define cpu_dcache_line 16 -#define cpu_icache_line 16 -#define cpu_dcache_line_mask 0xF /*cpu_dcache_line-1*/ -#define cpu_icache_line_mask 0xF /*cpu_icache_line-1*/ -#define cpu_tlb_entry 32 -//#define cpu_mem_size (64 << 20) -#define cpu_mem_size (32 << 20) -//#define cpu_mem_size ((7 << 20)-16) //reserve 16 byte for firmware header - -#define cpu_imem_size 0 -#define cpu_dmem_size 0 -#define cpu_smem_size 0 - -#elif defined(CONFIG_RTL_819XD) - -#define cpu_scache_size 0 -#define cpu_dcache_size ( 32 << 10) -#define cpu_icache_size (64 << 10) -#define cpu_scache_line 0 -#define cpu_dcache_line 32 -#define cpu_icache_line 32 -#define cpu_dcache_line_mask 0x1F /*cpu_dcache_line-1*/ -#define cpu_icache_line_mask 0x1F /*cpu_icache_line-1*/ -#define cpu_tlb_entry 32 - -//#define cpu_mem_size (64 << 20) -//#define cpu_mem_size (16 << 20) - -#define cpu_imem_size 0 -#define cpu_dmem_size 0 -#define cpu_smem_size 0 - -#endif - -#endif diff --git a/target/linux/realtek/files/arch/rlx/bsp/bspinit.h b/target/linux/realtek/files/arch/rlx/bsp/bspinit.h deleted file mode 100644 index e7dddccb4..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/bspinit.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Realtek Semiconductor Corp. - * - * bspinit.h: - * - * Tony Wu (tonywu@realtek.com.tw) - * Dec. 7, 2007 - */ -#ifndef __BSPINIT_H_ -#define __BSPINIT_H_ - -.macro kernel_entry_setup -.endm - -.macro smp_slave_setup -.endm - -#endif diff --git a/target/linux/realtek/files/arch/rlx/bsp/dev_usb.c b/target/linux/realtek/files/arch/rlx/bsp/dev_usb.c deleted file mode 100644 index 10aa2e4d3..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/dev_usb.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Realte rtl819x USB host device support - * - * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> - -#include "bspchip.h" -#include "dev_usb.h" - -/* - * OHCI (USB full speed host controller) - */ -static struct resource rtl819x_ohci_resources[] = { - [0] = { - .start = PADDR(OHCI_RTL819x_USB_BASE), - .end = PADDR(OHCI_RTL819x_USB_BASE) + OHCI_RTL819x_USB_REG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = RTL819x_USB_IRQ, - .end = RTL819x_USB_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 rtl819x_ohci_dmamask = RTL819x_DMA_MASK; -static struct platform_device rtl819x_ohci_device = { - .name = "rtl819x-ohci", - .id = -1, - .resource = rtl819x_ohci_resources, - .num_resources = ARRAY_SIZE(rtl819x_ohci_resources), - .dev = { - .dma_mask = &rtl819x_ohci_dmamask, - .coherent_dma_mask = RTL819x_DMA_MASK, - }, -}; - -/* - * EHCI (USB high/full speed host controller) - */ -static struct resource rtl819x_ehci_resources[] = { - [0] = { - .start = PADDR(EHCI_RTL819x_USB_BASE), - .end = PADDR(EHCI_RTL819x_USB_BASE) + EHCI_RTL819x_USB_REG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = RTL819x_USB_IRQ, - .end = RTL819x_USB_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 rtl819x_ehci_dmamask = RTL819x_DMA_MASK; - -struct rtl819x_ehci_platform_data { - u8 is_rtl819x; -}; - -static struct rtl819x_ehci_platform_data rtl819x_ehci_data; - -static struct platform_device rtl819x_ehci_device = { - .name = "rtl819x-ehci", - .id = -1, - .resource = rtl819x_ehci_resources, - .num_resources = ARRAY_SIZE(rtl819x_ehci_resources), - .dev = { - .dma_mask = &rtl819x_ehci_dmamask, - .coherent_dma_mask = RTL819x_DMA_MASK, - .platform_data = &rtl819x_ehci_data, - }, -}; - -void SetUSBPhy(unsigned char reg, unsigned char val) -{ - - #define USB2_PHY_DELAY {mdelay(5);} - - //8196C demo board: 0xE0:99, 0xE1:A8, 0xE2:98, 0xE3:C1, 0xE5:91, - -#if !CONFIG_RTL_819XD //8198 - REG32(0xb8000034) = (0x1f00 | val); USB2_PHY_DELAY; -#else //8196D - #define SYS_USB_SIE 0xb8000034 - #define SYS_USB_PHY 0xb8000090 - int oneportsel=(REG32(SYS_USB_SIE) & (1<<18))>>18; - - unsigned int tmp = REG32(SYS_USB_PHY); //8672 only - tmp = tmp & ~((0xff<<11)|(0xff<<0)); - - - if(oneportsel==0) - { REG32(SYS_USB_PHY) = (val << 0) | tmp; //phy 0 - } - else - { REG32(SYS_USB_PHY) = (val << 11) | tmp; //phy1 - } - - USB2_PHY_DELAY; -#endif - //printk("0xb8000034=%08x\n", REG32(0xb8000034)); - - unsigned char reg_h=(reg &0xf0)>>4; - unsigned char reg_l=(reg &0x0f); - - mdelay(100); - REG32(0xb80210A4) = (0x00300000 | (reg_l<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00200000 | (reg_l<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00300000 | (reg_l<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00300000 | (reg_h<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00200000 | (reg_h<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00300000 | (reg_h<<16)); USB2_PHY_DELAY; -} - -unsigned char GetUSBPhy(unsigned char reg) -{ - #define USB2_PHY_DELAY {mdelay(5);} - - unsigned char reg_h=((reg &0xf0)>>4)-2; - unsigned char reg_l=(reg &0x0f); - - REG32(0xb80210A4) = (0x00300000 | (reg_l<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00200000 | (reg_l<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00300000 | (reg_l<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00300000 | (reg_h<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00200000 | (reg_h<<16)); USB2_PHY_DELAY; - REG32(0xb80210A4) = (0x00300000 | (reg_h<<16)); USB2_PHY_DELAY; - - unsigned char val; - val=REG32(0xb80210A4)>>24; - //printk("reg=%x val=%x\n",reg, val); - return val; -} - -static void synopsys_usb_patch(void) -{ - -#define USB2_PHY_DELAY {int i=100; while(i>0) {i--;}} - /* Patch: for USB 2.0 PHY */ -#if !defined(CONFIG_RTL_8196C) - /* For Port-0 */ - REG32(0xb8003314) = 0x0000000E; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00340000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00240000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00340000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x003E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x002E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x003E0000; USB2_PHY_DELAY; - REG32(0xb8003314) = 0x000000D8; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00360000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00260000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00360000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x003E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x002E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x003E0000; USB2_PHY_DELAY; - - /* For Port-1 */ - REG32(0xb8003314) = 0x000E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00540000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00440000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00540000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x005E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x004E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x005E0000; USB2_PHY_DELAY; - REG32(0xb8003314) = 0x00D80000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00560000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00460000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x00560000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x005E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x004E0000; USB2_PHY_DELAY; - REG32(0xb80210A4) = 0x005E0000; USB2_PHY_DELAY; - - printk("USB 2.0 Phy Patch(D): &0xb80210A4 = %08x\n", REG32(0xb80210A4)); /* A85E0000 */ - -#elif defined(CONFIG_RTL_8196C) - - //disable Host chirp J-K - SetUSBPhy(0xf4,0xe3); GetUSBPhy(0xf4); - //8196C demo board: 0xE0:99, 0xE1:A8, 0xE2:98, 0xE3:C1, 0xE5:91, - SetUSBPhy(0xe0,0x99); if(GetUSBPhy(0xe0)!=0x99) printk("reg 0xe0 not correct\n"); - SetUSBPhy(0xe1,0xa8); if(GetUSBPhy(0xe1)!=0xa8) printk("reg 0xe1 not correct\n"); - SetUSBPhy(0xe2,0x98); if(GetUSBPhy(0xe2)!=0x98) printk("reg 0xe2 not correct\n"); - SetUSBPhy(0xe3,0xc1); if(GetUSBPhy(0xe3)!=0xc1) printk("reg 0xe3 not correct\n"); - SetUSBPhy(0xe5,0x91); if(GetUSBPhy(0xe5)!=0x91) printk("reg 0xe5 not correct\n"); - - //test packet. - /* - REG32(0xb8021054)=0x85100000; - REG32(0xb8021010)=0x08000100; - REG32(0xb8021054)=0x85180400; - */ - printk("USB 2.0 PHY Patch Done.\n"); - -#else - printk("========================== NO PATCH USB 2.0 PHY =====================\n"); -#endif - return; -} -//-------------------------------------------- -void EnableUSBPHY(int portnum) -{ - if(portnum==0) - { - //phy0 - REG32(0xb8000090) |= (1<<8); //USBPHY_EN=1 - REG32(0xb8000090) |= (1<<9); //usbphy_reset=1, active high - REG32(0xb8000090) &= ~(1<<9); //usbphy_reset=0, active high - REG32(0xb8000090) |= (1<<10); //active_usbphyt=1 - } - else - { - //phy1 - REG32(0xb8000090) |= (1<<19); //USBPHY_EN=1 - REG32(0xb8000090) |= (1<<20); //usbphy_reset=1, active high - REG32(0xb8000090) &= ~(1<<20); //usbphy_reset=0, active high - REG32(0xb8000090) |= (1<<21); //active_usbphyt=1 - } -} - -static void __init rtl819x_usb_setup(void) -{ - -#if !defined(CONFIG_RTL_819XD) //8198 - REG32(0xb8000010)=REG32(0xb8000010)|(1<<17); -#else //8196D - - //one port sel - //is 0: phy#1 connect OTG mac, EHCI is in phy0 - //is 1: phy#1 connect EHCI mac - -#ifdef CONFIG_RTL_USB_OTG - int oneportsel=0; - REG32(0xb8000034) &= ~(1<<18); //one port sel=0 -#else -#if 1 //software force - int oneportsel=1; - if(oneportsel==1) - { REG32(0xb8000034) |= (1<<18); //one port sel=1 - } - else - { REG32(0xb8000034) &= ~(1<<18); //one port sel=0 - } -#else //read-back decide - int oneportsel= (REG32(0xb8000034) & (1<<18))>>18; - printk("EHCI: one_port_host_sel=%d, EHCI in Port %s\n", oneportsel, (oneportsel==0) ? "0": "1"); -#endif -#endif - //sie - REG32(0xb8000034) |= (1<<11); //s_utmi_suspend0=1 - REG32(0xb8000034) |= (1<<12); //en_usbhost=1 - REG32(0xb8000034) |= (1<<17); //enable pgbndry_disable=1 - - if(oneportsel==1) - { - EnableUSBPHY(1); - } - else - { - //phy0, phy1 -#ifdef CONFIG_RTL_OTGCTRL - extern unsigned int TurnOn_OTGCtrl_Interrupt(unsigned int); - unsigned int old= TurnOn_OTGCtrl_Interrupt(0); -#endif - EnableUSBPHY(0); - EnableUSBPHY(1); -#ifdef CONFIG_RTL_OTGCTRL - TurnOn_OTGCtrl_Interrupt(old); -#endif - } - - //ip clock mgr - REG32(0xb8000010) |= (1<<12)|(1<<13)|(1<<19)|(1<<20); //enable lx1, lx2 - REG32(0xb8000010) |= (1<<21); //enable host ip - - mdelay(100); - //printk("b8021000=%x\n", REG32(0xb8021000) ); - //printk("b8021054=%x\n", REG32(0xb8021054) ); -#endif - - /*register platform device*/ - platform_device_register(&rtl819x_ehci_device); - platform_device_register(&rtl819x_ohci_device); - -#if defined(CONFIG_RTL_8196C) - synopsys_usb_patch(); -#endif - - -#if 1 //wei add - //dump - int i; - for(i=0xe0;i<=0xe7; i++) - printk("reg %x=%x\n", i,GetUSBPhy(i) ); - for(i=0xf0;i<=0xf6; i++) - printk("reg %x=%x\n", i,GetUSBPhy(i) ); -#endif - - return 0; -} - -void __init rtl819x_add_device_usb(void) -{ - rtl819x_usb_setup(); -} - diff --git a/target/linux/realtek/files/arch/rlx/bsp/dev_usb.h b/target/linux/realtek/files/arch/rlx/bsp/dev_usb.h deleted file mode 100644 index 22ad6cf1c..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/dev_usb.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright (c) 2005 freescale semiconductor - * Copyright (c) 2005 MontaVista Software - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include "bspchip.h" -#ifndef _USB_RTL819x_H -#define _USB_RTL819x_H -#define PADDR(addr) ((addr) & 0x1FFFFFFF) - -/* USB 2.0 Host - * OHCI: 0xB802_0000 ~ 0xB802_0FFF (len = 0x1000) - * EHCI: 0xB802_1000 ~ 0xB802_FFFF (len = 0xF000) - */ - -//#define REG32(reg) (*((volatile unsigned int *)(reg))) -#define OHCI_RTL819x_USB_BASE 0xb8020000 -#define OHCI_RTL819x_USB_REG_SIZE 0x1000 -//#define OHCI_RTL819x_USB_REG_SIZE sizeof(struct ohci_regs) -/* offsets for the non-ehci registers in the FSL SOC USB controller */ -#define EHCI_RTL819x_USB_BASE 0xb8021000 -#define EHCI_RTL819x_USB_REG_SIZE 0xf000 -//#define EHCI_RTL819x_USB_REG_SIZE sizeof(struct ehci_regs) -#define RTL819x_USB_IRQ BSP_USB_IRQ -#define RTL819x_DMA_MASK 0xffffffffUL -#endif /* _USB_RTL819x_H_ */ diff --git a/target/linux/realtek/files/arch/rlx/bsp/irq.c b/target/linux/realtek/files/arch/rlx/bsp/irq.c deleted file mode 100644 index 489a72386..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/irq.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2013, Artur Artamonov <artur@advem.lv> - */ - -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel_stat.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/timex.h> -#include <linux/slab.h> -#include <linux/random.h> -#include <linux/irq.h> - -#include <asm/bitops.h> -#include <asm/bootinfo.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/irq_cpu.h> -#include <asm/irq_vec.h> -#include <asm/system.h> - -#include <asm/rlxregs.h> -#include <asm/rlxbsp.h> -#include <net/rtl/rtl_types.h> - -#include "bspchip.h" -#include "rlxhack.h" - -static struct irqaction irq_cascade = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; - -static void bsp_ictl_irq_mask(unsigned int irq) -{ - REG32(BSP_GIMR) &= ~(1 << (irq - BSP_IRQ_ICTL_BASE)); -} - -static void bsp_ictl_irq_unmask(unsigned int irq) -{ - REG32(BSP_GIMR) |= (1 << (irq - BSP_IRQ_ICTL_BASE)); -} - -static struct irq_chip bsp_ictl_irq = { - .typename = "ICTL", - .ack = bsp_ictl_irq_mask, - .mask = bsp_ictl_irq_mask, - .mask_ack = bsp_ictl_irq_mask, - .unmask = bsp_ictl_irq_unmask, -}; - -static void bsp_ictl_irq_dispatch(void) -{ - volatile unsigned int pending; - - pending = REG32(BSP_GIMR) & REG32(BSP_GISR); - - if (pending & BSP_UART0_IP) - do_IRQ(BSP_UART0_IRQ); -#if defined(CONFIG_RTL_819XD) - else if (pending & BSP_UART1_IP) - do_IRQ(BSP_UART1_IRQ); -#endif - else if (pending & BSP_TC1_IP) - do_IRQ(BSP_TC1_IRQ); -#if defined(CONFIG_RTL_819XD) - #if CONFIG_RTL_USB_OTG //wei add - #if (BSP_OTG_IRQ >= BSP_IRQ_ICTL_BASE) // double check otg is ictl not lopi - else if (pending & BSP_OTG_IP) - do_IRQ(BSP_OTG_IRQ); - #endif - #endif - #if defined( CONFIG_RTK_VOIP ) || defined(CONFIG_PCIE_POWER_SAVING) - else if (pending & BSP_GPIO_ABCD_IP) - do_IRQ(BSP_GPIO_ABCD_IRQ); - else if (pending & BSP_GPIO_EFGH_IP) - do_IRQ(BSP_GPIO_EFGH_IRQ); - - else if (pending & BSP_GPIO_ABCD_IP) - do_IRQ(BSP_GPIO_ABCD_IRQ); - #endif -#endif - else { - REG32(BSP_GIMR) &= (~pending); -#if defined(CONFIG_RTL_819XD) - REG32(BSP_GISR) = REG32(BSP_GISR); -#endif - printk("Unknown Interrupt0:%x\n", pending); - #if defined(CONFIG_RTK_VOIP) || defined(CONFIG_RTL_819X) - spurious_interrupt(SPURIOS_INT_CASCADE); - #else - spurious_interrupt(); - #endif - } -} - -void bsp_irq_dispatch(void) -{ - volatile unsigned int pending; - pending = read_c0_cause() & read_c0_status(); - - if (pending & CAUSEF_IP2) - bsp_ictl_irq_dispatch(); - else if (pending & CAUSEF_IP0) - do_IRQ(0); - else if (pending & CAUSEF_IP1) - do_IRQ(1); - else { -#if defined(CONFIG_RTK_VOIP) || defined(CONFIG_RTL_819X) - spurious_interrupt(SPURIOS_INT_CPU); -#else - spurious_interrupt(); -#endif - } -} - -static void __init bsp_ictl_irq_init(unsigned int irq_base) -{ - int i; - - for (i=0; i < BSP_IRQ_ICTL_NUM; i++) - set_irq_chip_and_handler(irq_base + i, &bsp_ictl_irq, handle_level_irq); - - setup_irq(BSP_ICTL_IRQ, &irq_cascade); -} - -#ifdef CONFIG_RTL_8198_NFBI_BOARD -extern void (*flush_icache_range)(unsigned long start, unsigned long end); - -int get_dram_type(void) -{ - // read hw_strap register - if (REG32(0xb8000008) & 0x2) //bit 1 - return 1; //DDR - else - return 0; //SDR -} - -void setup_reboot_addr(unsigned long addr) -{ - unsigned int dramcode[20]={ - 0x3c080f0a, // lui t0,0f0a - 0x3508dfff, // ori t0,t0,0xdfff - 0x3c09b800, // lui t1,0xb800 - 0x35290048, // ori t1,t1,0x0048 - 0xad280000, // sw t0,0(t1) - - 0x3c0801FF, // lui t0,01FF - 0x3508FF8A, // ori t0,t0,0xFF8A - 0x3c09b800, // lui t1,0xb800 - 0x35290010, // ori t1,t1,0x0010 - 0xad280000, // sw t0,0(t1) - - 0x3c086cea, // lui t0,0x6cea - 0x35080a80, // ori t0,t0,0x0a80 - 0x3c09b800, // lui t1,0xb800 - 0x35291008, // ori t1,t1,0x1008 - 0xad280000, // sw t0,0(t1) - - 0x3c085208, // lui t0,0x5208 //8MB DRAM - 0x35080000, // ori t0,t0,0x0000 - 0x3c09b800, // lui t1,0xb800 - 0x35291004, // ori t1,t1,0x1004 - 0xad280000, // sw t0,0(t1) - }; - unsigned int jmpcode[4]={ - 0x3c1aa070, // lui k0,0xa070 - 0x375a0000, // ori k0,k0,0x0000 - 0x03400008, // jr k0 - 0x0 // nop - }; - int i, offset; - - // setting DCR and DTR register - dramcode[10]=(dramcode[10] &0xffff0000) | 0xffff; - dramcode[11]=(dramcode[11] &0xffff0000) | 0x05c0; - //if (check_ddr_tmp_file()) - if (get_dram_type()) { //DDR - dramcode[15]=(dramcode[15] &0xffff0000) | 0x5448; //DDR, 32M - //8198:1.set bigger current for DDR - dramcode[0]=(dramcode[0] &0xffff0000) | 0x0b0a; - // TX RX delay - dramcode[5]=(dramcode[5] &0xffff0000) | 0x01ff; - dramcode[6]=(dramcode[6] &0xffff0000) | 0xfc70; - } - else { - dramcode[15]=(dramcode[15] &0xffff0000) | 0x5208; //SDR, 8M - //8198:1.set bigger current for DDR - dramcode[0]=(dramcode[0] &0xffff0000) | 0x0f0a; - // TX RX delay - dramcode[5]=(dramcode[5] &0xffff0000) | 0x01ff; - dramcode[6]=(dramcode[6] &0xffff0000) | 0xff8a; - } - dramcode[16]=(dramcode[16] &0xffff0000) | 0x0000; - - for (i=0, offset=0; i<20; i++, offset++) - *(volatile u32 *)(KSEG0 + 0x8000 + offset*4) = dramcode[i]; - - // set jump command - jmpcode[0] = (jmpcode[0]&0xffff0000) | ((addr>>16)&0xffff); - jmpcode[1] = (jmpcode[1]&0xffff0000) | (addr&0xffff); - - for (i=0; i<4; i++, offset++) - *(volatile u32 *)(KSEG0 + 0x8000 + offset*4) = jmpcode[i]; - - flush_icache_range(KSEG0+0x8000, KSEG0 + offset*4); -} -#endif //CONFIG_RTL_8198_NFBI_BOARD - - -void __init bsp_irq_init(void) -{ - //unsigned int status; - //volatile unsigned int status; - /* disable ict interrupt */ - REG32(BSP_GIMR) = 0; - - /* initialize IRQ action handlers */ - rlx_cpu_irq_init(BSP_IRQ_CPU_BASE); - rlx_vec_irq_init(BSP_IRQ_LOPI_BASE); - bsp_ictl_irq_init(BSP_IRQ_ICTL_BASE); - - /* Set IRR */ - REG32(BSP_IRR0) = BSP_IRR0_SETTING; - REG32(BSP_IRR1) = BSP_IRR1_SETTING; - REG32(BSP_IRR2) = BSP_IRR2_SETTING; - REG32(BSP_IRR3) = BSP_IRR3_SETTING; - - //status = read_c0_status(); - //status = (status&(~ST0_IM))|(CAUSEF_IP2|CAUSEF_IP3|CAUSEF_IP4|CAUSEF_IP5|CAUSEF_IP6); - //write_c0_status(status); -#ifdef CONFIG_USB - REG32(BSP_GIMR) |= BSP_USB_H_IE; -#endif - -#ifdef CONFIG_DWC_OTG //wei add - REG32(BSP_GIMR) |= BSP_OTG_IE; //mac -#endif -} - -#if defined(CONFIG_ARCH_SUSPEND_POSSIBLE)//michaelxxx - #define CONFIG_RTL819X_SUSPEND_CHECK_INTERRUPT - #ifdef CONFIG_RTL819X_SUSPEND_CHECK_INTERRUPT - #include <linux/proc_fs.h> - #include <linux/kernel_stat.h> - #include <asm/uaccess.h> - //#define INT_HIGH_WATER_MARK 1850 //for window size = 1, based on LAN->WAN test result - //#define INT_LOW_WATER_MARK 1150 - //#define INT_HIGH_WATER_MARK 9190 //for window size = 5, based on LAN->WAN test result - //#define INT_LOW_WATER_MARK 5500 - #define INT_HIGH_WATER_MARK 3200 //for window size = 5, based on WLAN->WAN test result - #define INT_LOW_WATER_MARK 2200 - #define INT_WINDOW_SIZE_MAX 10 - static int suspend_check_enable = 1; - static int suspend_check_high_water_mark = INT_HIGH_WATER_MARK; - static int suspend_check_low_water_mark = INT_LOW_WATER_MARK; - static int suspend_check_win_size = 5; - static struct timer_list suspend_check_timer; - static int index=0, prev_count=0; - static int eth_int_count[INT_WINDOW_SIZE_MAX]; - static int wlan_int_count[INT_WINDOW_SIZE_MAX]; - int cpu_can_suspend = 1; - int cpu_can_suspend_check_init = 0; - - static int read_proc_suspend_check(char *page, char **start, off_t off, - int count, int *eof, void *data) - { - int len; - - len = sprintf(page, "enable=%d, winsize=%d(%d), high=%d, low=%d, suspend=%d, prev_count=%d\n", - suspend_check_enable, suspend_check_win_size, INT_WINDOW_SIZE_MAX, - suspend_check_high_water_mark, suspend_check_low_water_mark, cpu_can_suspend, prev_count); - - if (len <= off+count) - *eof = 1; - *start = page + off; - len -= off; - if (len > count) - len = count; - if (len < 0) - len = 0; - return len; - } - - static int write_proc_suspend_check(struct file *file, const char *buffer, - unsigned long count, void *data) - { - char tmp[128]; - - if (buffer && !copy_from_user(tmp, buffer, 128)) { - sscanf(tmp, "%d %d %d %d %d", - &suspend_check_enable, &suspend_check_win_size, - &suspend_check_high_water_mark, &suspend_check_low_water_mark, &cpu_can_suspend); - if (suspend_check_win_size >= INT_WINDOW_SIZE_MAX) - suspend_check_win_size = INT_WINDOW_SIZE_MAX - 1; - if (suspend_check_enable) { - mod_timer(&suspend_check_timer, jiffies + 100); - } - else { - del_timer(&suspend_check_timer); - } - } - return count; - } - - static void suspend_check_timer_fn(unsigned long arg) - { - int count, j; - - index++; - if (INT_WINDOW_SIZE_MAX <= index) - index = 0; - eth_int_count[index] = kstat_irqs(BSP_SWCORE_IRQ); - wlan_int_count[index] = kstat_irqs(BSP_PCIE_IRQ); - j = index - suspend_check_win_size; - if (j < 0) - j += INT_WINDOW_SIZE_MAX; - count = (eth_int_count[index] - eth_int_count[j]) + - (wlan_int_count[index]- wlan_int_count[j]); //unit: number of interrupt occurred - - prev_count = count; - - if (cpu_can_suspend) { - if (count > suspend_check_high_water_mark) { - cpu_can_suspend = 0; - //printk("\n<<<RTL8196C LEAVE SLEEP>>>\n"); /* for Debug Only*/ - } - } - else { - if (count < suspend_check_low_water_mark) { - cpu_can_suspend = 1; - //printk("\n<<<RTL8196C ENTER SLEEP>>>\n"); /* for Debug Only*/ - } - } -#if 0 /* for Debug Only*/ - printk("###index=%d, count=%d (%d+%d) suspend=%d###\n",index, count, - eth_int_count[index] - eth_int_count[j]), - (wlan_int_count[index]- wlan_int_count[j]), - cpu_can_suspend); -#endif - mod_timer(&suspend_check_timer, jiffies + 100); - } - - void suspend_check_interrupt_init(void) - { - struct proc_dir_entry *res; - int i; - - res = create_proc_entry("suspend_check", 0, NULL); - if (res) { - res->read_proc = read_proc_suspend_check; - res->write_proc = write_proc_suspend_check; - } - else { - printk("unable to create /proc/suspend_check\n"); - } - - for (i=0; i<INT_WINDOW_SIZE_MAX; i++) { - wlan_int_count[i] = 0; - eth_int_count[i] = 0; - } - init_timer(&suspend_check_timer); - suspend_check_timer.data = 0; - suspend_check_timer.function = suspend_check_timer_fn; - suspend_check_timer.expires = jiffies + 100; /* in jiffies */ - add_timer(&suspend_check_timer); - } -#endif // CONFIG_RTL819X_SUSPEND_CHECK_INTERRUPT -#endif //CONFIG_ARCH_SUSPEND_POSSIBLE - diff --git a/target/linux/realtek/files/arch/rlx/bsp/kgdb.c b/target/linux/realtek/files/arch/rlx/bsp/kgdb.c deleted file mode 100644 index 93960b21f..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/kgdb.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Realtek semiconductor Corp. - * - * arch/rlx/rlxocp/kgdb.c: - * Kernel debugging on the rtl5739. - * - * Tony Wu (tonywu@realtek.com.tw) - * Dec. 7, 2007 - */ -#include <asm/system.h> -#include <asm/tx3912.h> - -static int remoteDebugInitialized = 0; - -void debugInit(void) -{ -/* - * If low-level debugging (before GDB or console operational) is - * configured, then we do not need to re-initialize the UART. - */ -#ifndef CONFIG_DEBUG_LL -// earlyInitUartPR31700(); -#endif -} - -char getDebugChar(void) -{ - char buf; - unsigned long int2, flags; - - if (!remoteDebugInitialized) { - debugInit(); - remoteDebugInitialized = 1; - } - - save_and_cli(flags); - - int2 = IntEnable2; - - IntEnable2 = 0; - - while (!(UartA_Ctrl1 & UART_RX_HOLD_FULL)); - - buf = UartA_Data; - - IntEnable2 = int2; - - restore_flags(flags); - - return buf; -} - -int putDebugChar(char c) -{ - int i; - unsigned long int2; - - if (!remoteDebugInitialized) { - debugInit(); - remoteDebugInitialized = 1; - } - - int2 = IntEnable2; - - IntEnable2 &= - ~(INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY); - - for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < 10000); i++); - - IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY; - - UartA_Data = c; - - for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < 10000); i++); - - IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY; - - IntEnable2 = int2; - - return 1; -} diff --git a/target/linux/realtek/files/arch/rlx/bsp/pci.c b/target/linux/realtek/files/arch/rlx/bsp/pci.c deleted file mode 100644 index 147f743cb..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/pci.c +++ /dev/null @@ -1,1265 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * RTL819XX PCIE Host Controller Glue Driver - * Copyright (C) 2006, Realtek Semiconductor Corp. - * Author: (ghhuang@realtek.com.tw) - * - * Copyright (C) 2013, Artur Artamonov (artur@advem.lv) - * - * Notes: - * - Two host controllers available. - * - Each host direcly connects to one device - * - Supports PCI devices through PCIE-to-PCI bridges - * - If no PCI devices are connected to RC. Timeout monitor shall be - * enabled to prevent bus hanging. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -//#include <asm/rlxregs.h> -#include "bspchip.h" - -#define PCI_8BIT_ACCESS 1 -#define PCI_16BIT_ACCESS 2 -#define PCI_32BIT_ACCESS 4 -#define PCI_ACCESS_READ 8 -#define PCI_ACCESS_WRITE 16 - -#define MAX_NUM_DEV 4 - -#define DEBUG_PRINTK 0 - -#define CLK_MANAGE 0xb8000010 -#define SYS_PCIE_PHY0 (0xb8000000 +0x50) -#define SYS_PCIE_PHY1 (0xb8000000 +0x54) -#define PCIE_PHY0 0xb8b01008 -#define PCIE_PHY1 0xb8b21008 -//best define ever -#define PIN_208 1 - -#define MAX_PAYLOAD_SIZE_128B 0 - -static int pci0_bus_number = 0xff; -static int pci1_bus_number = 0xff; - - - -static struct resource rtl8196c_pci0_io_resource = { - .name = "RTL8196C PCI0 IO", - .flags = IORESOURCE_IO, - .start = PADDR(BSP_PCIE0_D_IO), - .end = PADDR(BSP_PCIE0_D_IO + 0x1FFFFF) -}; - -static struct resource rtl8196c_pci0_mem_resource = { - .name = "RTL8196C PCI0 MEM", - .flags = IORESOURCE_MEM, - .start = PADDR(BSP_PCIE0_D_MEM), - .end = PADDR(BSP_PCIE0_D_MEM + 0xFFFFFF) -}; - -static struct resource rtl8196d_pci0_io_resource = { - .name = "RTL8196D PCI0 IO", - .flags = IORESOURCE_IO, - .start = PADDR(BSP_PCIE0_D_IO), - .end = PADDR(BSP_PCIE0_D_IO + 0x1FFFFF) -}; - -static struct resource rtl8196d_pci0_mem_resource = { - .name = "RTL8196D PCI0 MEM", - .flags = IORESOURCE_MEM, - .start = PADDR(BSP_PCIE0_D_MEM), - .end = PADDR(BSP_PCIE0_D_MEM + 0xFFFFFF) -}; - -static struct resource rtl8196b_pci1_io_resource = { - .name = "RTL8196B PCI1 IO", - .flags = IORESOURCE_IO, - .start = PADDR(BSP_PCIE1_D_IO), - .end = PADDR(BSP_PCIE1_D_IO + 0x1FFFFF) -}; - -static struct resource rtl8196b_pci1_mem_resource = { - .name = "RTL8196B PCI1 MEM", - .flags = IORESOURCE_MEM, - .start = PADDR(BSP_PCIE1_D_MEM), - .end = PADDR(BSP_PCIE1_D_MEM + 0xFFFFFF) -}; - - -#if defined(CONFIG_RTL_8196C) -static struct resource rtl8196b_pci0_io_resource = resource rtl8196c_pci0_io_resource; -static struct resource rtl8196b_pci0_mem_resource = resource rtl8196c_pci0_mem_resource; -#elif defined(CONFIG_RTL_819XD) -static struct resource rtl8196b_pci0_io_resource = resource rtl8196d_pci0_io_resource; -static struct resource rtl8196b_pci0_mem_resource = resource rtl8196d_pci0_mem_resource; -#endif - -//HOST PCIE -#define PCIE0_RC_EXT_BASE (0xb8b01000) -#define PCIE1_RC_EXT_BASE (0xb8b21000) - -//RC Extended register -#define PCIE0_MDIO (PCIE0_RC_EXT_BASE+0x00) -#define PCIE1_MDIO (PCIE1_RC_EXT_BASE+0x00) - -//MDIO -#define PCIE_MDIO_DATA_OFFSET (16) -#define PCIE_MDIO_DATA_MASK (0xffff <<PCIE_MDIO_DATA_OFFSET) -#define PCIE_MDIO_REG_OFFSET (8) -#define PCIE_MDIO_RDWR_OFFSET (0) - -int at2_mode=0; - -//------------------------------------------------------------------------ -unsigned int HostPCIe_SetPhyMdioRead(unsigned int portnum, unsigned int regaddr) -{ - unsigned int mdioaddr=PCIE0_MDIO; -/* - if(portnum==0) mdioaddr=PCIE0_MDIO; - else if(portnum==1) mdioaddr=PCIE1_MDIO; - else return 0; -*/ - REG32(mdioaddr)= ((regaddr&0x1f)<<PCIE_MDIO_REG_OFFSET) | (0<<PCIE_MDIO_RDWR_OFFSET); - //delay - volatile int i; - for(i=0;i<5555;i++) ; - - int val; - val=REG32(mdioaddr)& (0xffff <<PCIE_MDIO_DATA_OFFSET) ; - return ((val>>PCIE_MDIO_DATA_OFFSET)&0xffff); - -} - - -void HostPCIe_SetPhyMdioWrite(unsigned int portnum, unsigned int regaddr, unsigned short val) -{ - unsigned int mdioaddr; - - if(portnum==0) mdioaddr=PCIE0_MDIO; - else if(portnum==1) mdioaddr=PCIE1_MDIO; - else return 0; - - REG32(mdioaddr)= ( (regaddr&0x1f)<<PCIE_MDIO_REG_OFFSET) | ((val&0xffff)<<PCIE_MDIO_DATA_OFFSET) | (1<<PCIE_MDIO_RDWR_OFFSET) ; - //delay - volatile int i; - for(i=0;i<5555;i++) ; -} - -//---------------------------------------------------------------------------- - -void PCIE_MDIO_Reset(unsigned int portnum) -{ - #define SYS_PCIE_PHY0 (0xb8000000 +0x50) - #define SYS_PCIE_PHY1 (0xb8000000 +0x54) - unsigned int sys_pcie_phy; - - if (portnum==0) - sys_pcie_phy=SYS_PCIE_PHY0; - else if (portnum==1) - sys_pcie_phy=SYS_PCIE_PHY1; - else - return; - - // 3.MDIO Reset - REG32(sys_pcie_phy) = (1<<3) |(0<<1) | (0<<0); //mdio reset=0, - REG32(sys_pcie_phy) = (1<<3) |(0<<1) | (1<<0); //mdio reset=1, - REG32(sys_pcie_phy) = (1<<3) |(1<<1) | (1<<0); //bit1 load_done=1 -} -//------------------------------------------------------------------------ -void PCIE_PHY_Reset(unsigned int portnum) -{ - #define PCIE_PHY0 0xb8b01008 - #define PCIE_PHY1 0xb8b21008 - unsigned int pcie_phy; - - if(portnum==0) pcie_phy=PCIE_PHY0; - else if(portnum==1) pcie_phy=PCIE_PHY1; - else return; - - //4. PCIE PHY Reset - REG32(pcie_phy) = 0x01; //bit7:PHY reset=0 bit0: Enable LTSSM=1 - REG32(pcie_phy) = 0x81; //bit7: PHY reset=1 bit0: Enable LTSSM=1 - -} -//------------------------------------------------------------------------ -int PCIE_Check_Link(unsigned int portnum) -{ - unsigned int dbgaddr; - unsigned int cfgaddr; - - if(portnum==0) dbgaddr=0xb8b00728; - else if(portnum==1) dbgaddr=0xb8b20728; - else return; - - //wait for LinkUP -#ifdef CONFIG_RTK_VOIP - // accelerate when no pcie card - int i=3; -#else - int i=20; -#endif - while(--i) - { - if( (REG32(dbgaddr)&0x1f)==0x11) - break; - mdelay(300); - - } - if(i==0) - { - printk("i=%x Cannot LinkUP \n",i); - return 0; - } - else - { - printk("\nLink-UP OK\n"); - if(portnum==0) - cfgaddr=0xb8b10000; - else if(portnum==1) - cfgaddr=0xb8b30000; - - - REG32(cfgaddr+0x04)=0x00100007; - - printk("Find Port=%x Device:Vender ID=%x\n", portnum, REG32(cfgaddr) ); - REG32(cfgaddr); - mdelay(1); - - #if defined(CONFIG_RTL_819XD) - if (portnum == 0) - REG32(BSP_GIMR) |= BSP_PCIE_IE; - else - REG32(BSP_GIMR) |= BSP_PCIE2_IE; - #endif - } - return 1; -} -//------------------------------------------------------------------------ -/* -void PCIE_Device_PERST(void) -{ - REG32(CLK_MANAGE) &= ~(1<<12); //perst=0 off. - mdelay(500); //PCIE standadrd: poweron: 100us, after poweron: 100ms - mdelay(500); - REG32(CLK_MANAGE) |= (1<<12); //PERST=1 - mdelay(500); -} -*/ - -static void PCIE_Device_PERST(int portnum) -{ - #define CLK_MANAGE 0xb8000010 - #define GPIO_BASE 0xB8003500 - #define PEFGHCNR_REG (0x01C + GPIO_BASE) /* Port EFGH control */ - #define PEFGHPTYPE_REG (0x020 + GPIO_BASE) /* Port EFGH type */ - #define PEFGHDIR_REG (0x024 + GPIO_BASE) /* Port EFGH direction */ - #define PEFGHDAT_REG (0x028 + GPIO_BASE) /* Port EFGH data */ - if (portnum==0) - { - REG32(CLK_MANAGE) &= ~(1<<26); //perst=0 off. - mdelay(500); //PCIE standadrd: poweron: 100us, after poweron: 100ms - mdelay(500); - REG32(CLK_MANAGE) |= (1<<26); //PERST=1 - } - else if (portnum==1) - { - /* PCIE Device Reset - * The pcei1 slot reset register depends on the hw - */ -#if 1//defined(CONFIG_RTL_DUAL_PCIESLOT_BIWLAN) || (RTL_USED_PCIE_SLOT==1) || defined(CONFIG_RTL_DUAL_PCIESLOT_BIWLAN_D) - REG32(PEFGHDAT_REG) &= ~(0x1000); //perst=0 off. - mdelay(300); //PCIE standadrd: poweron: 100us, after poweron: 100ms - mdelay(300); - REG32(PEFGHDAT_REG) |= (0x1000); //PERST=1 -#elif defined(CONFIG_RTL_92D_SUPPORT) - REG32(CLK_MANAGE) &= ~(1<<26); //perst=0 off. - mdelay(500); //PCIE standadrd: poweron: 100us, after poweron: 100ms - mdelay(500); - REG32(CLK_MANAGE) |= (1<<26); //PERST=1 -#endif - } - else - return; -} - -//------------------------------------------------------------------------ - -int OnlyOneReset() -{ - - int result=0; - int portnum=0; - printk("PCIE RESET Only Once\n"); - - - #define CLK_MANAGE 0xb8000010 -#ifdef CONFIG_RTL_819XD - REG32(CLK_MANAGE)|= (1<<12)|(1<<13)|(1<<19)|(1<<20)|(1<<18)|(1<<16); -#endif - REG32(CLK_MANAGE) &= (~(1<<14)); //disable active_pcie0 - REG32(CLK_MANAGE) |= (1<<14); //enable active_pcie0 - - #define PAD_CONTROL 0xb8000048 - REG32(PAD_CONTROL)|=(1<<27); //switch to rc - REG32(CLK_MANAGE) &= (~(1<<16)); //disable active_pcie1 - REG32(CLK_MANAGE) |= (1<<16); //enable active_pcie1 - - //PERST=1 - //REG32(CLK_MANAGE) |= (1<<26); - //PCIE_Device_PERST(0); - - - - for(portnum=0; portnum<2; portnum++) - PCIE_MDIO_Reset(portnum); - mdelay(500); - - for(portnum=0; portnum<2; portnum++) - { - #if 1//def RTL8198_FORMALCHIP_A - HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087); //bokai tell, and fix - - HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003); - HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18); - #ifdef CONFIG_PHY_EAT_40MHZ - HostPCIe_SetPhyMdioWrite(portnum, 5, 0x0BCB); //40M - #endif - - #ifdef CONFIG_PHY_EAT_40MHZ - HostPCIe_SetPhyMdioWrite(portnum, 6, 0xF148); //40M - #else - HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf848); //25M - #endif - - HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff); - - #ifdef CONFIG_RTL_819XD - HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d6); //peisi tune - #else - HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d7); //peisi tune - #endif - HostPCIe_SetPhyMdioWrite(portnum, 0x09, 0x539c); - HostPCIe_SetPhyMdioWrite(portnum, 0x0a, 0x20eb); - HostPCIe_SetPhyMdioWrite(portnum, 0x0d, 0x1766); - //HostPCIe_SetPhyMdioWrite(portnum, 0x0d, 0x1464); //wei add - - HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0511); //for sloving low performance - - - HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00); - HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0); - - HostPCIe_SetPhyMdioWrite(portnum, 0x1a, 0x7e40); //formal chip, reg 0x1a.4=0 - HostPCIe_SetPhyMdioWrite(portnum, 0x1b, 0xFC01); //formal chip reg 0x1b.0=1 - - HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280); - - #endif - } - - PCIE_Device_PERST(0); - mdelay(500); - for(portnum=0; portnum<2; portnum++) - PCIE_PHY_Reset(portnum); - - mdelay(500); - mdelay(500); - mdelay(500); - - - for(portnum=0; portnum<2; portnum++) - { result=PCIE_Check_Link(portnum); - if(result!=1) - continue; - - - #if 1 //wei add patch - - //add compatible, slove sata pcie card. - if(portnum==0) REG32(0xb8b0100c)=(1<<3); //set target Device Num=1; - if(portnum==1) REG32(0xb8b2100c)=(2<<3); //set target Device Num=1; - - unsigned int rc_cfg, cfgaddr; - unsigned int iomapaddr; - unsigned int memmapaddr; - -#define PCIE0_RC_CFG_BASE (0xb8b00000) -#define PCIE0_RC_EXT_BASE (PCIE0_RC_CFG_BASE + 0x1000) -#define PCIE0_EP_CFG_BASE (0xb8b10000) - -#define PCIE1_RC_CFG_BASE (0xb8b20000) -#define PCIE1_RC_EXT_BASE (PCIE1_RC_CFG_BASE + 0x1000) -#define PCIE1_EP_CFG_BASE (0xb8b30000) - - -#define PCIE0_MAP_IO_BASE (0xb8c00000) -#define PCIE0_MAP_MEM_BASE (0xb9000000) - -#define PCIE1_MAP_IO_BASE (0xb8e00000) -#define PCIE1_MAP_MEM_BASE (0xba000000) - -#define MAX_READ_REQSIZE_128B 0x00 -#define MAX_READ_REQSIZE_256B 0x10 -#define MAX_READ_REQSIZE_512B 0x20 -#define MAX_READ_REQSIZE_1KB 0x30 -#define MAX_READ_REQSIZE_2KB 0x40 -#define MAX_READ_REQSIZE_4KB 0x50 - -#define MAX_PAYLOAD_SIZE_128B 0x00 -#define MAX_PAYLOAD_SIZE_256B 0x20 -#define MAX_PAYLOAD_SIZE_512B 0x40 -#define MAX_PAYLOAD_SIZE_1KB 0x60 -#define MAX_PAYLOAD_SIZE_2KB 0x80 -#define MAX_PAYLOAD_SIZE_4KB 0xA0 - - if(portnum==0) - { rc_cfg=PCIE0_RC_CFG_BASE; - cfgaddr=PCIE0_EP_CFG_BASE; - iomapaddr=PCIE0_MAP_IO_BASE; - memmapaddr=PCIE0_MAP_MEM_BASE; - } - else if(portnum==1) - { rc_cfg=PCIE1_RC_CFG_BASE; - cfgaddr=PCIE1_EP_CFG_BASE; - iomapaddr=PCIE1_MAP_IO_BASE; - memmapaddr=PCIE1_MAP_MEM_BASE; - } - //STATUS - //bit 4: capabilties List - - //CMD - //bit 2: Enable Bys master, - //bit 1: enable memmap, - //bit 0: enable iomap - REG32(rc_cfg + 0x04)= 0x00100007; - - //Device Control Register - //bit [7-5] payload size - REG32(rc_cfg + 0x78)= (REG32(rc_cfg + 0x78 ) & (~0xE0)) | MAX_PAYLOAD_SIZE_128B; // Set MAX_PAYLOAD_SIZE to 128B,default - REG32(cfgaddr + 0x04)= 0x00100007; //0x00180007 - - //bit 0: 0:memory, 1 io indicate - //REG32(cfgaddr + 0x10)= (iomapaddr | 0x00000001) & 0x1FFFFFFF; // Set BAR0 - - //bit 3: prefetch - //bit [2:1] 00:32bit, 01:reserved, 10:64bit 11:reserved - //REG32(cfgaddr + 0x18)= (memmapaddr | 0x00000004) & 0x1FFFFFFF; // Set BAR1 - - //offset 0x78 [7:5] - REG32(cfgaddr + 0x78) = (REG32(cfgaddr + 0x78) & (~0xE0)) | (MAX_PAYLOAD_SIZE_128B); // Set MAX_PAYLOAD_SIZE to 128B - - //offset 0x79: [6:4] - REG32(cfgaddr + 0x78) = (REG32(cfgaddr + 0x78) & (~0x7000)) | (MAX_READ_REQSIZE_256B<<8); // Set MAX_REQ_SIZE to 256B,default - - //io and mem limit, setting to no litmit - REG32(rc_cfg+ 0x1c) = (2<<4) | (0<<12); // [7:4]=base [15:12]=limit - REG32(rc_cfg+ 0x20) = (2<<4) | (0<<20); // [15:4]=base [31:20]=limit - REG32(rc_cfg+ 0x24) = (2<<4) | (0<<20); // [15:4]=base [31:20]=limit -#endif - } - - return 1; - -} - -//---------------------------------------------------------------------- -//====================================================================== -//please rewrite me/ here is a lot of ... -#if defined(CONFIG_RTL_8196C) -int PCIE_reset_procedure(int portnum, int Use_External_PCIE_CLK, int mdio_reset) -{ - #define CLK_MANAGE 0xb8000010 - int result; - - REG32(CLK_MANAGE) |= (1<<11); //enable active_pcie0 - - mdelay(10); - REG32(0xb8b0100c)=(1<<3); //set target Device Num=1; - mdelay(10); - - if (mdio_reset) { - printk("Do MDIO_RESET\n"); - // 3.MDIO Reset - PCIE_MDIO_Reset(portnum); - mdelay(10); - } - //4. PCIE PHY Reset - PCIE_PHY_Reset(portnum); - mdelay(10); - mdelay(10); - - //---------------------------------------- - if (mdio_reset) { - HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087); //bokai tell, and fix - - HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003); - HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18); -#ifdef CONFIG_PHY_EAT_40MHZ -#ifdef CONFIG_HIGH_POWER_EXT_PA - HostPCIe_SetPhyMdioWrite(portnum, 5, 0x0BF3); //40M -#else - HostPCIe_SetPhyMdioWrite(portnum, 5, 0x0BCB); //40M -#endif -#endif - -#ifdef CONFIG_PHY_EAT_40MHZ - HostPCIe_SetPhyMdioWrite(portnum, 6, 0xF148); //40M -#else - HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf848); //25M -#endif - - HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff); - HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d7); //peisi tune - -#if 0 //old, - HostPCIe_SetPhyMdioWrite(portnum, 9, 0x531c); - HostPCIe_SetPhyMdioWrite(portnum, 0xd, 0x1766); //peisi tune -#else //saving more power, 8196c pe-si tune - HostPCIe_SetPhyMdioWrite(portnum, 0x09, 0x539c); - HostPCIe_SetPhyMdioWrite(portnum, 0x0a, 0x20eb); - HostPCIe_SetPhyMdioWrite(portnum, 0x0d, 0x1764); -#endif - HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0511); //for sloving low performance - - HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00); - HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0); - - HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280); - } - - //--------------------------------------- - PCIE_Device_PERST(); - - PCIE_PHY_Reset(portnum); - mdelay(500); - REG32(0xb8b00000 + 0x04)= 0x00100007; - REG8(0xb8b00000 + 0x78)=((REG8(0xb8b00000 + 0x78) & (~0xE0)) | MAX_PAYLOAD_SIZE_128B); - mdelay(500); - result=PCIE_Check_Link(portnum); - return result; -} -#elif defined(CONFIG_RTL_819XD) -int PCIE_reset_procedure(int portnum, int Use_External_PCIE_CLK, int mdio_reset) -{ - // dprintf("port=%x, mdio_rst=%x \n", portnum, mdio_reset); - int result=0; - - //first, Turn On PCIE IP - #define CLK_MANAGE 0xb8000010 - if(portnum==0) REG32(CLK_MANAGE) |= (1<<14); //enable active_pcie0 - else if(portnum==1) REG32(CLK_MANAGE) |= (1<<16); //enable active_pcie1 - else return result; - if (portnum==0) - { - REG32(CLK_MANAGE) |= (1<<26); //PERST=1 - } - else if (portnum==1) - { - REG32(0xb8000040)|=0x300; - REG32(PEFGHCNR_REG) &= ~(0x1000); /*port F bit 4 */ - REG32(PEFGHDIR_REG) |= (0x1000); /*port F bit 4 */ - REG32(PEFGHDAT_REG) |= (0x1000); //PERST=1 - } -#ifdef CONFIG_RTL_819XD - REG32(CLK_MANAGE) |= (1<<12)| (1<<13)|(1<<18); -#endif - mdelay(500); - #ifdef CONFIG_RTL8198_REVISION_B - if(portnum==1) - { - #define PAD_CONTROL 0xb8000048 - REG32(PAD_CONTROL)|=(1<<27); - } - #endif - - - if(mdio_reset) - { - if(at2_mode==0) //no auto test, show message - printk("Do MDIO_RESET\n"); - mdelay(1); - // 3.MDIO Reset - PCIE_MDIO_Reset(portnum); - } -/* - PCIE_PHY_Reset(portnum); - */ - mdelay(500); - mdelay(500); - - //---------------------------------------- - if(mdio_reset) - { - //fix 8198 test chip pcie tx problem. -#if defined(CONFIG_RTL8198_REVISION_B) || defined(CONFIG_RTL_819XD) - if ((REG32(BSP_REVR) >= BSP_RTL8198_REVISION_B) || ((REG32(BSP_REVR)&0xfffff000) == BSP_RTL8197D)) - { - #if 1//def RTL8198_FORMALCHIP_A - HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087); //bokai tell, and fix - - HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003); - HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18); - #ifdef CONFIG_PHY_EAT_40MHZ - HostPCIe_SetPhyMdioWrite(portnum, 5, 0x0BCB); //40M - #endif - - #ifdef CONFIG_PHY_EAT_40MHZ - HostPCIe_SetPhyMdioWrite(portnum, 6, 0xF148); //40M - #else - HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf848); //25M - #endif - - HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff); - HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d5); //peisi tune - - #if 0 //old, - HostPCIe_SetPhyMdioWrite(portnum, 9, 0x531c); - HostPCIe_SetPhyMdioWrite(portnum, 0xd, 0x1766); //peisi tune - #else //saving more power, 8196c pe-si tune - HostPCIe_SetPhyMdioWrite(portnum, 0x09, 0x539c); - HostPCIe_SetPhyMdioWrite(portnum, 0x0a, 0x20eb); - HostPCIe_SetPhyMdioWrite(portnum, 0x0d, 0x1766); - #endif -#ifdef CONFIG_RTL_819XD - HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0711); //for sloving low performance -#else - HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0511); //for sloving low performance -#endif - - HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00); - HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0); - - HostPCIe_SetPhyMdioWrite(portnum, 0x1a, 0x7e4f); //formal chip, reg 0x1a.4=0 - HostPCIe_SetPhyMdioWrite(portnum, 0x1b, 0xFC01); //formal chip reg 0x1b.0=1 - - HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280); - - #endif - - } - else -#endif - { -//#define PHY_USE_TEST_CHIP 1 // 1: test chip, 0: fib chip -//#define PHY_EAT_40MHZ 0 // 0: 25MHz, 1: 40MHz - - //HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD187);//ori - HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087); - - HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003); - //HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18); - HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf448); //new - HostPCIe_SetPhyMdioWrite(portnum, 6, 0x408); //avoid noise infuse //15-12=0, 7-5=0, 0448 - - HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff); - HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d5); //new - HostPCIe_SetPhyMdioWrite(portnum, 9, 0x531c); - - //HostPCIe_SetPhyMdioWrite(portnum, 0xa, 0x00C9); - //HostPCIe_SetPhyMdioWrite(portnum, 0xb, 0xe511); - //HostPCIe_SetPhyMdioWrite(portnum, 0xc, 0x0820); - HostPCIe_SetPhyMdioWrite(portnum, 0xd, 0x1766); - HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0010);//ori - // HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00); - - HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0); - HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280); - - - -#if 0 //saving more power - HostPCIe_SetPhyMdioWrite(0xa, 0xeb); - HostPCIe_SetPhyMdioWrite(0x9, 0x538c); - -// HostPCIe_SetPhyMdioWrite(0xc, 0xC828); //original -// HostPCIe_SetPhyMdioWrite(0x0, 0x502F); //fix - - HostPCIe_SetPhyMdioWrite(0xc, 0x8828); //new - HostPCIe_SetPhyMdioWrite(0x0, 0x502F); //fix -#endif - } - } - - //--------------------------------------- - PCIE_Device_PERST(portnum); - - PCIE_PHY_Reset(portnum); - mdelay(500); - mdelay(500); - result=PCIE_Check_Link(portnum); - #if 0 - if(portnum==0) - { - if(result) - { - WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) & 0xFFFFFF7F); - mdelay(100); - WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) | 0x00000080); - } - } - else - { - #ifdef PIN_208 - if(result) - { - WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) & 0xFFFFFF7F); - mdelay(100); - WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) | 0x00000080); - } - #endif - } - #endif - return result; -#endif - -//======================================================================================== - -static int rtl8196b_pci_reset(void) -{ - /* If PCI needs to be reset, put code here. - * Note: - * Software may need to do hot reset for a period of time, say ~100us. - * Here we put 2ms. - */ -#if 1 -//Modified for PCIE PHY parameter due to RD center suggestion by Jason 12252009 -WRITE_MEM32(0xb8000044, 0x9);//Enable PCIE PLL -mdelay(10); -//WRITE_MEM32(0xb8000010, 0x00FFFFD6);//Active LX & PCIE Clock in 8196B system register -WRITE_MEM32(0xb8000010, READ_MEM32(0xb8000010)|(1<<8)|(1<<9)|(1<<10)); -#ifdef PIN_208 -WRITE_MEM32(0xb8000010, READ_MEM32(0xb8000010)|(1<<12)); -#endif -mdelay(10); -WRITE_MEM32(0xb800003C, 0x1);//PORT0 PCIE PHY MDIO Reset -mdelay(10); -WRITE_MEM32(0xb800003C, 0x3);//PORT0 PCIE PHY MDIO Reset -mdelay(10); -#ifdef PIN_208 -WRITE_MEM32(0xb8000040, 0x1);//PORT1 PCIE PHY MDIO Reset -mdelay(10); -WRITE_MEM32(0xb8000040, 0x3);//PORT1 PCIE PHY MDIO Reset -mdelay(10); -#endif -WRITE_MEM32(0xb8b01008, 0x1);// PCIE PHY Reset Close:Port 0 -mdelay(10); -WRITE_MEM32(0xb8b01008, 0x81);// PCIE PHY Reset On:Port 0 -mdelay(10); -#ifdef PIN_208 -WRITE_MEM32(0xb8b21008, 0x1);// PCIE PHY Reset Close:Port 1 -mdelay(10); -WRITE_MEM32(0xb8b21008, 0x81);// PCIE PHY Reset On:Port 1 -mdelay(10); -#endif -#ifdef OUT_CYSTALL -WRITE_MEM32(0xb8b01000, 0xcc011901);// PCIE PHY Reset On:Port 0 -mdelay(10); -#ifdef PIN_208 -WRITE_MEM32(0xb8b21000, 0xcc011901);// PCIE PHY Reset On:Port 1 -mdelay(10); -#endif -#endif -//WRITE_MEM32(0xb8000010, 0x01FFFFD6);// PCIE PHY Reset On:Port 1 -WRITE_MEM32(0xb8000010, READ_MEM32(0xb8000010)|(1<<24)); -mdelay(10); -#endif - WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) & 0xFFFFFF7F); -#ifdef PIN_208 - WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) & 0xFFFFFF7F); -#endif - mdelay(100); - WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) | 0x00000080); -#ifdef PIN_208 - WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) | 0x00000080); -#endif - return 0; -} - -//======================================================================================== - -static int rtl8196b_pcibios_config_access(unsigned char access_type, - unsigned int addr, unsigned int *data) -{ - /* Do 8bit/16bit/32bit access */ - if (access_type & PCI_ACCESS_WRITE) - { - if (access_type & PCI_8BIT_ACCESS) - WRITE_MEM8(addr, *data); - else if (access_type & PCI_16BIT_ACCESS) - WRITE_MEM16(addr, *data); - else - WRITE_MEM32(addr, *data); - } - else if (access_type & PCI_ACCESS_READ) - { - if (access_type & PCI_8BIT_ACCESS) - { - #ifdef CONFIG_RTL8198_REVISION_B - unsigned int data_temp=0; int swap[4]={0,8,16,24}; int diff = addr&0x3; - data_temp=READ_MEM32(addr); - *data=(unsigned int)(( data_temp>>swap[diff])&0xff); - #else - *data = READ_MEM8(addr); - #endif - } - else if (access_type & PCI_16BIT_ACCESS) - { - #ifdef CONFIG_RTL8198_REVISION_B - unsigned int data_temp=0; int swap[4]={0,8,16,24}; int diff = addr&0x3; - data_temp=READ_MEM32(addr); - *data=(unsigned int)(( data_temp>>swap[diff])&0xffff); - #else - *data = READ_MEM16(addr); - #endif - } - else - *data = READ_MEM32(addr); - } - - /* If need to check for PCIE access timeout, put code here */ - /* ... */ - - return 0; -} - - -//======================================================================================== -/* - * RTL8196b supports config word read access for 8/16/32 bit - * - * FIXME: currently only utilize 32bit access - */ -static int rtl8196b_pcibios0_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, unsigned int *val) -{ - unsigned int data = 0; - unsigned int addr = 0; - - if (pci0_bus_number == 0xff) - pci0_bus_number = bus->number; - #if DEBUG_PRINTK - //printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); - //printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); - #endif - - if (bus->number == pci0_bus_number) - { - /* PCIE host controller */ - if (PCI_SLOT(devfn) == 0) - { - addr = BSP_PCIE0_H_CFG + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - else if (bus->number == (pci0_bus_number + 1)) - { - /* PCIE devices directly connected */ - if (PCI_SLOT(devfn) == 0) - { - addr = BSP_PCIE0_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - { - /* Devices connected through bridge */ - if (PCI_SLOT(devfn) < MAX_NUM_DEV) - { - WRITE_MEM32(BSP_PCIE0_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); - addr = BSP_PCIE0_D_CFG1 + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } -#if defined(CONFIG_RTL_819XD) - REG32(0xb8000014)=0x800200; -#endif - #if DEBUG_PRINTK - //printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); - //printk("Read Value: 0x%08X\n", *val); - #endif - - return PCIBIOS_SUCCESSFUL; -} - -//======================================================================================== -static int rtl8196b_pcibios0_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, unsigned int val) -{ - unsigned int data = 0; - unsigned int addr = 0; - - static int pci0_bus_number = 0xff; - if (pci0_bus_number == 0xff) - pci0_bus_number = bus->number; - - #if DEBUG_PRINTK - //printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); - //printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); - #endif - - if (bus->number == pci0_bus_number) - { - /* PCIE host controller */ - if (PCI_SLOT(devfn) == 0) - { - addr = BSP_PCIE0_H_CFG + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); - else - data = val; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - else if (bus->number == (pci0_bus_number + 1)) - { - /* PCIE devices directly connected */ - if (PCI_SLOT(devfn) == 0) - { - addr = BSP_PCIE0_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - { - /* Devices connected through bridge */ - if (PCI_SLOT(devfn) < MAX_NUM_DEV) - { - WRITE_MEM32(BSP_PCIE0_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); - addr = BSP_PCIE0_D_CFG1 + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - - return PCIBIOS_SUCCESSFUL; -} -//======================================================================================== - -/* - * RTL8196b supports config word read access for 8/16/32 bit - * - * FIXME: currently only utilize 32bit access - */ -#ifdef PIN_208 -static int rtl8196b_pcibios1_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, unsigned int *val) -{ - unsigned int data = 0; - unsigned int addr = 0; - - if (pci1_bus_number == 0xff) - pci1_bus_number = bus->number; - - #if DEBUG_PRINTK - printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); - printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); - #endif - - if (bus->number == pci1_bus_number) - { - /* PCIE host controller */ - if (PCI_SLOT(devfn) == 0) - { - addr = BSP_PCIE1_H_CFG + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - else if (bus->number == (pci1_bus_number + 1)) - { - /* PCIE devices directly connected */ - if (PCI_SLOT(devfn) == 0) - { - addr = BSP_PCIE1_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - { - /* Devices connected through bridge */ - if (PCI_SLOT(devfn) < MAX_NUM_DEV) - { - WRITE_MEM32(BSP_PCIE1_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); - addr = BSP_PCIE1_D_CFG1 + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - - #if DEBUG_PRINTK - printk("0xb8000014:%x\n",REG32(0xb8000014)); - //printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); - //printk("Read Value: 0x%08X\n", *val); - #endif - - return PCIBIOS_SUCCESSFUL; -} - -//======================================================================================== -static int rtl8196b_pcibios1_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, unsigned int val) -{ - unsigned int data = 0; - unsigned int addr = 0; - - static int pci1_bus_number = 0xff; - - if (pci1_bus_number == 0xff) - pci1_bus_number = bus->number; - - #if DEBUG_PRINTK - printk("0xb8000014:%x\n",REG32(0xb8000014)); - //printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); - //printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); - #endif - - - if (bus->number == pci1_bus_number) - { - /* PCIE host controller */ - if (PCI_SLOT(devfn) == 0) - { - addr = BSP_PCIE1_H_CFG + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); - else - data = val; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - else if (bus->number == (pci1_bus_number + 1)) - { - /* PCIE devices directly connected */ - if (PCI_SLOT(devfn) == 0) - { - addr = BSP_PCIE1_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - { - /* Devices connected through bridge */ - if (PCI_SLOT(devfn) < MAX_NUM_DEV) - { - WRITE_MEM32(BSP_PCIE1_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); - addr = BSP_PCIE1_D_CFG1 + where; - - if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) - return PCIBIOS_DEVICE_NOT_FOUND; - } - else - return PCIBIOS_DEVICE_NOT_FOUND; - } - - return PCIBIOS_SUCCESSFUL; -} -#endif -//======================================================================================== -struct pci_ops rtl8196b_pci0_ops = { - .read = rtl8196b_pcibios0_read, - .write = rtl8196b_pcibios0_write -}; - -#ifdef PIN_208 -struct pci_ops rtl8196b_pci1_ops = { - .read = rtl8196b_pcibios1_read, - .write = rtl8196b_pcibios1_write -}; -#endif - -static struct pci_controller rtl8196b_pci0_controller = { - .pci_ops = &rtl8196b_pci0_ops, - .mem_resource = &rtl8196b_pci0_mem_resource, - .io_resource = &rtl8196b_pci0_io_resource, -}; - -#ifdef PIN_208 -static struct pci_controller rtl8196b_pci1_controller = { - .pci_ops = &rtl8196b_pci1_ops, - .mem_resource = &rtl8196b_pci1_mem_resource, - .io_resource = &rtl8196b_pci1_io_resource, -}; -#endif - -//======================================================================================== -int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - #if DEBUG_PRINTK - printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); - printk("**Slot: %d\n", slot); - printk("**Pin: %d\n", pin); - printk("**Dev->BUS->Number: %d\n", dev->bus->number); - #endif - -#if defined(CONFIG_RTL_819XD) - if (dev->bus->number < pci1_bus_number) - return BSP_PCIE_IRQ; - else - return BSP_PCIE2_IRQ; -#else - return BSP_PCIE_IRQ; -#endif -} -//======================================================================================== -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - #if DEBUG_PRINTK - printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); - #endif - - return 0; -} - -static __init int bsp_pcie_init(void) -{ - - int Use_External_PCIE_CLK=0; - int result=0,result1=0; - - printk("<<<<<Register 1st PCI Controller>>>>>\n"); - mdelay(1); - - //sry i need more time to figure out all how that stuff should coorectly work - #if defined(CONFIG_RTL_8196C) - result=PCIE_reset_procedure(0, 0, 1); - if (result) - register_pci_controller(&rtl8196b_pci0_controller); - else - REG32(CLK_MANAGE) &= (~(1<<11)); //disable active_pcie0 - #elif defined(CONFIG_RTL_819XD) - #ifndef CONFIG_RTL_DUAL_PCIESLOT_BIWLAN_D - #ifndef PIN_208 - result=PCIE_reset_procedure(0, Use_External_PCIE_CLK, 1); - #else - result=PCIE_reset_procedure(0, Use_External_PCIE_CLK, 1); - mdelay(1); - result1=PCIE_reset_procedure(1, Use_External_PCIE_CLK, 1); - #endif - #else //wei add - OnlyOneReset(); - - result=PCIE_Check_Link(0); - result1=PCIE_Check_Link(1); - - #endif - - #if DEBUG_PRINTK - printk("<<<<<Register 1st PCI Controller>>>>>\n"); - #ifdef PIN_208 - printk("<<<<<Register 2nd PCI Controller>>>>>\n"); - #endif - #endif - mdelay(1); - #ifndef CONFIG_RTL_DUAL_PCIESLOT_BIWLAN_D - if(result) - register_pci_controller(&rtl8196b_pci0_controller); - else - { - REG32(CLK_MANAGE) &= (~(1<<14)); //disable active_pcie0 - } - #ifdef PIN_208 - if(result1) - register_pci_controller(&rtl8196b_pci1_controller); - else - { - REG32(CLK_MANAGE) &= (~(1<<16)); //disable active_pcie1 - } - #endif - #else - - if(result1) - register_pci_controller(&rtl8196b_pci1_controller); - else - { REG32(CLK_MANAGE) &= (~(1<<16)); //disable active_pcie1 - } - - - if(result) - register_pci_controller(&rtl8196b_pci0_controller); - else - { REG32(CLK_MANAGE) &= (~(1<<14)); //disable active_pcie0 - } - - - #endif - #endif - - return 0 -} - -arch_initcall(bsp_pcie_init); diff --git a/target/linux/realtek/files/arch/rlx/bsp/prom.c b/target/linux/realtek/files/arch/rlx/bsp/prom.c deleted file mode 100644 index 1580cc1fe..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/prom.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (C) 2006, Realtek Semiconductor Corp. - * Copyright (C) 2013, Artur Artamonov (artur@advem.lv) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <asm/bootinfo.h> -#include <asm/addrspace.h> -#include <asm/page.h> -#include <asm/cpu.h> - -#include <asm/rlxbsp.h> - -#include "bspchip.h" -#include "bspcpu.h" -#include "rlxhack.h" - -extern char arcs_cmdline[]; - -#ifdef CONFIG_EARLY_PRINTK -static int promcons_output __initdata = 0; - -void unregister_prom_console(void) -{ - if (promcons_output) { - promcons_output = 0; - } -} - -void disable_early_printk(void) - __attribute__ ((alias("unregister_prom_console"))); -#endif - - -const char *get_system_type(void) -{ -#if defined(CONFIG_RTL_8196C) - return "RTL8196C"; -#elif defined(CONFIG_RTL_819XD) - return "RTL819xD"; -#endif -} - -/* Do basic initialization */ -void __init bsp_init(void) -{ - u_long mem_size; - - /*user CMLLINE created by menuconfig*/ - /* - arcs_cmdline[0] = '\0'; - strcpy(arcs_cmdline, "console=ttyS0,38400"); - */ - -#if defined(CONFIG_RTL_819X) - #ifdef cpu_mem_size - mem_size = cpu_mem_size; - #elif defined(RTL_8198_NFBI_BOARD) - mem_size = ((7 << 20)-16); //reserve 16 byte for firmware header; - #endif - /*now: alway believe DRAM configuration register*/ - { - unsigned int DCRvalue = 0; - unsigned int bus_width = 0, chip_sel = 0, row_cnt = 0, col_cnt = 0,bank_cnt = 0; - - DCRvalue = ( (*(volatile unsigned int *)BSP_MC_MTCR0)); - - /*bit 19,0:2 bank; 1: 4 bank*/ - switch(DCRvalue & 0x080000) - { - case 0x0: - bank_cnt = 2; - break; - case 0x080000: - bank_cnt = 4; - break; - default: - bank_cnt = 0; - break; - } - - /*bit 22~24: colomn count*/ - switch(DCRvalue & 0x01C00000) - { - case 0x00000000: - col_cnt = 256; - break; - case 0x00400000: - col_cnt = 512; - break; - case 0x00800000: - col_cnt = 1024; - break; - case 0x00C00000: - col_cnt = 2048; - break; - case 0x01000000: - col_cnt = 4096; - break; - default: - printk("unknow colomn count(0x%x)\n",DCRvalue & 0x01C00000); - break; - } - - /*bit 25~26: row count*/ - switch(DCRvalue & 0x06000000) - { - case 0x00000000: - row_cnt = 2048; - break; - case 0x02000000: - row_cnt = 4096; - break; - case 0x04000000: - row_cnt = 8192; - break; - case 0x06000000: - row_cnt = 16384; - break; - default: - printk("unknow row count(0x%x)\n",DCRvalue & 0x06000000); - break; - } - - /*bit 27: chip select*/ - switch(DCRvalue & 0x08000000) - { - case 0x0: - chip_sel = 1; - break; - case 0x08000000: - chip_sel = 2; - break; - default: - printk("unknow chip select(0x%x)\n",DCRvalue & 0x08000000); - break; - } - - /*bit 28~29: bus width*/ - switch(DCRvalue & 0x30000000) - { - case 0x0: - bus_width = 8; - break; - case 0x10000000: - bus_width = 16; - break; - case 0x20000000: - bus_width = 32; - break; - default: - printk("bus width is reseved!\n"); - break; - } - - /*total size(Byte)*/ - if((REG32(0xb800100C)&0x40000000) == 0x40000000) - { - mem_size = (row_cnt * col_cnt *bank_cnt) * (bus_width >> 3) * chip_sel*2; - } - else - { - mem_size = (row_cnt * col_cnt *bank_cnt) * (bus_width >> 3) * chip_sel; - } - } -#else - mem_size = cpu_mem_size; -#endif - add_memory_region(0, mem_size, BOOT_MEM_RAM); -} - -void __init bsp_free_prom_memory(void) -{ - return; -} diff --git a/target/linux/realtek/files/arch/rlx/bsp/rlxhack.h b/target/linux/realtek/files/arch/rlx/bsp/rlxhack.h deleted file mode 100644 index 5d7d87433..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/rlxhack.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __RLXHACK_H -#define __RLXHACK_H - -/* - * Register access macro - */ - -#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg)) -#define REG16(reg) (*(volatile unsigned short *)((unsigned int)reg)) -#define REG08(reg) (*(volatile unsigned char *)((unsigned int)reg)) -#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg)) - -#define WRITE_MEM32(addr, val) (*(volatile unsigned int *) (addr)) = (val) -#define READ_MEM32(addr) (*(volatile unsigned int *) (addr)) -#define WRITE_MEM16(addr, val) (*(volatile unsigned short *) (addr)) = (val) -#define READ_MEM16(addr) (*(volatile unsigned short *) (addr)) -#define WRITE_MEM8(addr, val) (*(volatile unsigned char *) (addr)) = (val) -#define READ_MEM8(addr) (*(volatile unsigned char *) (addr)) - - -#endif diff --git a/target/linux/realtek/files/arch/rlx/bsp/serial.c b/target/linux/realtek/files/arch/rlx/bsp/serial.c deleted file mode 100644 index f4e1ef19d..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/serial.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2006, Realtek Semiconductor Corp. - * Copyright (C) 2013, Artur Artamonov <artur@advem.lv> - */ - - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/serial.h> -#include <linux/serial_core.h> -#include <linux/serial_8250.h> -#include <linux/string.h> - -#include <asm/serial.h> - -#include "bspchip.h" - -void __init bsp_serial_init(void) -{ -#ifdef CONFIG_SERIAL_SC16IS7X0 - extern void __init sc16is7x0_get_port( struct uart_port *port ); -#endif -#if defined( CONFIG_SERIAL_SC16IS7X0 ) || defined( CONFIG_SERIAL_RTL8198_UART1 ) - unsigned int line = 0; -#else - const unsigned int line = 0; -#endif - struct uart_port s; - - /* clear memory */ - memset(&s, 0, sizeof(s)); - - /* - * UART0 - */ - s.line = line; - s.type = PORT_16550A; - s.irq = BSP_UART0_IRQ; - s.iotype = UPIO_MEM; - s.regshift = 2; -#if 1 - s.uartclk = BSP_SYS_CLK_RATE; - s.fifosize = 16; - //s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY; - s.flags = UPF_SKIP_TEST; - s.mapbase = BSP_UART0_MAP_BASE; - //s.membase = ioremap_nocache(s.mapbase, BSP_UART0_MAPSIZE); - s.membase = ioremap_nocache(s.mapbase, 0x20); -#else - s.uartclk = BSP_SYS_CLK_RATE - BSP_BAUDRATE * 24; //??? - s.fifosize = 1; //??? - s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_SPD_CUST; - s.membase = (unsigned char *)BSP_UART0_BASE; - s.custom_divisor = BSP_SYS_CLK_RATE / (BSP_BAUDRATE * 16) - 1; -#endif - - if (early_serial_setup(&s) != 0) - { - #if defined(CONFIG_RTL_8196C) - panic("RTL8196C: bsp_serial_init failed!"); - #elif defined(CONFIG_RTL_819XD) - panic("RTL8196D: bsp_serial_init failed!"); - #endif - } -#ifdef CONFIG_SERIAL_RTL8198_UART1 - // UART1 - #define UART_BASE 0xB8000100 //0xb8002100 uart 1 - REG32(0xb8000040) = (REG32(0xb8000040) & ~(0x3<<3)) | (0x01<<3); //pin mux to UART1 - REG32(0xb8002110) |= (1<<29); //enable flow control - s.line = ++ line; - s.irq = BSP_UART1_IRQ; - s.mapbase = BSP_UART1_MAP_BASE; - s.membase = ioremap_nocache(s.mapbase, 0x20); - - if (early_serial_setup(&s) != 0) { - panic("RTL819xD: bsp_serial_init UART1 failed!"); - } -#endif - -#ifdef CONFIG_SERIAL_SC16IS7X0 - sc16is7x0_get_port( &s ); - s.line = ++ line; - - if (early_serial_setup(&s) != 0) { - panic("RTL819xD: bsp_serial_init i2c uart failed!"); - } -#endif -} diff --git a/target/linux/realtek/files/arch/rlx/bsp/setup.c b/target/linux/realtek/files/arch/rlx/bsp/setup.c deleted file mode 100644 index 48b776044..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/setup.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2006, Realtek Semiconductor Corp. - * Copyright (C) 2013, Artur Artamonov (artur@advem.lv) - */ - -#include <linux/console.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/sched.h> -#include <linux/netdevice.h> -#include <linux/rtnetlink.h> - -#include <asm/addrspace.h> -#include <asm/irq.h> -#include <asm/io.h> - -#include <asm/bootinfo.h> -#include <asm/time.h> -#include <asm/reboot.h> -#include <asm/rlxbsp.h> - -#include <asm/rtl865x/rtl865xc_asicregs.h> - -#include "bspchip.h" - -extern int bsp_swcore_init(unsigned int version); -extern void rtl819x_add_device_usb(void); - -static void prom_putchar(char c) -{ -#define UART0_BASE 0xB8002000 -#define UART0_THR (UART0_BASE + 0x000) -#define UART0_FCR (UART0_BASE + 0x008) -#define UART0_LSR (UART0_BASE + 0x014) -#define TXRST 0x04 -#define CHAR_TRIGGER_14 0xC0 -#define LSR_THRE 0x20 -#define TxCHAR_AVAIL 0x00 -#define TxCHAR_EMPTY 0x20 -unsigned int busy_cnt = 0; - - do - { - /* Prevent Hanging */ - if (busy_cnt++ >= 30000) - { - /* Reset Tx FIFO */ - REG8(UART0_FCR) = TXRST | CHAR_TRIGGER_14; - return; - } - } while ((REG8(UART0_LSR) & LSR_THRE) == TxCHAR_AVAIL); - - /* Send Character */ - REG8(UART0_THR) = c; -} - -static void early_console_write(const char *s, unsigned n) -{ - while (n-- && *s) { - if (*s == '\n') - prom_putchar('\r'); - prom_putchar(*s); - s++; - } -} - - -static void shutdown_netdev(void) -{ - struct net_device *dev; - - printk("Shutdown network interface\n"); - read_lock(&dev_base_lock); - - for_each_netdev(&init_net, dev) - { - if(dev->flags &IFF_UP) - { - printk("%s:===>\n",dev->name); - rtnl_lock(); -#if defined(CONFIG_COMPAT_NET_DEV_OPS) - if(dev->stop) - dev->stop(dev); -#else - if ((dev->netdev_ops)&&(dev->netdev_ops->ndo_stop)) - dev->netdev_ops->ndo_stop(dev); -#endif - rtnl_unlock(); - } - } -#if defined(CONFIG_RTL8192CD) || defined(CONFIG_RTL8192E) - { - extern void force_stop_wlan_hw(void); - force_stop_wlan_hw(); - } -#endif - read_unlock(&dev_base_lock); -} - -static void bsp_machine_restart(char *command) -{ - static void (*back_to_prom)(void) = (void (*)(void)) 0xbfc00000; - - REG32(GIMR)=0; - - local_irq_disable(); -#ifdef CONFIG_NET - shutdown_netdev(); -#endif - REG32(BSP_WDTCNR) = 0; //enable watch dog - while (1) ; - /* Reboot */ - back_to_prom(); -} - -static void bsp_machine_halt(void) -{ - while(1); -} - -static void bsp_machine_power_off(void) -{ - while(1); -} - -/* - * callback function - */ -extern void _imem_dmem_init(void); -void __init bsp_setup(void) -{ - int ret= -1; - unsigned int version = 0; - #if defined(CONFIG_RTL_819XD) - if((REG32(0xb8000000)&0xf)<3) - { - REG32(0xb8000088)= (REG32(0xb8000088) & ( ~(3<<5)&~(0xF<<0))); - //printk("0xb8000088=%x\n",REG32(0xb8000088)); - REG32(0xb8000088) =(REG32(0xb8000088)|(1<<4)); - //printk("0xb8000088=%x\n",REG32(0xb8000088)); - REG32(0xb8000088) = REG32(0xb8000088) & (~(3<<7)); - //printk("0xb8000088=%x\n",REG32(0xb8000088)); - } - #endif - - /* define io/mem region */ - ioport_resource.start = 0x18000000; - ioport_resource.end = 0x1fffffff; - - iomem_resource.start = 0x18000000; - iomem_resource.end = 0x1fffffff; - - /* set reset vectors */ - _machine_restart = bsp_machine_restart; - _machine_halt = bsp_machine_halt; - pm_power_off = bsp_machine_power_off; - -#if defined(CONFIG_RTL_819XD) - #if defined(CONFIG_RTL_DUAL_PCIESLOT_BIWLAN_D) - { - unsigned int tmp=0,tmp1=0,tmp2=0; - tmp1=REG32(0xb8001004); - if((REG32(0xb8001000)&0x80000000)==0x80000000) - { - //REG32(0xb8001008)=0x6d13a4c0; - REG32(0xb8001004)=tmp1; - } - } - #endif -#endif - - #if defined(CONFIG_RTL_8196C) - version = 15; - #elif defined(CONFIG_RTL_819XD) - version = 8; - #endif - /* initialize uart */ - bsp_serial_init(); - _imem_dmem_init(); - - /* initialize switch core */ -#if defined(CONFIG_RTL_819X) - ret = bsp_swcore_init(version); - if(ret != 0) - { - bsp_machine_halt(); - } -#endif -} - -pure_initcall(rtl819x_add_device_usb); diff --git a/target/linux/realtek/files/arch/rlx/bsp/timer.c b/target/linux/realtek/files/arch/rlx/bsp/timer.c deleted file mode 100644 index 137e73557..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/timer.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * linux/arch/rlx/rlxocp/time.c - * - * Copyright (C) 1999 Harald Koerfgen - * Copyright (C) 2000 Pavel Machek (pavel@suse.cz) - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * Copyright (C) 2006 Realtek Semiconductor Corp. - * Copyright (C) 2013 Artur Artamonov (artur@advem.lv) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Time handling functinos for Philips Nino. - */ -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <linux/timex.h> -#include <linux/delay.h> - -#include <asm/time.h> -#include <asm/rlxbsp.h> - -#include "bspchip.h" -#include "rlxhack.h" - -#ifdef CONFIG_RTL_TIMER_ADJUSTMENT -#include <net/rtl/rtl_types.h> -#include <rtl865xc_asicregs.h> - -void rtl865x_setupTimer1(void) -{ - WRITE_MEM32( BSP_TCCNR, READ_MEM32(BSP_TCCNR) & ~BSP_TC1EN );/* Disable timer1 */ - #ifdef CONFIG_RTL8196C_REVISION_B - WRITE_MEM32( BSP_TC1DATA, 0xfffffff0); - #else - WRITE_MEM32( BSP_TC1DATA, 0xffffff00); - #endif - WRITE_MEM32( BSP_TCCNR, ( READ_MEM32(BSP_TCCNR) | BSP_TC1EN ) | BSP_TC1MODE_TIMER );/* Enable timer1 - timer mode */ - WRITE_MEM32( BSP_TCIR, READ_MEM32(BSP_TCIR) & ~BSP_TC1IE ); /* Disable timer1 interrupt */ -} -#endif - -void inline bsp_timer_ack(void) -{ - REG32(BSP_TCIR) |= BSP_TC0IP; -} - -void __init bsp_timer_init(void) -{ - unsigned int sys_clock_rate; - - sys_clock_rate = BSP_SYS_CLK_RATE; - - /* Clear Timer IP status */ - if (REG32(BSP_TCIR) & BSP_TC0IP) - REG32(BSP_TCIR) |= BSP_TC0IP; - - /* disable timer */ - REG32(BSP_TCCNR) = 0; /* disable timer before setting CDBR */ - - /* initialize timer registers */ -#if defined(CONFIG_RTL_8196C) - REG32(BSP_CDBR)=(BSP_DIVISOR*8) << BSP_DIVF_OFFSET; - #ifdef CONFIG_RTL8196C_REVISION_B - if (REG32(BSP_REVR) == RTL8196C_REVISION_B) - REG32(BSP_TC0DATA) = (((sys_clock_rate/(BSP_DIVISOR*8))/HZ)) << 4; - else - #endif - REG32(BSP_TC0DATA) = (((sys_clock_rate/(BSP_DIVISOR*8))/HZ)) << BSP_TCD_OFFSET; - -//when will add one more platform change to more generic code -#elif defined(CONFIG_RTL_819XD) - REG32(BSP_CDBR)=(BSP_DIVISOR) << BSP_DIVF_OFFSET; - #if defined(CONFIG_RTL8198_REVISION_B) || defined(CONFIG_RTL_819XD) - if ((REG32(BSP_REVR) >= BSP_RTL8198_REVISION_B) || ((REG32(BSP_REVR) & 0xFFFFF000) == BSP_RTL8197D)) - REG32(BSP_TC0DATA) = (((sys_clock_rate/BSP_DIVISOR)/HZ)) << 4; - else - #endif - REG32(BSP_TC0DATA) = (((sys_clock_rate/BSP_DIVISOR)/HZ)) << BSP_TCD_OFFSET; - #if defined(CONFIG_RTL_WTDOG) - #ifdef CONFIG_RTK_VOIP - { - extern void bsp_enable_watchdog( void ); - bsp_enable_watchdog(); - } - #else - REG32(BSP_WDTCNR) = 0x00600000; - #endif - #endif -#endif - - - // extend timer base to 4 times - //REG32(BSP_CDBR)=(BSP_DIVISOR*4) << BSP_DIVF_OFFSET; - //REG32(BSP_TC0DATA) = (((sys_clock_rate/(BSP_DIVISOR*4))/HZ)) << BSP_TCD_OFFSET; -#if defined(CONFIG_RTL_WTDOG) - REG32(BSP_WDTCNR) = 0x00600000; -#endif - - /* hook up timer interrupt handler */ - rlx_clockevent_init(BSP_TC0_IRQ); - - /* enable timer */ - REG32(BSP_TCCNR) = BSP_TC0EN | BSP_TC0MODE_TIMER; - REG32(BSP_TCIR) = BSP_TC0IE; -#ifdef CONFIG_RTL_TIMER_ADJUSTMENT - rtl865x_setupTimer1(); -#endif - -} - -#ifdef CONFIG_RTK_VOIP -void timer1_enable(void) -{ - printk( "timer1_enable not implement!!\n" ); -} - -void timer1_disable(void) -{ - printk( "timer1_disable not implement!!\n" ); -} - -#ifdef CONFIG_RTL_WTDOG -int bBspWatchdog = 0; - -void bsp_enable_watchdog( void ) -{ - bBspWatchdog = 1; - *(volatile unsigned long *)(0xb800311C)=0x00600000; -} - -void bsp_disable_watchdog( void ) -{ - *(volatile unsigned long *)(0xb800311C)=0xA5600000; - bBspWatchdog = 0; -} -#endif // CONFIG_RTL_WTDOG - -#endif // CONFIG_RTK_VOIP diff --git a/target/linux/realtek/files/arch/rlx/bsp/vmlinux.lds.S b/target/linux/realtek/files/arch/rlx/bsp/vmlinux.lds.S deleted file mode 100644 index 80048359f..000000000 --- a/target/linux/realtek/files/arch/rlx/bsp/vmlinux.lds.S +++ /dev/null @@ -1,296 +0,0 @@ -#include <asm/asm-offsets.h> -#include <asm-generic/vmlinux.lds.h> - -#undef mips -#define mips mips -OUTPUT_ARCH(mips) -ENTRY(kernel_entry) -PHDRS { - text PT_LOAD FLAGS(7); /* RWX */ - note PT_NOTE FLAGS(4); /* R__ */ -} -jiffies = JIFFIES; - -SECTIONS -{ - . = LOADADDR; - /* read-only */ - _text = .; /* Text and read-only data */ - .text : { - TEXT_TEXT - SCHED_TEXT - LOCK_TEXT - KPROBES_TEXT - *(.text.*) - *(.fixup) - *(.gnu.warning) -/*#ifdef CONFIG_RTL8192SE*/ -#if 1 - /* start of wlan f/w definition */ - __fw_start = . ; - *(.rtl8192sfw.bin) - __fw_end = . ; - - __AGC_TAB_start = . ; - *(.AGC_TAB.txt) - __AGC_TAB_end = . ; - - __phy_reg_start = . ; - *(.phy_reg.txt) - __phy_reg_end = . ; - - __phy_reg_MP_start = . ; - *(.phy_reg_MP.txt) - __phy_reg_MP_end = . ; - - __MACPHY_REG_start = . ; - *(.MACPHY_REG.txt) - __MACPHY_REG_end = . ; - - __radio_a_start = . ; - *(.radio_a.txt) - __radio_a_end = . ; - - __radio_b_start = . ; - *(.radio_b.txt) - __radio_b_end = . ; - - __PHY_REG_PG_start = .; - *(.PHY_REG_PG.txt) - __PHY_REG_PG_end = .; - - __PHY_to1T2R_start = .; - *(.PHY_to1T2R.txt) - __PHY_to1T2R_end = .; - - __PHY_to1T2R_b_start = .; - *(.PHY_to1T2R_b.txt) - __PHY_to1T2R_b_end = .; - - __PHY_to1T1R_start = .; - *(.PHY_to1T1R.txt) - __PHY_to1T1R_end = .; - - __PHY_to1T1R_b_start = .; - *(.PHY_to1T1R_b.txt) - __PHY_to1T1R_b_end = .; - - __radio_a_hp_start = . ; - *(.radio_a_hp.txt) - __radio_a_hp_end = . ; - - /* end of wlan f/w definition */ -#endif - - } :text = 0 - _etext = .; /* End of text section */ - - /* Exception table */ - . = ALIGN(16); - __ex_table : { - __start___ex_table = .; - *(__ex_table) - __stop___ex_table = .; - } - - /* Exception table for data bus errors */ - __dbe_table : { - __start___dbe_table = .; - *(__dbe_table) - __stop___dbe_table = .; - } - - . = ALIGN(16384); - __iram = . ; - .iram : - { - *(.iram-gen) /* general usage (essential) */ - *(.iram-fwd) /* general packet forwarding used */ - *(.iram-rtkwlan) /* realtek wlan driver */ - *(.iram-l2-fwd) /* L2 packet forwarding */ - *(.iram-l34-fwd) /* L34 packet forwarding */ - *(.iram-tx) /* protocol stack TX */ - *(.iram-extdev) /* ROMEDRV extension device fwd */ - *(.iram-crypto) /* authetication / crypto-engine */ - *(.iram-voip) /* voip */ - *(.iram) /* other usage */ - *(.iram.1) - } - - . = ALIGN(8192); - __dram = . ; - __dram_start = . ; - .dram : - { - *(.dram-wapi) /*wapi encryption/decryption used*/ - *(.dram-gen) /* general usage (essential) */ - *(.dram-fwd) /* general packet forwarding used */ - *(.dram-l2-fwd) /* L2 packet forwarding */ - *(.dram-l34-fwd) /* L34 packet forwarding */ - *(.dram-extdev) /* ROMEDRV extension device fwd */ - *(.dram-rtkwlan) /* realtek wlan driver */ - *(.dram-crypto) /* authetication / crypto-engine */ - *(.dram-voip) /* voip */ - *(.dram-tx) /* protocol stack TX */ - *(.dram) /* other usage */ - *(.dram.1) - } - . = ALIGN(8192); - __dram_end = . ; - - NOTES :text :note - .dummy : { *(.dummy) } :text - - RODATA - - /* writeable */ - .data : { /* Data */ - . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ - /* - * This ALIGN is needed as a workaround for a bug a - * gcc bug upto 4.1 which limits the maximum alignment - * to at most 32kB and results in the following - * warning: - * - * CC arch/mips/kernel/init_task.o - * arch/mips/kernel/init_task.c:30: warning: alignment - * of ‘init_thread_union�is greater than maximum - * object file alignment. Using 32768 - */ - . = ALIGN(_PAGE_SIZE); - *(.data.init_task) - - DATA_DATA - CONSTRUCTORS - } - _gp = . + 0x8000; - .lit8 : { - *(.lit8) - } - .lit4 : { - *(.lit4) - } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { - *(.sdata) - } - - . = ALIGN(_PAGE_SIZE); - .data_nosave : { - __nosave_begin = .; - *(.data.nosave) - } - . = ALIGN(_PAGE_SIZE); - __nosave_end = .; - - . = ALIGN(1 << 5); - .data.cacheline_aligned : { - *(.data.cacheline_aligned) - } - _edata = .; /* End of data section */ - - /* will be freed after init */ - . = ALIGN(_PAGE_SIZE); /* Init code and data */ - __init_begin = .; - .init.text : { - _sinittext = .; - INIT_TEXT - _einittext = .; - } - .init.data : { - INIT_DATA - } - . = ALIGN(16); - .init.setup : { - __setup_start = .; - *(.init.setup) - __setup_end = .; - } - - .initcall.init : { - __initcall_start = .; - INITCALLS - __initcall_end = .; - } - - .con_initcall.init : { - __con_initcall_start = .; - *(.con_initcall.init) - __con_initcall_end = .; - } - SECURITY_INIT - - /* .exit.text is discarded at runtime, not link time, to deal with - * references from .rodata - */ - .exit.text : { - EXIT_TEXT - } - .exit.data : { - EXIT_DATA - } -#if defined(CONFIG_BLK_DEV_INITRD) - . = ALIGN(_PAGE_SIZE); - .init.ramfs : { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - } -#endif - PERCPU(_PAGE_SIZE) - . = ALIGN(_PAGE_SIZE); - __init_end = .; - /* freed after init ends here */ - - __bss_start = .; /* BSS */ - .sbss : { - *(.sbss) - *(.scommon) - } - .bss : { - *(.bss) - *(COMMON) - } - __bss_stop = .; - - _end = . ; - - /* Sections to be discarded */ - /DISCARD/ : { - *(.exitcall.exit) - - /* ABI crap starts here */ - *(.MIPS.options) - *(.options) - *(.pdr) - *(.reginfo) - } - - /* These mark the ABI of the kernel for debuggers. */ - .mdebug.abi32 : { - KEEP(*(.mdebug.abi32)) - } - .mdebug.abi64 : { - KEEP(*(.mdebug.abi64)) - } - - /* This is the MIPS specific mdebug section. */ - .mdebug : { - *(.mdebug) - } - - STABS_DEBUG - DWARF_DEBUG - - /* These must appear regardless of . */ - .gptab.sdata : { - *(.gptab.data) - *(.gptab.sdata) - } - .gptab.sbss : { - *(.gptab.bss) - *(.gptab.sbss) - } -} |