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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-12-14 07:16:56 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-12-14 07:16:56 +0000
commit99cb0c3b29cc609fce9099af190036c38a885899 (patch)
treed050d6333deea639ed926a820d362541e35ac164 /target
parent728059014263c1046bb6991269b84cfbcd305f2f (diff)
ar71xx: reorder some patches
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34674 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/patches-3.3/523-MIPS-ath79-OTP-support.patch (renamed from target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch)6
-rw-r--r--target/linux/ar71xx/patches-3.3/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch (renamed from target/linux/ar71xx/patches-3.3/621-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch)0
-rw-r--r--target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch20
-rw-r--r--target/linux/ar71xx/patches-3.6/523-MIPS-ath79-OTP-support.patch (renamed from target/linux/ar71xx/patches-3.6/620-MIPS-ath79-OTP-support.patch)6
-rw-r--r--target/linux/ar71xx/patches-3.6/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch (renamed from target/linux/ar71xx/patches-3.6/621-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch)0
-rw-r--r--target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch20
6 files changed, 26 insertions, 26 deletions
diff --git a/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-3.3/523-MIPS-ath79-OTP-support.patch
index 7bd17d80d..5f7fd2100 100644
--- a/target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch
+++ b/target/linux/ar71xx/patches-3.3/523-MIPS-ath79-OTP-support.patch
@@ -149,9 +149,9 @@
#endif /* _ATH79_DEV_WMAC_H */
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -129,6 +129,14 @@
- #define QCA955X_NFC_BASE 0x1b000200
- #define QCA955X_NFC_SIZE 0xb8
+@@ -113,6 +113,14 @@
+ #define QCA955X_EHCI1_BASE 0x1b400000
+ #define QCA955X_EHCI_SIZE 0x200
+#define AR9300_OTP_BASE 0x14000
+#define AR9300_OTP_STATUS 0x15f18
diff --git a/target/linux/ar71xx/patches-3.3/621-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch b/target/linux/ar71xx/patches-3.3/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
index bada5a897..bada5a897 100644
--- a/target/linux/ar71xx/patches-3.3/621-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
+++ b/target/linux/ar71xx/patches-3.3/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
index 150f0eecb..7ca7dfc04 100644
--- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
@@ -53,9 +53,9 @@
+#define QCA955X_NFC_BASE 0x1b000200
+#define QCA955X_NFC_SIZE 0xb8
- /*
- * DDR_CTRL block
-@@ -167,6 +183,9 @@
+ #define AR9300_OTP_BASE 0x14000
+ #define AR9300_OTP_STATUS 0x15f18
+@@ -175,6 +191,9 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
@@ -65,7 +65,7 @@
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
-@@ -179,6 +198,8 @@
+@@ -187,6 +206,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
@@ -74,7 +74,7 @@
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -191,6 +212,9 @@
+@@ -199,6 +220,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
@@ -84,7 +84,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -212,6 +236,8 @@
+@@ -220,6 +244,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
@@ -93,7 +93,7 @@
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -244,6 +270,8 @@
+@@ -252,6 +278,8 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
@@ -102,7 +102,7 @@
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
-@@ -370,16 +398,50 @@
+@@ -378,16 +406,50 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@@ -153,7 +153,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -520,6 +582,12 @@
+@@ -528,6 +590,12 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -166,7 +166,7 @@
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
-@@ -550,4 +618,133 @@
+@@ -558,4 +626,133 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
diff --git a/target/linux/ar71xx/patches-3.6/620-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-3.6/523-MIPS-ath79-OTP-support.patch
index 7bd17d80d..5f7fd2100 100644
--- a/target/linux/ar71xx/patches-3.6/620-MIPS-ath79-OTP-support.patch
+++ b/target/linux/ar71xx/patches-3.6/523-MIPS-ath79-OTP-support.patch
@@ -149,9 +149,9 @@
#endif /* _ATH79_DEV_WMAC_H */
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -129,6 +129,14 @@
- #define QCA955X_NFC_BASE 0x1b000200
- #define QCA955X_NFC_SIZE 0xb8
+@@ -113,6 +113,14 @@
+ #define QCA955X_EHCI1_BASE 0x1b400000
+ #define QCA955X_EHCI_SIZE 0x200
+#define AR9300_OTP_BASE 0x14000
+#define AR9300_OTP_STATUS 0x15f18
diff --git a/target/linux/ar71xx/patches-3.6/621-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch b/target/linux/ar71xx/patches-3.6/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
index bada5a897..bada5a897 100644
--- a/target/linux/ar71xx/patches-3.6/621-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
+++ b/target/linux/ar71xx/patches-3.6/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
diff --git a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
index 511fc1fd8..006217f6f 100644
--- a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
@@ -53,9 +53,9 @@
+#define QCA955X_NFC_BASE 0x1b000200
+#define QCA955X_NFC_SIZE 0xb8
- /*
- * DDR_CTRL block
-@@ -167,6 +183,9 @@
+ #define AR9300_OTP_BASE 0x14000
+ #define AR9300_OTP_STATUS 0x15f18
+@@ -175,6 +191,9 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
@@ -65,7 +65,7 @@
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
-@@ -179,6 +198,8 @@
+@@ -187,6 +206,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
@@ -74,7 +74,7 @@
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -191,6 +212,9 @@
+@@ -199,6 +220,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
@@ -84,7 +84,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -212,6 +236,8 @@
+@@ -220,6 +244,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
@@ -93,7 +93,7 @@
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -244,6 +270,8 @@
+@@ -252,6 +278,8 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
@@ -102,7 +102,7 @@
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
-@@ -370,16 +398,50 @@
+@@ -378,16 +406,50 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@@ -153,7 +153,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -520,6 +582,12 @@
+@@ -528,6 +590,12 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -166,7 +166,7 @@
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
-@@ -551,4 +619,133 @@
+@@ -559,4 +627,133 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 00:11:28 +0000