diff options
| author | Roman Yeryomin <roman@advem.lv> | 2013-02-06 02:59:31 +0200 |
|---|---|---|
| committer | Roman Yeryomin <roman@advem.lv> | 2013-05-26 00:48:31 +0300 |
| commit | d76a86507530dd3d3a63a73523b4f48bd656aed9 (patch) | |
| tree | cfd2f8b5f2feee81a34f73ca7fa5fd7694419f63 /target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d | |
| parent | b8c7700266d9eee9e49ba91a5be70498d4f22413 (diff) | |
Rebase files to rsdk 3.2 and refresh patches. Compilable (not by humans).
Signed-off-by: Roman Yeryomin <roman@advem.lv>
Diffstat (limited to 'target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d')
11 files changed, 2327 insertions, 0 deletions
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/AGC_TAB_n_92d_hp.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/AGC_TAB_n_92d_hp.txt new file mode 100644 index 000000000..dbaa0ad9b --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/AGC_TAB_n_92d_hp.txt @@ -0,0 +1,265 @@ +// AGC_TABLE 101222
+0xc78 0x7B000001 //-110
+0xc78 0x7A010001
+0xc78 0x79020001
+0xc78 0x78030001
+0xc78 0x77040001
+0xc78 0x76050001 //-100
+0xc78 0x75060001
+0xc78 0x74070001
+0xc78 0x73080001
+0xc78 0x72090001
+0xc78 0x710A0001 //-90
+0xc78 0x700B0001
+0xc78 0x6F0C0001
+0xc78 0x6E0D0001
+0xc78 0x6D0E0001
+0xc78 0x6C0F0001 //-80
+0xc78 0x6B100001
+0xc78 0x6A110001
+0xc78 0x69120001
+0xc78 0x68130001
+0xc78 0x67140001 //-70
+0xc78 0x66150001
+0xc78 0x65160001
+0xc78 0x64170001
+0xc78 0x63180001
+0xc78 0x62190001 //-60
+0xc78 0x611A0001
+0xc78 0x601B0001
+0xc78 0x491C0001
+0xc78 0x481D0001
+0xc78 0x471E0001 //-50
+0xc78 0x461F0001
+0xc78 0x45200001
+0xc78 0x44210001
+0xc78 0x43220001
+0xc78 0x42230001 //-40
+0xc78 0x41240001
+0xc78 0x40250001
+0xc78 0x26260001
+0xc78 0x25270001
+0xc78 0x24280001 //-30
+0xc78 0x23290001
+0xc78 0x222A0001
+0xc78 0x212B0001
+0xc78 0x202C0001
+0xc78 0x062D0001 //-20
+0xc78 0x052E0001
+0xc78 0x042F0001
+0xc78 0x03300001
+0xc78 0x02310001
+0xc78 0x01320001 //-10
+0xc78 0x00330001
+0xc78 0x00340001
+0xc78 0x00350001
+0xc78 0x00360001
+0xc78 0x00370001 //0
+0xc78 0x00380001
+0xc78 0x00390001
+0xc78 0x003A0001
+0xc78 0x003B0001
+0xc78 0x003C0001 //10
+0xc78 0x003D0001
+0xc78 0x003E0001
+0xc78 0x003F0001 //16
+// AGC_TABLE 2
+0xc78 0x7b400001 //-110
+0xc78 0x7b410001
+0xc78 0x7a420001
+0xc78 0x79430001
+0xc78 0x78440001
+0xc78 0x77450001 //-100
+0xc78 0x76460001
+0xc78 0x75470001
+0xc78 0x74480001
+0xc78 0x73490001
+0xc78 0x724a0001 //-90
+0xc78 0x714b0001
+0xc78 0x704c0001
+0xc78 0x6f4d0001
+0xc78 0x6e4e0001
+0xc78 0x6d4f0001 //-80
+0xc78 0x6c500001
+0xc78 0x6b510001
+0xc78 0x6a520001
+0xc78 0x69530001
+0xc78 0x68540001 //-70
+0xc78 0x67550001
+0xc78 0x66560001
+0xc78 0x65570001
+0xc78 0x64580001
+0xc78 0x63590001 //-60
+0xc78 0x625a0001
+0xc78 0x615b0001
+0xc78 0x605c0001
+0xc78 0x485d0001
+0xc78 0x475e0001 //-50
+0xc78 0x465f0001
+0xc78 0x45600001
+0xc78 0x44610001
+0xc78 0x43620001
+0xc78 0x42630001 //-40
+0xc78 0x41640001
+0xc78 0x40650001
+0xc78 0x27660001
+0xc78 0x26670001
+0xc78 0x25680001 //-30
+0xc78 0x24690001
+0xc78 0x236a0001
+0xc78 0x226b0001
+0xc78 0x216c0001
+0xc78 0x206d0001 //-20
+0xc78 0x206e0001
+0xc78 0x206f0001
+0xc78 0x20700001
+0xc78 0x20710001
+0xc78 0x20720001 //-10
+0xc78 0x20730001
+0xc78 0x20740001
+0xc78 0x20750001
+0xc78 0x20760001
+0xc78 0x20770001 //0
+0xc78 0x20780001
+0xc78 0x20790001
+0xc78 0x207a0001
+0xc78 0x207b0001
+0xc78 0x207c0001 //10
+0xc78 0x207d0001
+0xc78 0x207e0001
+0xc78 0x207f0001 //16
+// RSSI TABLE_0 (for 2G)
+0xc78 0x2C000002
+0xc78 0x2C010002
+0xc78 0x2C020002
+0xc78 0x2C030002
+0xc78 0x2C040002
+0xc78 0x2C050002
+0xc78 0x2C060002
+0xc78 0x2C070002
+0xc78 0x2C080002 //-54
+0xc78 0x30090002 //-50
+0xc78 0x320A0002
+0xc78 0x340B0002 //-46
+0xc78 0x380C0002 //-42
+0xc78 0x3C0D0002 //-38
+0xc78 0x400E0002
+0xc78 0x440F0002 //-30
+0xc78 0x48100002
+0xc78 0x4A110002 //-24
+0xc78 0x4E120002 //-20
+0xc78 0x50130002
+0xc78 0x54140002 //-14
+0xc78 0x58150002
+0xc78 0x5C160002
+0xc78 0x60170002
+0xc78 0x62180002
+0xc78 0x62190002
+0xc78 0x621A0002
+0xc78 0x621B0002
+0xc78 0x621C0002
+0xc78 0x621D0002
+0xc78 0x621E0002
+0xc78 0x621F0002
+// RSSI TABLE_1 (for 5G)
+0xc78 0x32000044
+0xc78 0x32010044
+0xc78 0x32020044
+0xc78 0x32030044
+0xc78 0x32040044
+0xc78 0x32050044
+0xc78 0x32060044
+0xc78 0x32070044
+0xc78 0x32080044 //-60 32
+0xc78 0x34090044
+0xc78 0x350a0044
+0xc78 0x360b0044
+0xc78 0x370c0044
+0xc78 0x380d0044
+0xc78 0x390e0044
+0xc78 0x3a0f0044 //-50 3a
+0xc78 0x3e100044
+0xc78 0x42110044
+0xc78 0x44120044
+0xc78 0x46130044 //-40 46
+0xc78 0x4a140044
+0xc78 0x4e150044
+0xc78 0x50160044 //-30 50
+0xc78 0x55170044
+0xc78 0x5a180044 //-20 5a
+0xc78 0x5e190044
+0xc78 0x641A0044 //-10 64
+0xc78 0x6e1B0044 //0 6e
+0xc78 0x6e1C0044
+0xc78 0x6e1D0044
+0xc78 0x6e1E0044
+0xc78 0x6e1F0044
+// RSSI TABLE_2
+//0xc78 0x32000088
+//0xc78 0x32010088
+//0xc78 0x32020088
+//0xc78 0x32030088
+//0xc78 0x32040088
+//0xc78 0x32050088
+//0xc78 0x38060088
+//0xc78 0x38070088
+//0xc78 0x38080088
+//0xc78 0x40090088
+//0xc78 0x460a0088
+//0xc78 0x4a0b0088
+//0xc78 0x4e0c0088
+//0xc78 0x540d0088
+//0xc78 0x560e0088
+//0xc78 0x580f0088
+//0xc78 0x5c100088
+//0xc78 0x64110088
+//0xc78 0x6a120088
+//0xc78 0x6e130088
+//0xc78 0x6e140088
+//0xc78 0x6e150088
+//0xc78 0x6e160088
+//0xc78 0x6e170088
+//0xc78 0x6e180088
+//0xc78 0x6e190088
+//0xc78 0x6e1A0088
+//0xc78 0x6e1B0088
+//0xc78 0x6e1C0088
+//0xc78 0x6e1D0088
+//0xc78 0x6e1E0088
+//0xc78 0x6e1F0088
+//// RSSI TABLE_3
+//0xc78 0x320000d0
+//0xc78 0x320100d0
+//0xc78 0x320200d0
+//0xc78 0x320300d0
+//0xc78 0x320400d0
+//0xc78 0x320500d0
+//0xc78 0x380600d0
+//0xc78 0x380700d0
+//0xc78 0x380800d0
+//0xc78 0x400900d0
+//0xc78 0x460a00d0
+//0xc78 0x4a0b00d0
+//0xc78 0x4e0c00d0
+//0xc78 0x540d00d0
+//0xc78 0x560e00d0
+//0xc78 0x580f00d0
+//0xc78 0x5c1000d0
+//0xc78 0x641100d0
+//0xc78 0x6a1200d0
+//0xc78 0x6e1300d0
+//0xc78 0x6e1400d0
+//0xc78 0x6e1500d0
+//0xc78 0x6e1600d0
+//0xc78 0x6e1700d0
+//0xc78 0x6e1800d0
+//0xc78 0x6e1900d0
+//0xc78 0x6e1A00d0
+//0xc78 0x6e1B00d0
+//0xc78 0x6e1C00d0
+//0xc78 0x6e1D00d0
+//0xc78 0x6e1E00d0
+//0xc78 0x6e1F00d0
+// disable all AGC& RSSI table select
+0xc78 0x6e1f0000
+0xff
\ No newline at end of file diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/PHY_REG_PG_92d_hp.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/PHY_REG_PG_92d_hp.txt new file mode 100644 index 000000000..f610a173d --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/PHY_REG_PG_92d_hp.txt @@ -0,0 +1,287 @@ +//=========================
+// PHY_related MAC register by channel,
+// Related from willis 090406 PHY_REG_PG.txt for 92D
+//=========================
+
+//Offset talbe_0 for for EEPROM_0xC4[bit0~2]= 0 , Table_0 (20/40MHz, all channel)
+// USB_POWER_SUPPORT use this table ONLY!
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+//=========================
+//Offset talbe_1 for EEPROM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+//=========================
+//Offset talbe_2 for Mode EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+//=========================
+//Offset talbe_3 for Mode EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz, ch10~ch14)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+//=========================
+// Offset table _4 for EERPOM_0xC4[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03)
+// For Ant_A
+0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M
+0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M
+0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12
+// For Ant_B
+0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M
+0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M
+0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12
+
+//=========================
+// Offset table _5 for EEPROM_0xC4[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09)
+// For Ant_A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+//=========================
+// Offset table _6 for EEPROM_0xC4[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz, ch10~ch14)
+// For Ant_A
+0xe00 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x2a // for CCK 1M
+0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M
+0xe10 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12
+// For Ant_B
+0x830 0xffffffff 0x00000000 // base on 0x2a // for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x2a // for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x2a // for CCK 5.5M, 2M, 1M
+0x86c 0x000000ff 0x00 // base on 0x2a // for CCK 11M
+0x83c 0xffffffff 0x00000000 // base on 0x2a // for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x2a // for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x2a // for MCS=15,14,13,12
+
+
+//========================= 11a mode
+//Offset talbe_L_band for EEPROM_0xC4[bit0~2]= 1 Ch36-Ch64, Table_L_band (20MHz, ch36~ch50 ch52~ch64)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+
+//========================= 11a mode
+//Offset talbe_M_band for EEPROM_0xC4[bit0~2]= 1 Ch100-Ch140, Table_M_band (20MHz, ch100~ch140)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+
+
+//========================= 11a mode
+//Offset talbe_H_band for EEPROM_0xC4[bit0~2]= 1 Ch149-Ch165, Table_H_band (20MHz, ch149~ch165)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+
+//========================= 11a mode
+//Offset talbe_L_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch38-Ch62, Table_L_band_40 (40MHz, ch38~ch48 ch54~ch62)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+
+//========================= 11a mode
+//Offset talbe_M_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch102-Ch138, Table_M_band_40 (40MHz, ch102~ch138)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+
+//========================= 11a mode
+//Offset talbe_H_band_40 for EEPROM_0xC4[bit0~2]= 1 Ch151-Ch163, Table_H_band_40 (40MHz, ch151~ch163)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30 //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30 //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00 // base on 0x30 //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000 // base on 0x30 //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30 //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30 //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30 //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30 //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32 //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32 //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000 // base on 0x34 //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00 // base on 0x34 //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32 //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32 //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32 //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32 //for MCS=15,14,13,12
+
+
+0xff //end of file
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/PHY_REG_n_92d_hp.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/PHY_REG_n_92d_hp.txt new file mode 100644 index 000000000..81e6b1ea0 --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/PHY_REG_n_92d_hp.txt @@ -0,0 +1,222 @@ +//Release version: RTL8192D.0.1006.2011
+//100909
+//0x024 0x0011800d //syn CLK enable, Xtal_bsel=nand
+//0x028 0x00ffdb83 //320MHz CLK enable
+//0x014 0x088ba955 //SPS=1.537V
+//0x010 0x49022b03
+//=======================
+// PAGE_8 ( FPGA_PHY0 )
+//=======================
+0x800 0x80040002 // turn off RF when 1R CCA
+0x804 0x00000003
+0x808 0x0000fc00
+0x80c 0x0000000A
+0x810 0x10001331
+0x814 0x020c3d10
+0x818 0x02200385 // [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385
+0x81c 0x00000000
+0x820 0x01000100 // 0x01000000 (SI), 0x01000100 (PI)
+0x824 0x00390004
+0x828 0x01000100 // 0x01000000 (SI), 0x01000100 (PI)
+0x82c 0x00390004
+0x830 0x27272727 // Path-B TX AGC codewod, 6M, 9M, 12M, 18M
+0x834 0x27272727 // Path-B TX AGC codewod, 24M, 36M, 48M, 54M
+0x838 0x27272727 // Path-B TX AGC codewod, MCS32, 1M, 2M, 5.5M
+0x83c 0x27272727 // Path-B TX AGC codewod, MCS0, MCS1, MCS2, MCS3
+0x840 0x00010000 //RF to standby mode
+0x844 0x00010000 //RF to standby mode
+0x848 0x27272727 // Path-B TX AGC codewod, MCS4, MCS5, MCS6, MCS7
+0x84c 0x27272727 // Path-B TX AGC codewod, MCS8, MCS9, MCS10, MCS11
+0x850 0x00000000 // RF wakeup, TBD
+0x854 0x00000000 // RF sleep, TBD
+0x858 0x569a569a
+0x85c 0x0c1b25a4 // AFE ctrl reg (ASIC) RX AD3 CCA mode
+0x860 0x66e60250 //88CE default left anatenna
+0x864 0x061f0150
+0x868 0x27272727 // Path-B TX AGC codewod, MCS12, MCS13, MCS14, MCS15
+0x86c 0x272b2b2b // Path-B 11M TX AGC codeword, Path-A 2M/5.5M/11M TX AGC codeword
+0x870 0x07000700 // z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA)
+0x874 0x22188000 //AD3 must be off for 92D testchip
+0x878 0x08080808 // RF mode for standby & rx_low_power codeword
+0x87c 0x0001fff8 // TST mode
+0x880 0xc0083070 // AFE ctrl reg (ASIC)
+0x884 0x00000cd5 // AFE ctrl reg (ASIC)
+0x888 0x00000000 // AFE ctrl reg (ASIC)
+0x88c 0xcc0000c0 // [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND
+0x890 0x00000800
+0x894 0xfffffffe
+0x898 0x40302010
+0x89c 0x00706050
+//
+//=======================
+// PAGE_9 ( FPGA_PHY1 )
+//=======================
+0x900 0x00000000
+0x904 0x00000023
+0x908 0x00000000
+0x90c 0x81121313 // tx antenna by contorl register
+//
+//=======================
+// PAGE_A ( CCK_PHY0 )
+//=======================
+0xa00 0x00d047c8
+0xa04 0x80ff000c // CCK 1T for power saving
+0xa08 0x8c8a8300 //
+0xa0c 0x2e68120f
+0xa10 0x9500bb78 //
+0xa14 0x11144028
+0xa18 0x00881117
+0xa1c 0x89140f00
+0xa20 0x15160000 //Arthur-power tracking for high-power
+0xa24 0x070b0f12 //Arthur-power tracking for high-power
+0xa28 0x00000104 //Arthur-power tracking for high-power
+0xa2c 0x00d30000
+0xa70 0x101fbf00
+0xa74 0x00000007
+//
+//=======================
+// PAGE_B
+//=======================
+//
+//
+//=======================
+// PAGE_C ( OFDM_PHY0 )
+//=======================
+0xc00 0x40071d40 // initial gain @ CCA negedge
+0xc04 0x03a05633
+0xc08 0x001000e4 // [8:4] is about DBG_GPIO selection
+0xc0c 0x6c6c6c6c
+0xc10 0x08800000
+0xc14 0x40000100
+0xc18 0x08800000
+0xc1c 0x40000100
+0xc20 0x00000000 // DTR TH
+0xc24 0x00000000 // DTR TH
+0xc28 0x00000000 // DTR TH
+0xc2c 0x00000000 // DTR TH
+0xc30 0x69e9ac44 // PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44
+0xc34 0x469652cf
+0xc38 0x49795994
+0xc3c 0x0a979718
+0xc40 0x1f7c403f
+0xc44 0x000100b7
+0xc48 0xec020107 //[1]=1:enable L1_SBD
+0xc4c 0x007f037f // turn off edcca
+0xc50 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420
+0xc54 0x43bc009e
+0xc58 0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420
+0xc5c 0x433c00a8
+0xc60 0x00000000 // DTR TH
+0xc64 0x7116848b //L1-SBD //31168a8b for 6M sen. 0x5116828b, 0x5116848b
+0xc68 0x47c00bff //L1-SBD
+0xc6c 0x00000036 //L1-SBD
+0xc70 0x2c7f000d // disable AGC flow-1
+0xc74 0x258610db // AGC RSSI setting time = 600nS.//0x0186109b=>RRSI=500ns,BBP=300ns for PI used, 0x0186175b
+0xc78 0x0000001f
+0xc7c 0x40b95612 // enable ht rxhp
+0xc80 0x24000090 //2011.11.16 Arthur-power tracking for high-power
+0xc84 0x20f60000
+0xc88 0x24000090 //2011.11.16 Arthur-power tracking for high-power
+0xc8c 0xa0e40000
+0xc90 0x00121820 // TX Power Training for path-A
+0xc94 0x00000007
+0xc98 0x00121820// TX Power Training for path-B
+0xc9c 0x00007f7f // turn off pre-cca
+0xca0 0x00000000
+0xca4 0x00000080 // reserved
+0xca8 0x00000000 // reserved
+0xcac 0x00000000 // reserved
+0xcb0 0x00000000 // reserved
+0xcb4 0x00000000 // reserved
+0xcb8 0x00000000 // reserved
+0xcbc 0x28000000
+0xcc0 0x00000000 // reserved
+0xcc4 0x00000000 // reserved
+0xcc8 0x00000000 // reserved
+0xccc 0x00000000 // reserved
+0xcd0 0x00000000 // reserved
+0xcd4 0x00000000 // reserved
+0xcd8 0x64b11e20 // DFS
+0xcdc 0xe0767533 // DFS
+0xce0 0x00222222
+0xce4 0x00000000
+0xce8 0x37644302
+0xcec 0x2f97d40c
+//
+//=======================
+// PAGE_D ( OFDM_PHY1 )
+//=======================
+0xd00 0x00080740
+0xd04 0x00020403
+0xd08 0x0000907f
+0xd0c 0x20010201
+0xd10 0xa0633333
+0xd14 0x3333bc43
+0xd18 0x7a8f5b6b
+0xd2c 0xcc979975
+0xd30 0x00000000
+0xd34 0x80608404
+0xd38 0x00000000
+0xd3c 0x00027353
+0xd40 0x00000000
+0xd44 0x00000000
+0xd48 0x00000000
+0xd4c 0x00000000
+0xd50 0x6437140a
+0xd54 0x00000000
+0xd58 0x00000000
+0xd5c 0x30032064
+0xd60 0x4653de68
+0xd64 0x04518a3c //[26]=1:enable L1-SBD//
+0xd68 0x00002101
+0xd6c 0x2a201c16 // DTR
+0xd70 0x1812362e // DTR
+0xd74 0x322c2220 // DTR
+0xd78 0x000e3c24 // DTR
+//=======================
+// PAGE_E
+//=======================
+0xe00 0x2a2a2a2a // Path-A TX AGC codewod, 6M, 9M, 12M, 18M
+0xe04 0x2a2a2a2a // Path-A TX AGC codewod, 24M, 36M, 48M, 54M
+0xe08 0x03902a2a // Path-A TX AGC codewod, MCS32, 1M
+0xe10 0x2a2a2a2a // Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3
+0xe14 0x2a2a2a2a // Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7
+0xe18 0x2a2a2a2a // Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11
+0xe1c 0x2a2a2a2a // Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15
+0xe28 0x00000000
+0xe30 0x1000dc1f // 0xe30~0xe60: IQK
+0xe34 0x10008c1f
+0xe38 0x02140102
+0xe3C 0x681604c2
+0xe40 0x01007c00
+0xe44 0x01004800
+0xe48 0xfb000000
+0xe4c 0x000028d1
+0xe50 0x1000dc1f
+0xe54 0x10008c1f
+0xe58 0x02140102
+0xe5C 0x28160d05
+0xe60 0x00000010
+//0xe64 0x281600a0 // Reserved in 92C/88C
+0xe68 0x001b25a4 //AFE ctrl reg (ASIC) Ultra low power
+0xe6c 0x63db25a4 // AFE ctrl reg (ASIC) Blue-Tooth
+0xe70 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_CCA
+0xe74 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_RFON
+0xe78 0x0c126da4 // AFE ctrl reg (ASIC) TX_CCK_BBON
+0xe7c 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_RFON
+0xe80 0x0c126da4 // AFE ctrl reg (ASIC) TX_OFDM_BBON
+0xe84 0x63db25a4 // AFE ctrl reg (ASIC) TX_TO_RX
+0xe88 0x0c126da4 // AFE ctrl reg (ASIC) TX_TO_TX
+0xe8c 0x63db25a4 // AFE ctrl reg (ASIC) RX_CCK
+0xed0 0x63db25a4 // AFE ctrl reg (ASIC) RX_OFDM
+0xed4 0x63db25a4 // AFE ctrl reg (ASIC) RX_WAIT_RIFS
+0xed8 0x63db25a4 // AFE ctrl reg (ASIC) RX_TO_RX
+0xedc 0x001b25a4 // AFE ctrl reg (ASIC) Standby
+0xee0 0x001b25a4 // AFE ctrl reg (ASIC) Sleep
+0xeec 0x6fdb25a4 // AFE ctrl reg (ASIC) PMPD_ANAEN
+//
+0xf14 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG
+0xf1c 0x64 // Pkt Interval = 100us
+0xf4c 0x00000004 // Only for FPGA PMAC
+0xf00 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb
+0xff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d.txt new file mode 100644 index 000000000..54fb34af9 --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d.txt @@ -0,0 +1,40 @@ +
+//<Band_P> <BBSW Positive delta value>, refer to thermal delta value between read and PG.
+//<Band_N> <BBSW Negative delta value>, refer to thermal delta value between read and PG.
+
+//============== 2G CCK PathA&B ===============
+
+2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22
+2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18
+2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23
+2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18
+
+//============== 2G PathA&B ===============
+
+2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22
+2GA_N 1 3 4 6 7 9 10 12 13 15 16 18
+2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23
+2GB_N 1 3 4 6 7 9 10 12 13 15 16 18
+
+//============== 5GL PathA&B ===============
+// 5G bane1&2
+5GLA_P 2 4 7 8 10 11 15 17 19 21 23
+5GLA_N 2 3 4 7 8 10 12 13 15 16 17 18
+5GLB_P 2 4 7 8 10 11 15 17 19 21 23
+5GLB_N 4 5 6 8 9 11 12 13 14 15 16 17
+
+//============== 5GM PathA&B ===============
+// 5G bane3
+5GMA_P 2 4 5 7 9 13 15 19 21 22 23
+5GMA_N 4 5 8 9 11 14 15 16 17 18 19 20
+5GMB_P 2 4 5 7 9 13 15 19 21 22 23
+5GMB_N 3 4 6 7 9 12 13 14 15 17 18 19
+
+//============== 5GH PathA&B ===============
+// 5G bane4
+5GHA_P 2 4 6 8 10 14 16 19 21 22 24
+5GHA_N 4 5 8 9 11 14 15 17 18 19 20 21
+5GHB_P 3 5 7 9 11 13 17 19 21 22 23
+5GHB_N 3 4 6 7 9 12 13 15 16 17 18 19
+
+
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d_hp.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d_hp.txt new file mode 100644 index 000000000..54fb34af9 --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/REG_TXPWR_TRK_n_92d_hp.txt @@ -0,0 +1,40 @@ +
+//<Band_P> <BBSW Positive delta value>, refer to thermal delta value between read and PG.
+//<Band_N> <BBSW Negative delta value>, refer to thermal delta value between read and PG.
+
+//============== 2G CCK PathA&B ===============
+
+2GCCKA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22
+2GCCKA_N 1 3 4 6 7 9 10 12 13 15 16 18
+2GCCKB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23
+2GCCKB_N 1 3 4 6 7 9 10 12 13 15 16 18
+
+//============== 2G PathA&B ===============
+
+2GA_P 2 4 5 7 8 10 11 13 14 16 17 19 20 22
+2GA_N 1 3 4 6 7 9 10 12 13 15 16 18
+2GB_P 3 5 6 8 9 11 12 14 15 17 18 20 21 23
+2GB_N 1 3 4 6 7 9 10 12 13 15 16 18
+
+//============== 5GL PathA&B ===============
+// 5G bane1&2
+5GLA_P 2 4 7 8 10 11 15 17 19 21 23
+5GLA_N 2 3 4 7 8 10 12 13 15 16 17 18
+5GLB_P 2 4 7 8 10 11 15 17 19 21 23
+5GLB_N 4 5 6 8 9 11 12 13 14 15 16 17
+
+//============== 5GM PathA&B ===============
+// 5G bane3
+5GMA_P 2 4 5 7 9 13 15 19 21 22 23
+5GMA_N 4 5 8 9 11 14 15 16 17 18 19 20
+5GMB_P 2 4 5 7 9 13 15 19 21 22 23
+5GMB_N 3 4 6 7 9 12 13 14 15 17 18 19
+
+//============== 5GH PathA&B ===============
+// 5G bane4
+5GHA_P 2 4 6 8 10 14 16 19 21 22 24
+5GHA_N 4 5 8 9 11 14 15 17 18 19 20 21
+5GHB_P 3 5 7 9 11 13 17 19 21 22 23
+5GHB_N 3 4 6 7 9 12 13 15 16 17 18 19
+
+
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_GM_new.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_GM_new.txt new file mode 100644 index 000000000..617a70c2c --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_GM_new.txt @@ -0,0 +1,244 @@ +//100909
+0x00 0x30000 //HSSI_AGC
+0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN
+0x02 0x00000 //2G_TXIQGEN
+0x03 0x18c63
+0x04 0x18c63 //0x70000
+//0x05 0xfd800 //HSSI_power_control
+//0x06 0xf001c //HSSI_2G_5G_RX_gain_control
+//0x07 0x3c800 //HSSI_TX_gain_control
+0x08 0x84000 //2G_LO_leakage
+0x0b 0x1c000 //24000//2G_5G_TX_PA
+0x0e 0x18c67 //APK default 0x18c63
+0x0f 0x00851 //2G_TXRX_IQGEN
+0x14 0x21440 //TX_bias_table_I
+//0x15 0x00430 //TX_IPA_table
+//0x16 0xe0332 //TX_bias_table_II
+//0x17 0xf0000 //HSSI_SYN2_power_control
+0x18 0x17524 //channel_band_control
+0x19 0x00000 //TRXIQ control
+0x1d 0xa1290 //RXBB_contorl
+//0x22 0x00000
+0x23 0x01558 //TXBB_control
+//0x24 0x00000
+//0x3d 0x00000
+//0x3e 0x00000
+//0x3f 0x00000
+//0x42 0x08400 //thermal meter
+
+//2G_RFE_control
+0x1a 0x30a99
+0x1b 0x40b00
+0x1c 0xfc339
+//5G_RFE_control
+0x3a 0xa57eb //0xfd7eb
+0x3b 0x20000 //0xe0000
+0x3c 0xff454 //0xff7d4
+//2G_TX_RFE_control
+0x20 0x0aa52
+0x21 0x54000
+//5G_TX_RFE_control
+0x40 0x0aa52
+0x41 0x14000
+//SYN control
+0x25 0x803be
+0x26 0xfc638
+0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting
+0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting
+0x29 0xd7110
+0x2a 0x8eb04 //for Tx 40M spur//0x8cb04
+0x2b 0x4128b
+0x2c 0x01840
+//0x2f 0x22ff0
+//2G_PA_control
+0x43 0x2444f
+0x44 0x1adb0
+0x45 0x56467
+0x46 0x8992c
+0x47 0x0452c
+//5G_PA_control_intPA
+0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443
+0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730
+0x4a 0x50f0f
+0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee
+0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee
+
+////2G_table_start////
+0x18 0x07401
+0x00 0x70000
+//2G_RX_gain_table
+0x12 0xdc000
+0x12 0x90000
+0x12 0x51000
+0x12 0x12000
+//2G_TX_gain_table
+0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40
+0x13 0x247ab
+0x13 0x2079f
+0x13 0x1c793
+0x13 0x1839f
+0x13 0x14396
+0x13 0x1019e
+0x13 0x0c195
+0x13 0x08198
+0x13 0x040a4
+0x13 0x0001c
+//2G_IPA_bias_table
+0x15 0x0f424
+0x15 0x4f424
+0x15 0x8f424
+//2G_TX_table_II
+0x16 0xe1330 //High gain
+0x16 0xa1330 //middle gain
+0x16 0x61330 //low gain
+0x16 0x21330 //ultra low gain
+
+
+////5G_table_start////
+//5GL_channel
+0x18 0x17524
+0x00 0x70000
+//5GL_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GL_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x103b9
+0x13 0x0c3ad
+0x13 0x081b9
+0x13 0x041ad
+0x13 0x000b9
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GM_channel
+0x18 0x37564
+0x00 0x70000
+//5GM_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GM_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x103b9
+0x13 0x0c3ad
+0x13 0x081b9
+0x13 0x041ad
+0x13 0x000b9
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GH_channel
+0x18 0x57595
+0x00 0x70000
+//5GH_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GH_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x103b9 //0x1039d //0x10399
+0x13 0x0c3ad //0x0c399 //0x0c38d
+0x13 0x081b9 //0x0819d //0x08199
+0x13 0x041ad //0x04199 //0x0418d
+0x13 0x000b9 //0x00099 //0x00099
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+// 5G_IMR_tank_start
+0x30 0x4470f
+0x31 0x44ff0
+0x32 0x00070
+0x33 0xdd480
+0x34 0xffac0
+0x35 0xb80c0
+0x36 0x77000
+0x37 0x64ff2
+0x38 0xe7661
+0x39 0x00e90
+//end
+
+0x00 0x30000
+0x18 0x0f401 //2G channel
+0xfe
+0xfe
+0x1e 0x88009
+0x1f 0x80003
+0xfe
+0x1e 0x88001
+0x1f 0x80000
+0xfe
+//Rewrite Syn-table
+0x18 0x97524 //for DMSP EVM [bit19]=1
+0xfe
+0xfe
+0xfe
+0xfe
+0x2b 0x41289
+0xfe
+0x2d 0x6aaaa
+0x2e 0xb4d01
+0x2d 0x80000
+0x2e 0x04d02
+0x2d 0x95555
+0x2e 0x54d03
+0x2d 0xaaaaa
+0x2e 0xb4d04
+0x2d 0xc0000
+0x2e 0x04d05
+0x2d 0xd5555
+0x2e 0x54d06
+0x2d 0xeaaaa
+0x2e 0xb4d07
+0x2d 0x00000
+0x2e 0x05108
+0x2d 0x15555
+0x2e 0x55109
+0x2d 0x2aaaa
+0x2e 0xb510a
+0x2d 0x40000
+0x2e 0x0510b
+0x2d 0x55555
+0x2e 0x5510c
+//end
+//0x18 0x17524
+0xff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_GM_new1.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_GM_new1.txt new file mode 100644 index 000000000..3f72bcd46 --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_GM_new1.txt @@ -0,0 +1,244 @@ +//100909
+0x00 0x30000 //HSSI_AGC
+0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN
+0x02 0x00000 //2G_TXIQGEN
+0x03 0x18c63
+0x04 0x18c63 //0x70000
+//0x05 0xfd800 //HSSI_power_control
+//0x06 0xf001c //HSSI_2G_5G_RX_gain_control
+//0x07 0x3c800 //HSSI_TX_gain_control
+0x08 0x84000 //2G_LO_leakage
+0x0b 0x1c000 //24000//2G_5G_TX_PA
+0x0e 0x18c67 //APK default 0x18c63
+0x0f 0x00851 //2G_TXRX_IQGEN
+0x14 0x21440 //TX_bias_table_I
+//0x15 0x00430 //TX_IPA_table
+//0x16 0xe0332 //TX_bias_table_II
+//0x17 0xf0000 //HSSI_SYN2_power_control
+0x18 0x17524 //channel_band_control
+0x19 0x00000 //TRXIQ control
+0x1d 0xa1290 //RXBB_contorl
+//0x22 0x00000
+0x23 0x01558 //TXBB_control
+//0x24 0x00000
+//0x3d 0x00000
+//0x3e 0x00000
+//0x3f 0x00000
+//0x42 0x08400 //thermal meter
+
+//2G_RFE_control
+0x1a 0x30a99
+0x1b 0x40b00
+0x1c 0xfc339
+//5G_RFE_control
+0x3a 0xa57eb //0xfd7eb
+0x3b 0x20000 //0xe0000
+0x3c 0xff454 //0xff7d4
+//2G_TX_RFE_control
+0x20 0x0aa52
+0x21 0x54000
+//5G_TX_RFE_control
+0x40 0x0aa52
+0x41 0x14000
+//SYN control
+0x25 0x803be
+0x26 0xfc638
+0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting
+0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting
+0x29 0xd7110
+0x2a 0x8eb04 //for Tx 40M spur//0x8cb04
+0x2b 0x4128b
+0x2c 0x01840
+//0x2f 0x22ff0
+//2G_PA_control
+0x43 0x2444f
+0x44 0x1adb0
+0x45 0x56467
+0x46 0x8992c
+0x47 0x0452c
+//5G_PA_control_intPA
+0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443
+0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730
+0x4a 0x50f0f
+0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee
+0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee
+
+////2G_table_start////
+0x18 0x07401
+0x00 0x70000
+//2G_RX_gain_table
+0x12 0xdc000
+0x12 0x90000
+0x12 0x51000
+0x12 0x12000
+//2G_TX_gain_table
+0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40
+0x13 0x247ab
+0x13 0x2079f
+0x13 0x1c793
+0x13 0x1839f
+0x13 0x14396
+0x13 0x1019e
+0x13 0x0c195
+0x13 0x08198
+0x13 0x040a4
+0x13 0x0001c
+//2G_IPA_bias_table
+0x15 0x0f424
+0x15 0x4f424
+0x15 0x8f424
+//2G_TX_table_II
+0x16 0xe1330 //High gain
+0x16 0xa1330 //middle gain
+0x16 0x61330 //low gain
+0x16 0x21330 //ultra low gain
+
+
+////5G_table_start////
+//5GL_channel
+0x18 0x17524
+0x00 0x70000
+//5GL_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GL_TX_gain_table_intPA
+0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power
+0x13 0x24fb3
+0x13 0x20fa7
+0x13 0x1cf9b
+0x13 0x18f8f
+0x13 0x1478f
+0x13 0x10692
+0x13 0x0c399
+0x13 0x0838d
+0x13 0x04199
+0x13 0x0018d
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GM_channel
+0x18 0x37564
+0x00 0x70000
+//5GM_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GM_TX_gain_table_intPA
+0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power
+0x13 0x24fb3
+0x13 0x20fa7
+0x13 0x1cf9b
+0x13 0x18f8f
+0x13 0x1478f
+0x13 0x10692
+0x13 0x0c399
+0x13 0x0838d
+0x13 0x04199
+0x13 0x0018d
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GH_channel
+0x18 0x57595
+0x00 0x70000
+//5GH_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GH_TX_gain_table_intPA
+0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power
+0x13 0x24fb3
+0x13 0x20fa7
+0x13 0x1cf9b
+0x13 0x18f8f
+0x13 0x1478f
+0x13 0x10692
+0x13 0x0c399
+0x13 0x0838d
+0x13 0x04199
+0x13 0x0018d
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+// 5G_IMR_tank_start
+0x30 0x4470f
+0x31 0x44ff0
+0x32 0x00070
+0x33 0xdd480
+0x34 0xffac0
+0x35 0xb80c0
+0x36 0x77000
+0x37 0x64ff2
+0x38 0xe7661
+0x39 0x00e90
+//end
+
+0x00 0x30000
+0x18 0x0f401 //2G channel
+0xfe
+0xfe
+0x1e 0x88009
+0x1f 0x80003
+0xfe
+0x1e 0x88001
+0x1f 0x80000
+0xfe
+//Rewrite Syn-table
+0x18 0x97524 //for DMSP EVM [bit19]=1
+0xfe
+0xfe
+0xfe
+0xfe
+0x2b 0x41289
+0xfe
+0x2d 0x6aaaa
+0x2e 0xb4d01
+0x2d 0x80000
+0x2e 0x04d02
+0x2d 0x95555
+0x2e 0x54d03
+0x2d 0xaaaaa
+0x2e 0xb4d04
+0x2d 0xc0000
+0x2e 0x04d05
+0x2d 0xd5555
+0x2e 0x54d06
+0x2d 0xeaaaa
+0x2e 0xb4d07
+0x2d 0x00000
+0x2e 0x05108
+0x2d 0x15555
+0x2e 0x55109
+0x2d 0x2aaaa
+0x2e 0xb510a
+0x2d 0x40000
+0x2e 0x0510b
+0x2d 0x55555
+0x2e 0x5510c
+//end
+//0x18 0x17524
+0xff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_new.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_new.txt new file mode 100644 index 000000000..2588184a7 --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_a_intPA_new.txt @@ -0,0 +1,244 @@ +//100909
+0x00 0x30000 //HSSI_AGC
+0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN
+0x02 0x00000 //2G_TXIQGEN
+0x03 0x18c63
+0x04 0x18c63 //0x70000
+//0x05 0xfd800 //HSSI_power_control
+//0x06 0xf001c //HSSI_2G_5G_RX_gain_control
+//0x07 0x3c800 //HSSI_TX_gain_control
+0x08 0x84000 //2G_LO_leakage
+0x0b 0x1c000 //24000//2G_5G_TX_PA
+0x0e 0x18c67 //APK default 0x18c63
+0x0f 0x00851 //2G_TXRX_IQGEN
+0x14 0x21440 //TX_bias_table_I
+//0x15 0x00430 //TX_IPA_table
+//0x16 0xe0332 //TX_bias_table_II
+//0x17 0xf0000 //HSSI_SYN2_power_control
+0x18 0x17524 //channel_band_control
+0x19 0x00000 //TRXIQ control
+0x1d 0xa1290 //RXBB_contorl
+//0x22 0x00000
+0x23 0x01558 //TXBB_control
+//0x24 0x00000
+//0x3d 0x00000
+//0x3e 0x00000
+//0x3f 0x00000
+//0x42 0x08400 //thermal meter
+
+//2G_RFE_control
+0x1a 0x30a99
+0x1b 0x40b00
+0x1c 0xfc339
+//5G_RFE_control
+0x3a 0xa57eb //0xfd7eb
+0x3b 0x20000 //0xe0000
+0x3c 0xff454 //0xff7d4
+//2G_TX_RFE_control
+0x20 0x0aa52
+0x21 0x54000
+//5G_TX_RFE_control
+0x40 0x0aa52
+0x41 0x14000
+//SYN control
+0x25 0x803be
+0x26 0xfc638
+0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting
+0x28 0xde471 //0xed531 for 2G //0xed771 for 5G // SYN loop setting
+0x29 0xd7110
+0x2a 0x8eb04 //for Tx 40M spur//0x8cb04
+0x2b 0x4128b
+0x2c 0x01840
+//0x2f 0x22ff0
+//2G_PA_control
+0x43 0x2444f
+0x44 0x1adb0
+0x45 0x56467
+0x46 0x8992c
+0x47 0x0452c
+//5G_PA_control_intPA
+0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443
+0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730
+0x4a 0x50f0f
+0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee
+0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee
+
+////2G_table_start////
+0x18 0x07401
+0x00 0x70000
+//2G_RX_gain_table
+0x12 0xdc000
+0x12 0x90000
+0x12 0x51000
+0x12 0x12000
+//2G_TX_gain_table
+0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40
+0x13 0x247ab
+0x13 0x2079f
+0x13 0x1c793
+0x13 0x1839f
+0x13 0x14396
+0x13 0x1019e
+0x13 0x0c195
+0x13 0x08198
+0x13 0x040a4
+0x13 0x0001c
+//2G_IPA_bias_table
+0x15 0x0f424
+0x15 0x4f424
+0x15 0x8f424
+//2G_TX_table_II
+0x16 0xe1330 //High gain
+0x16 0xa1330 //middle gain
+0x16 0x61330 //low gain
+0x16 0x21330 //ultra low gain
+
+
+////5G_table_start////
+//5GL_channel
+0x18 0x17524
+0x00 0x70000
+//5GL_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GL_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x10399
+0x13 0x0c38d
+0x13 0x08199
+0x13 0x0418d
+0x13 0x00099
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GM_channel
+0x18 0x37564
+0x00 0x70000
+//5GM_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GM_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x10399
+0x13 0x0c38d
+0x13 0x08199
+0x13 0x0418d
+0x13 0x00099
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GH_channel
+0x18 0x57595
+0x00 0x70000
+//5GH_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GH_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x10399 //0x1039d //0x10399
+0x13 0x0c38d //0x0c399 //0x0c38d
+0x13 0x08199 //0x0819d //0x08199
+0x13 0x0418d //0x04199 //0x0418d
+0x13 0x00099 //0x00099 //0x00099
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+// 5G_IMR_tank_start
+0x30 0x4470f
+0x31 0x44ff0
+0x32 0x00070
+0x33 0xdd480
+0x34 0xffac0
+0x35 0xb80c0
+0x36 0x77000
+0x37 0x64ff2
+0x38 0xe7661
+0x39 0x00e90
+//end
+
+0x00 0x30000
+0x18 0x0f401 //2G channel
+0xfe
+0xfe
+0x1e 0x88009
+0x1f 0x80003
+0xfe
+0x1e 0x88001
+0x1f 0x80000
+0xfe
+//Rewrite Syn-table
+0x18 0x97524 //for DMSP EVM [bit19]=1
+0xfe
+0xfe
+0xfe
+0xfe
+0x2b 0x41289
+0xfe
+0x2d 0x6aaaa
+0x2e 0xb4d01
+0x2d 0x80000
+0x2e 0x04d02
+0x2d 0x95555
+0x2e 0x54d03
+0x2d 0xaaaaa
+0x2e 0xb4d04
+0x2d 0xc0000
+0x2e 0x04d05
+0x2d 0xd5555
+0x2e 0x54d06
+0x2d 0xeaaaa
+0x2e 0xb4d07
+0x2d 0x00000
+0x2e 0x05108
+0x2d 0x15555
+0x2e 0x55109
+0x2d 0x2aaaa
+0x2e 0xb510a
+0x2d 0x40000
+0x2e 0x0510b
+0x2d 0x55555
+0x2e 0x5510c
+//end
+//0x18 0x17524
+0xff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_GM_new.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_GM_new.txt new file mode 100644 index 000000000..5a9c4e9a3 --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_GM_new.txt @@ -0,0 +1,247 @@ +//100909
+0x00 0x30000 //HSSI_AGC
+0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN
+0x02 0x00000 //2G_TXIQGEN
+0x03 0x18c63
+0x04 0x18c63 //0x70000
+//0x05 0xfd800 //HSSI_power_control
+//0x06 0xf001c //HSSI_2G_5G_RX_gain_control
+//0x07 0x3c800 //HSSI_TX_gain_control
+0x08 0x84000 //2G_LO_leakage
+0x0b 0x1c000 //24000//2G_5G_TX_PA
+0x0e 0x18c67 //APK default 0x18c63
+0x0f 0x00851 //2G_TXRX_IQGEN
+0x14 0x21440 //TX_bias_table_I
+//0x15 0x00430 //TX_IPA_table
+//0x16 0xe0332 //TX_bias_table_II
+//0x17 0x90000 //HSSI_SYN2_power_control
+0x18 0x07401 //channel_band_control
+0x19 0x00060 //TRXIQ control
+0x1d 0xa1290 //RXBB_contorl
+//0x22 0x00000
+0x23 0x01558 //TXBB_control
+//0x24 0x00000
+//0x3d 0x00000
+//0x3e 0x00000
+//0x3f 0x00000
+//0x42 0x08400 //thermal meter
+
+//2G_RFE_control
+0x1a 0x30a99
+0x1b 0x40b00
+0x1c 0xfc339
+//5G_RFE_control
+0x3a 0xa57eb
+0x3b 0x20000
+0x3c 0xff454 //0xff7d4
+//2G_TX_RFE_control
+0x20 0x0aa52
+0x21 0x54000
+//5G_TX_RFE_control
+0x40 0x0aa52
+0x41 0x14000
+//SYN control
+0x25 0x803be
+0x26 0xfc638
+0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting
+0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting
+0x29 0xd7110
+0x2a 0xaeb04 //for Tx 40M spur//0x8cb04
+0x2b 0x4128b
+0x2c 0x01840
+//0x2f 0x22ff0
+//2G_PA_control
+0x43 0x2444f
+0x44 0x1adb0
+0x45 0x56467
+0x46 0x8992c
+0x47 0x0452c
+//5G_PA_control_intPA
+0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443
+0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730
+0x4a 0x50f0f
+0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee
+0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee
+
+////2G_table_start////
+0x18 0x07401
+0x00 0x70000
+//2G_RX_gain_table
+0x12 0xdc000
+0x12 0x90000
+0x12 0x51000
+0x12 0x12000
+//2G_TX_gain_table
+0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40
+0x13 0x247ab
+0x13 0x2079f
+0x13 0x1c793
+0x13 0x1839f
+0x13 0x14396
+0x13 0x1019e
+0x13 0x0c195
+0x13 0x08198
+0x13 0x040a4
+0x13 0x0001c
+//2G_IPA_bias_table
+0x15 0x0f424
+0x15 0x4f424
+0x15 0x8f424
+//2G_TX_table_II
+0x16 0xe1330 //High gain
+0x16 0xa1330 //middle gain
+0x16 0x61330 //low gain
+0x16 0x21330 //ultra low gain
+
+
+////5G_table_start////
+//5GL_channel
+0x18 0x17524
+0x00 0x70000
+//5GL_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GL_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x103b9
+0x13 0x0c3ad
+0x13 0x081b9
+0x13 0x041ad
+0x13 0x000b9
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GM_channel
+0x18 0x37564
+0x00 0x70000
+//5GM_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GM_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x103b9
+0x13 0x0c3ad
+0x13 0x081b9
+0x13 0x041ad
+0x13 0x000b9
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GH_channel
+0x18 0x57595
+0x00 0x70000
+//5GH_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GH_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x103b9 //0x1039d //0x10399
+0x13 0x0c3ad //0x0c399 //0x0c38d
+0x13 0x081b9 //0x0819d //0x08199
+0x13 0x041ad //0x04199 //0x0418d
+0x13 0x000b9 //0x00099 //0x00099
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+// 5G_IMR_tank_start
+0x30 0x4470f
+0x31 0x44ff0
+0x32 0x00070
+0x33 0xdd480
+0x34 0xffac0
+0x35 0xb80c0
+0x36 0x77000
+0x37 0x64ff2
+0x38 0xe7661
+0x39 0x00e90
+//end
+
+0x00 0x30000
+0x18 0x0f401 //2G channel
+0xfe
+0xfe
+0x1e 0x88009
+0x1f 0x80003
+0xfe
+0x1e 0x88001
+0x1f 0x80000
+0xfe
+//Rewrite Syn-table
+0x18 0x87401 //for DMSP EVM [bit19]=1
+0xfe
+0xfe
+0xfe
+0x2b 0x41289 //02b4128b
+0xfe
+0x2d 0x66666
+0x2e 0x64001
+0x2d 0x91111
+0x2e 0x14002
+0x2d 0xbbbbb
+0x2e 0xb4003
+0x2d 0xe6666
+0x2e 0x64004
+0x2d 0x88888 //0x11111
+0x2e 0x84005 //0x14405
+0x2d 0x9dddd //0x3bbbb
+0x2e 0xd4006 //0xb4406
+0x2d 0xb3333 //0x66666
+0x2e 0x34007 //0x64407
+0x2d 0x48888 //0x91111
+0x2e 0x84408 //0x14408
+0x2d 0xbbbbb
+0x2e 0xb4409
+0x2d 0xe6666
+0x2e 0x6440a
+0x2d 0x11111
+0x2e 0x1480b
+0x2d 0x3bbbb
+0x2e 0xb480c
+0x2d 0x66666
+0x2e 0x6480d
+0x2d 0xccccc
+0x2e 0xc480e
+//end
+//0x18 0x0f401 //2G channel
+0xff 0xffff
\ No newline at end of file diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_GM_new1.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_GM_new1.txt new file mode 100644 index 000000000..c530cb8ec --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_GM_new1.txt @@ -0,0 +1,247 @@ +//100909
+0x00 0x30000 //HSSI_AGC
+0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN
+0x02 0x00000 //2G_TXIQGEN
+0x03 0x18c63
+0x04 0x18c63 //0x70000
+//0x05 0xfd800 //HSSI_power_control
+//0x06 0xf001c //HSSI_2G_5G_RX_gain_control
+//0x07 0x3c800 //HSSI_TX_gain_control
+0x08 0x84000 //2G_LO_leakage
+0x0b 0x1c000 //24000//2G_5G_TX_PA
+0x0e 0x18c67 //APK default 0x18c63
+0x0f 0x00851 //2G_TXRX_IQGEN
+0x14 0x21440 //TX_bias_table_I
+//0x15 0x00430 //TX_IPA_table
+//0x16 0xe0332 //TX_bias_table_II
+//0x17 0x90000 //HSSI_SYN2_power_control
+0x18 0x07401 //channel_band_control
+0x19 0x00060 //TRXIQ control
+0x1d 0xa1290 //RXBB_contorl
+//0x22 0x00000
+0x23 0x01558 //TXBB_control
+//0x24 0x00000
+//0x3d 0x00000
+//0x3e 0x00000
+//0x3f 0x00000
+//0x42 0x08400 //thermal meter
+
+//2G_RFE_control
+0x1a 0x30a99
+0x1b 0x40b00
+0x1c 0xfc339
+//5G_RFE_control
+0x3a 0xa57eb
+0x3b 0x20000
+0x3c 0xff454 //0xff7d4
+//2G_TX_RFE_control
+0x20 0x0aa52
+0x21 0x54000
+//5G_TX_RFE_control
+0x40 0x0aa52
+0x41 0x14000
+//SYN control
+0x25 0x803be
+0x26 0xfc638
+0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting
+0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting
+0x29 0xd7110
+0x2a 0xaeb04 //for Tx 40M spur//0x8cb04
+0x2b 0x4128b
+0x2c 0x01840
+//0x2f 0x22ff0
+//2G_PA_control
+0x43 0x2444f
+0x44 0x1adb0
+0x45 0x56467
+0x46 0x8992c
+0x47 0x0452c
+//5G_PA_control_intPA
+0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443
+0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730
+0x4a 0x50f0f
+0x4b 0x896ef //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee
+0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee
+
+////2G_table_start////
+0x18 0x07401
+0x00 0x70000
+//2G_RX_gain_table
+0x12 0xdc000
+0x12 0x90000
+0x12 0x51000
+0x12 0x12000
+//2G_TX_gain_table
+0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40
+0x13 0x247ab
+0x13 0x2079f
+0x13 0x1c793
+0x13 0x1839f
+0x13 0x14396
+0x13 0x1019e
+0x13 0x0c195
+0x13 0x08198
+0x13 0x040a4
+0x13 0x0001c
+//2G_IPA_bias_table
+0x15 0x0f424
+0x15 0x4f424
+0x15 0x8f424
+//2G_TX_table_II
+0x16 0xe1330 //High gain
+0x16 0xa1330 //middle gain
+0x16 0x61330 //low gain
+0x16 0x21330 //ultra low gain
+
+
+////5G_table_start////
+//5GL_channel
+0x18 0x17524
+0x00 0x70000
+//5GL_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GL_TX_gain_table_intPA
+0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power
+0x13 0x24fb3
+0x13 0x20fa7
+0x13 0x1cf9b
+0x13 0x18f8f
+0x13 0x1478f
+0x13 0x10692
+0x13 0x0c399
+0x13 0x0838d
+0x13 0x04199
+0x13 0x0018d
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GM_channel
+0x18 0x37564
+0x00 0x70000
+//5GM_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GM_TX_gain_table_intPA
+0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power
+0x13 0x24fb3
+0x13 0x20fa7
+0x13 0x1cf9b
+0x13 0x18f8f
+0x13 0x1478f
+0x13 0x10692
+0x13 0x0c399
+0x13 0x0838d
+0x13 0x04199
+0x13 0x0018d
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GH_channel
+0x18 0x57595
+0x00 0x70000
+//5GH_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GH_TX_gain_table_intPA
+0x13 0x28fbf //2011.10.18 Anchin Fix to increase tx power
+0x13 0x24fb3
+0x13 0x20fa7
+0x13 0x1cf9b
+0x13 0x18f8f
+0x13 0x1478f
+0x13 0x10692
+0x13 0x0c399
+0x13 0x0838d
+0x13 0x04199
+0x13 0x0018d
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+// 5G_IMR_tank_start
+0x30 0x4470f
+0x31 0x44ff0
+0x32 0x00070
+0x33 0xdd480
+0x34 0xffac0
+0x35 0xb80c0
+0x36 0x77000
+0x37 0x64ff2
+0x38 0xe7661
+0x39 0x00e90
+//end
+
+0x00 0x30000
+0x18 0x0f401 //2G channel
+0xfe
+0xfe
+0x1e 0x88009
+0x1f 0x80003
+0xfe
+0x1e 0x88001
+0x1f 0x80000
+0xfe
+//Rewrite Syn-table
+0x18 0x87401 //for DMSP EVM [bit19]=1
+0xfe
+0xfe
+0xfe
+0x2b 0x41289 //02b4128b
+0xfe
+0x2d 0x66666
+0x2e 0x64001
+0x2d 0x91111
+0x2e 0x14002
+0x2d 0xbbbbb
+0x2e 0xb4003
+0x2d 0xe6666
+0x2e 0x64004
+0x2d 0x88888 //0x11111
+0x2e 0x84005 //0x14405
+0x2d 0x9dddd //0x3bbbb
+0x2e 0xd4006 //0xb4406
+0x2d 0xb3333 //0x66666
+0x2e 0x34007 //0x64407
+0x2d 0x48888 //0x91111
+0x2e 0x84408 //0x14408
+0x2d 0xbbbbb
+0x2e 0xb4409
+0x2d 0xe6666
+0x2e 0x6440a
+0x2d 0x11111
+0x2e 0x1480b
+0x2d 0x3bbbb
+0x2e 0xb480c
+0x2d 0x66666
+0x2e 0x6480d
+0x2d 0xccccc
+0x2e 0xc480e
+//end
+//0x18 0x0f401 //2G channel
+0xff 0xffff
\ No newline at end of file diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_new.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_new.txt new file mode 100644 index 000000000..8d54f7a97 --- /dev/null +++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192cd/data_92d/radio_b_intPA_new.txt @@ -0,0 +1,247 @@ +//100909
+0x00 0x30000 //HSSI_AGC
+0x01 0x30000 //2G_RXIQGEN//2G_TXIQGEN
+0x02 0x00000 //2G_TXIQGEN
+0x03 0x18c63
+0x04 0x18c63 //0x70000
+//0x05 0xfd800 //HSSI_power_control
+//0x06 0xf001c //HSSI_2G_5G_RX_gain_control
+//0x07 0x3c800 //HSSI_TX_gain_control
+0x08 0x84000 //2G_LO_leakage
+0x0b 0x1c000 //24000//2G_5G_TX_PA
+0x0e 0x18c67 //APK default 0x18c63
+0x0f 0x00851 //2G_TXRX_IQGEN
+0x14 0x21440 //TX_bias_table_I
+//0x15 0x00430 //TX_IPA_table
+//0x16 0xe0332 //TX_bias_table_II
+//0x17 0x90000 //HSSI_SYN2_power_control
+0x18 0x07401 //channel_band_control
+0x19 0x00060 //TRXIQ control
+0x1d 0xa1290 //RXBB_contorl
+//0x22 0x00000
+0x23 0x01558 //TXBB_control
+//0x24 0x00000
+//0x3d 0x00000
+//0x3e 0x00000
+//0x3f 0x00000
+//0x42 0x08400 //thermal meter
+
+//2G_RFE_control
+0x1a 0x30a99
+0x1b 0x40b00
+0x1c 0xfc339
+//5G_RFE_control
+0x3a 0xa57eb
+0x3b 0x20000
+0x3c 0xff454 //0xff7d4
+//2G_TX_RFE_control
+0x20 0x0aa52
+0x21 0x54000
+//5G_TX_RFE_control
+0x40 0x0aa52
+0x41 0x14000
+//SYN control
+0x25 0x803be
+0x26 0xfc638
+0x27 0x77c18 //0x77c18 for 2G //0x07c08/0x77c58 for 5G 40M/20M,//0x7b858 // SYN loop setting
+0x28 0xd1c31 //0xed531 for 2G //0xed571 for 5G // SYN loop setting
+0x29 0xd7110
+0x2a 0xaeb04 //for Tx 40M spur//0x8cb04
+0x2b 0x4128b
+0x2c 0x01840
+//0x2f 0x22ff0
+//2G_PA_control
+0x43 0x2444f
+0x44 0x1adb0
+0x45 0x56467
+0x46 0x8992c
+0x47 0x0452c
+//5G_PA_control_intPA
+0x48 0xc0443 //5GL/5GM/5GH = 0x40443 /0xc0443 /0xc0443
+0x49 0x00730 //5GL/5GM/5GH = 0x00eb5 /0x00730 /0x00730
+0x4a 0x50f0f
+0x4b 0x896ee //5GL/5GM/5GH = 0x89bec /0x896ee /0x896ee
+0x4c 0x0ddee // per PAD Gain=101/110, 0x0dded/0x0ddee
+
+////2G_table_start////
+0x18 0x07401
+0x00 0x70000
+//2G_RX_gain_table
+0x12 0xdc000
+0x12 0x90000
+0x12 0x51000
+0x12 0x12000
+//2G_TX_gain_table
+0x13 0x287b7 //2011.10.18 Anchin Fix for Gap between 39 &40
+0x13 0x247ab
+0x13 0x2079f
+0x13 0x1c793
+0x13 0x1839f
+0x13 0x14396
+0x13 0x1019e
+0x13 0x0c195
+0x13 0x08198
+0x13 0x040a4
+0x13 0x0001c
+//2G_IPA_bias_table
+0x15 0x0f424
+0x15 0x4f424
+0x15 0x8f424
+//2G_TX_table_II
+0x16 0xe1330 //High gain
+0x16 0xa1330 //middle gain
+0x16 0x61330 //low gain
+0x16 0x21330 //ultra low gain
+
+
+////5G_table_start////
+//5GL_channel
+0x18 0x17524
+0x00 0x70000
+//5GL_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GL_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x10399
+0x13 0x0c38d
+0x13 0x08199
+0x13 0x0418d
+0x13 0x00099
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GM_channel
+0x18 0x37564
+0x00 0x70000
+//5GM_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GM_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x10399
+0x13 0x0c38d
+0x13 0x08199
+0x13 0x0418d
+0x13 0x00099
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+
+//5GH_channel
+0x18 0x57595
+0x00 0x70000
+//5GH_RX_gain_table
+0x12 0xcf000
+0x12 0xbc000
+0x12 0x78000
+0x12 0x00000
+//5GH_TX_gain_table_intPA
+0x13 0x287bf
+0x13 0x247b3
+0x13 0x207a7
+0x13 0x1c79b
+0x13 0x1839f
+0x13 0x14393
+0x13 0x10399 //0x1039d //0x10399
+0x13 0x0c38d //0x0c399 //0x0c38d
+0x13 0x08199 //0x0819d //0x08199
+0x13 0x0418d //0x04199 //0x0418d
+0x13 0x00099 //0x00099 //0x00099
+//5G_IPA_bias_table_intPA
+0x15 0x0f495
+0x15 0x4f495
+0x15 0x8f495
+//5G_TX_table_II_intPA
+0x16 0xe1874 //High gain
+0x16 0xa1874 //middle gain
+0x16 0x61874 //low gain
+0x16 0x21874 //ultra low gain
+// 5G_IMR_tank_start
+0x30 0x4470f
+0x31 0x44ff0
+0x32 0x00070
+0x33 0xdd480
+0x34 0xffac0
+0x35 0xb80c0
+0x36 0x77000
+0x37 0x64ff2
+0x38 0xe7661
+0x39 0x00e90
+//end
+
+0x00 0x30000
+0x18 0x0f401 //2G channel
+0xfe
+0xfe
+0x1e 0x88009
+0x1f 0x80003
+0xfe
+0x1e 0x88001
+0x1f 0x80000
+0xfe
+//Rewrite Syn-table
+0x18 0x87401 //for DMSP EVM [bit19]=1
+0xfe
+0xfe
+0xfe
+0x2b 0x41289 //02b4128b
+0xfe
+0x2d 0x66666
+0x2e 0x64001
+0x2d 0x91111
+0x2e 0x14002
+0x2d 0xbbbbb
+0x2e 0xb4003
+0x2d 0xe6666
+0x2e 0x64004
+0x2d 0x88888 //0x11111
+0x2e 0x84005 //0x14405
+0x2d 0x9dddd //0x3bbbb
+0x2e 0xd4006 //0xb4406
+0x2d 0xb3333 //0x66666
+0x2e 0x34007 //0x64407
+0x2d 0x48888 //0x91111
+0x2e 0x84408 //0x14408
+0x2d 0xbbbbb
+0x2e 0xb4409
+0x2d 0xe6666
+0x2e 0x6440a
+0x2d 0x11111
+0x2e 0x1480b
+0x2d 0x3bbbb
+0x2e 0xb480c
+0x2d 0x66666
+0x2e 0x6480d
+0x2d 0xccccc
+0x2e 0xc480e
+//end
+//0x18 0x0f401 //2G channel
+0xff 0xffff
\ No newline at end of file |