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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2009-10-04 19:53:17 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2009-10-04 19:53:17 +0000
commit8fb9ab479d4b4df9d66ea4f2f92fa7cf7ff43db5 (patch)
tree00a7ec1f4de21518bc2c783975daa58de2885ed1 /target/linux/ramips/files/arch/mips/include
parent63e4465014fd73e1b059cab09ed4a4c6466e1d72 (diff)
adds pci support for rt288x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17855 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include')
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_pci.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_pci.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_pci.h
new file mode 100644
index 000000000..f73d7ac15
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_pci.h
@@ -0,0 +1,19 @@
+
+#ifdef CONFIG_PCI
+
+#define RT2880_PCI_SLOT1_BASE 0x20000000
+#define RALINK_PCI_BASE 0xA0440000
+#define RT2880_PCI_PCICFG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0000))
+#define RT2880_PCI_ARBCTL ((unsigned long*)(RALINK_PCI_BASE + 0x0080))
+#define RT2880_PCI_BAR0SETUP_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0010))
+#define RT2880_PCI_CONFIG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0020))
+#define RT2880_PCI_CONFIG_DATA ((unsigned long*)(RALINK_PCI_BASE + 0x0024))
+#define RT2880_PCI_MEMBASE ((unsigned long*)(RALINK_PCI_BASE + 0x0028))
+#define RT2880_PCI_IOBASE ((unsigned long*)(RALINK_PCI_BASE + 0x002C))
+#define RT2880_PCI_IMBASEBAR0_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0018))
+#define RT2880_PCI_ID ((unsigned long*)(RALINK_PCI_BASE + 0x0030))
+#define RT2880_PCI_CLASS ((unsigned long*)(RALINK_PCI_BASE + 0x0034))
+#define RT2880_PCI_SUBID ((unsigned long*)(RALINK_PCI_BASE + 0x0038))
+#define RT2880_PCI_PCIMSK_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x000C))
+
+#endif