[lantiq] move files/ -> files-3.3/

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34060 3c298f89-4303-0410-b956-a3cf2f4a3e73

3 files changed, 0 insertions, 438 deletions

diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
deleted file mode 100644
index 4dc6466e8..000000000
--- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
- */
-
-#ifndef _FALCON_IRQ__
-#define _FALCON_IRQ__
-
-#define INT_NUM_IRQ0			8
-#define INT_NUM_IM0_IRL0		(INT_NUM_IRQ0 + 0)
-#define INT_NUM_IM1_IRL0		(INT_NUM_IM0_IRL0 + 32)
-#define INT_NUM_IM2_IRL0		(INT_NUM_IM1_IRL0 + 32)
-#define INT_NUM_IM3_IRL0		(INT_NUM_IM2_IRL0 + 32)
-#define INT_NUM_IM4_IRL0		(INT_NUM_IM3_IRL0 + 32)
-#define INT_NUM_EXTRA_START		(INT_NUM_IM4_IRL0 + 32)
-#define INT_NUM_IM_OFFSET		(INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
-
-#define MIPS_CPU_TIMER_IRQ			7
-
-/* HOST IF Event Interrupt */
-#define FALCON_IRQ_HOST				(INT_NUM_IM0_IRL0 + 0)
-/* HOST IF Mailbox0 Receive Interrupt */
-#define FALCON_IRQ_HOST_MB0_RX			(INT_NUM_IM0_IRL0 + 1)
-/* HOST IF Mailbox0 Transmit Interrupt */
-#define FALCON_IRQ_HOST_MB0_TX			(INT_NUM_IM0_IRL0 + 2)
-/* HOST IF Mailbox1 Receive Interrupt */
-#define FALCON_IRQ_HOST_MB1_RX			(INT_NUM_IM0_IRL0 + 3)
-/* HOST IF Mailbox1 Transmit Interrupt */
-#define FALCON_IRQ_HOST_MB1_TX			(INT_NUM_IM0_IRL0 + 4)
-/* I2C Last Single Data Transfer Request */
-#define FALCON_IRQ_I2C_LSREQ			(INT_NUM_IM0_IRL0 + 8)
-/* I2C Single Data Transfer Request */
-#define FALCON_IRQ_I2C_SREQ			(INT_NUM_IM0_IRL0 + 9)
-/* I2C Last Burst Data Transfer Request */
-#define FALCON_IRQ_I2C_LBREQ			(INT_NUM_IM0_IRL0 + 10)
-/* I2C Burst Data Transfer Request */
-#define FALCON_IRQ_I2C_BREQ			(INT_NUM_IM0_IRL0 + 11)
-/* I2C Error Interrupt */
-#define FALCON_IRQ_I2C_I2C_ERR			(INT_NUM_IM0_IRL0 + 12)
-/* I2C Protocol Interrupt */
-#define FALCON_IRQ_I2C_I2C_P			(INT_NUM_IM0_IRL0 + 13)
-/* SSC Transmit Interrupt */
-#define FALCON_IRQ_SSC_T			(INT_NUM_IM0_IRL0 + 14)
-/* SSC Receive Interrupt */
-#define FALCON_IRQ_SSC_R			(INT_NUM_IM0_IRL0 + 15)
-/* SSC Error Interrupt */
-#define FALCON_IRQ_SSC_E			(INT_NUM_IM0_IRL0 + 16)
-/* SSC Frame Interrupt */
-#define FALCON_IRQ_SSC_F			(INT_NUM_IM0_IRL0 + 17)
-/* Advanced Encryption Standard Interrupt */
-#define FALCON_IRQ_AES_AES			(INT_NUM_IM0_IRL0 + 27)
-/* Secure Hash Algorithm Interrupt */
-#define FALCON_IRQ_SHA_HASH			(INT_NUM_IM0_IRL0 + 28)
-/* PCM Receive Interrupt */
-#define FALCON_IRQ_PCM_RX			(INT_NUM_IM0_IRL0 + 29)
-/* PCM Transmit Interrupt */
-#define FALCON_IRQ_PCM_TX			(INT_NUM_IM0_IRL0 + 30)
-/* PCM Transmit Crash Interrupt */
-#define FALCON_IRQ_PCM_HW2_CRASH		(INT_NUM_IM0_IRL0 + 31)
-
-/* EBU Serial Flash Command Error */
-#define FALCON_IRQ_EBU_SF_CMDERR		(INT_NUM_IM1_IRL0 + 0)
-/* EBU Serial Flash Command Overwrite Error */
-#define FALCON_IRQ_EBU_SF_COVERR		(INT_NUM_IM1_IRL0 + 1)
-/* EBU Serial Flash Busy */
-#define FALCON_IRQ_EBU_SF_BUSY			(INT_NUM_IM1_IRL0 + 2)
-/* External Interrupt from GPIO P0 */
-#define FALCON_IRQ_GPIO_P0			(INT_NUM_IM1_IRL0 + 4)
-/* External Interrupt from GPIO P1 */
-#define FALCON_IRQ_GPIO_P1			(INT_NUM_IM1_IRL0 + 5)
-/* External Interrupt from GPIO P2 */
-#define FALCON_IRQ_GPIO_P2			(INT_NUM_IM1_IRL0 + 6)
-/* External Interrupt from GPIO P3 */
-#define FALCON_IRQ_GPIO_P3			(INT_NUM_IM1_IRL0 + 7)
-/* External Interrupt from GPIO P4 */
-#define FALCON_IRQ_GPIO_P4			(INT_NUM_IM1_IRL0 + 8)
-/* 8kHz backup interrupt derived from core-PLL */
-#define FALCON_IRQ_FSC_BKP			(INT_NUM_IM1_IRL0 + 10)
-/* FSC Timer Interrupt 0 */
-#define FALCON_IRQ_FSCT_CMP0			(INT_NUM_IM1_IRL0 + 11)
-/* FSC Timer Interrupt 1 */
-#define FALCON_IRQ_FSCT_CMP1			(INT_NUM_IM1_IRL0 + 12)
-/* 8kHz root interrupt derived from GPON interface */
-#define FALCON_IRQ_FSC_ROOT			(INT_NUM_IM1_IRL0 + 13)
-/* Time of Day */
-#define FALCON_IRQ_TOD				(INT_NUM_IM1_IRL0 + 14)
-/* PMA Interrupt from IntNode of the 200MHz Domain */
-#define FALCON_IRQ_PMA_200M			(INT_NUM_IM1_IRL0 + 15)
-/* PMA Interrupt from IntNode of the TX Clk Domain */
-#define FALCON_IRQ_PMA_TX			(INT_NUM_IM1_IRL0 + 16)
-/* PMA Interrupt from IntNode of the RX Clk Domain */
-#define FALCON_IRQ_PMA_RX			(INT_NUM_IM1_IRL0 + 17)
-/* SYS1 Interrupt */
-#define FALCON_IRQ_SYS1				(INT_NUM_IM1_IRL0 + 20)
-/* SYS GPE Interrupt */
-#define FALCON_IRQ_SYS_GPE			(INT_NUM_IM1_IRL0 + 21)
-/* Watchdog Access Error Interrupt */
-#define FALCON_IRQ_WDT_AEIR			(INT_NUM_IM1_IRL0 + 24)
-/* Watchdog Prewarning Interrupt */
-#define FALCON_IRQ_WDT_PIR			(INT_NUM_IM1_IRL0 + 25)
-/* SBIU interrupt */
-#define FALCON_IRQ_SBIU0			(INT_NUM_IM1_IRL0 + 27)
-/* FPI Bus Control Unit Interrupt */
-#define FALCON_IRQ_BCU0				(INT_NUM_IM1_IRL0 + 29)
-/* DDR Controller Interrupt */
-#define FALCON_IRQ_DDR				(INT_NUM_IM1_IRL0 + 30)
-/* Crossbar Error Interrupt */
-#define FALCON_IRQ_XBAR_ERROR			(INT_NUM_IM1_IRL0 + 31)
-
-/* ICTRLL 0 Interrupt */
-#define FALCON_IRQ_ICTRLL0			(INT_NUM_IM2_IRL0 + 0)
-/* ICTRLL 1 Interrupt */
-#define FALCON_IRQ_ICTRLL1			(INT_NUM_IM2_IRL0 + 1)
-/* ICTRLL 2 Interrupt */
-#define FALCON_IRQ_ICTRLL2			(INT_NUM_IM2_IRL0 + 2)
-/* ICTRLL 3 Interrupt */
-#define FALCON_IRQ_ICTRLL3			(INT_NUM_IM2_IRL0 + 3)
-/* OCTRLL 0 Interrupt */
-#define FALCON_IRQ_OCTRLL0			(INT_NUM_IM2_IRL0 + 4)
-/* OCTRLL 1 Interrupt */
-#define FALCON_IRQ_OCTRLL1			(INT_NUM_IM2_IRL0 + 5)
-/* OCTRLL 2 Interrupt */
-#define FALCON_IRQ_OCTRLL2			(INT_NUM_IM2_IRL0 + 6)
-/* OCTRLL 3 Interrupt */
-#define FALCON_IRQ_OCTRLL3			(INT_NUM_IM2_IRL0 + 7)
-/* OCTRLG Interrupt */
-#define FALCON_IRQ_OCTRLG			(INT_NUM_IM2_IRL0 + 9)
-/* IQM Interrupt */
-#define FALCON_IRQ_IQM				(INT_NUM_IM2_IRL0 + 10)
-/* FSQM Interrupt */
-#define FALCON_IRQ_FSQM				(INT_NUM_IM2_IRL0 + 11)
-/* TMU Interrupt */
-#define FALCON_IRQ_TMU				(INT_NUM_IM2_IRL0 + 12)
-/* LINK1 Interrupt */
-#define FALCON_IRQ_LINK1			(INT_NUM_IM2_IRL0 + 14)
-/* ICTRLC 0 Interrupt */
-#define FALCON_IRQ_ICTRLC0			(INT_NUM_IM2_IRL0 + 16)
-/* ICTRLC 1 Interrupt */
-#define FALCON_IRQ_ICTRLC1			(INT_NUM_IM2_IRL0 + 17)
-/* OCTRLC Interrupt */
-#define FALCON_IRQ_OCTRLC			(INT_NUM_IM2_IRL0 + 18)
-/* CONFIG Break Interrupt */
-#define FALCON_IRQ_CONFIG_BREAK			(INT_NUM_IM2_IRL0 + 19)
-/* CONFIG Interrupt */
-#define FALCON_IRQ_CONFIG			(INT_NUM_IM2_IRL0 + 20)
-/* Dispatcher Interrupt */
-#define FALCON_IRQ_DISP				(INT_NUM_IM2_IRL0 + 21)
-/* TBM Interrupt */
-#define FALCON_IRQ_TBM				(INT_NUM_IM2_IRL0 + 22)
-/* GTC Downstream Interrupt */
-#define FALCON_IRQ_GTC_DS			(INT_NUM_IM2_IRL0 + 29)
-/* GTC Upstream Interrupt */
-#define FALCON_IRQ_GTC_US			(INT_NUM_IM2_IRL0 + 30)
-/* EIM Interrupt */
-#define FALCON_IRQ_EIM				(INT_NUM_IM2_IRL0 + 31)
-
-/* ASC0 Transmit Interrupt */
-#define FALCON_IRQ_ASC0_T			(INT_NUM_IM3_IRL0 + 0)
-/* ASC0 Receive Interrupt */
-#define FALCON_IRQ_ASC0_R			(INT_NUM_IM3_IRL0 + 1)
-/* ASC0 Error Interrupt */
-#define FALCON_IRQ_ASC0_E			(INT_NUM_IM3_IRL0 + 2)
-/* ASC0 Transmit Buffer Interrupt */
-#define FALCON_IRQ_ASC0_TB			(INT_NUM_IM3_IRL0 + 3)
-/* ASC0 Autobaud Start Interrupt */
-#define FALCON_IRQ_ASC0_ABST			(INT_NUM_IM3_IRL0 + 4)
-/* ASC0 Autobaud Detection Interrupt */
-#define FALCON_IRQ_ASC0_ABDET			(INT_NUM_IM3_IRL0 + 5)
-/* ASC1 Modem Status Interrupt */
-#define FALCON_IRQ_ASC0_MS			(INT_NUM_IM3_IRL0 + 6)
-/* ASC0 Soft Flow Control Interrupt */
-#define FALCON_IRQ_ASC0_SFC			(INT_NUM_IM3_IRL0 + 7)
-/* ASC1 Transmit Interrupt */
-#define FALCON_IRQ_ASC1_T			(INT_NUM_IM3_IRL0 + 8)
-/* ASC1 Receive Interrupt */
-#define FALCON_IRQ_ASC1_R			(INT_NUM_IM3_IRL0 + 9)
-/* ASC1 Error Interrupt */
-#define FALCON_IRQ_ASC1_E			(INT_NUM_IM3_IRL0 + 10)
-/* ASC1 Transmit Buffer Interrupt */
-#define FALCON_IRQ_ASC1_TB			(INT_NUM_IM3_IRL0 + 11)
-/* ASC1 Autobaud Start Interrupt */
-#define FALCON_IRQ_ASC1_ABST			(INT_NUM_IM3_IRL0 + 12)
-/* ASC1 Autobaud Detection Interrupt */
-#define FALCON_IRQ_ASC1_ABDET			(INT_NUM_IM3_IRL0 + 13)
-/* ASC1 Modem Status Interrupt */
-#define FALCON_IRQ_ASC1_MS			(INT_NUM_IM3_IRL0 + 14)
-/* ASC1 Soft Flow Control Interrupt */
-#define FALCON_IRQ_ASC1_SFC			(INT_NUM_IM3_IRL0 + 15)
-/* GPTC Timer/Counter 1A Interrupt */
-#define FALCON_IRQ_GPTC_TC1A			(INT_NUM_IM3_IRL0 + 16)
-/* GPTC Timer/Counter 1B Interrupt */
-#define FALCON_IRQ_GPTC_TC1B			(INT_NUM_IM3_IRL0 + 17)
-/* GPTC Timer/Counter 2A Interrupt */
-#define FALCON_IRQ_GPTC_TC2A			(INT_NUM_IM3_IRL0 + 18)
-/* GPTC Timer/Counter 2B Interrupt */
-#define FALCON_IRQ_GPTC_TC2B			(INT_NUM_IM3_IRL0 + 19)
-/* GPTC Timer/Counter 3A Interrupt */
-#define FALCON_IRQ_GPTC_TC3A			(INT_NUM_IM3_IRL0 + 20)
-/* GPTC Timer/Counter 3B Interrupt */
-#define FALCON_IRQ_GPTC_TC3B			(INT_NUM_IM3_IRL0 + 21)
-/* DFEV0, Channel 1 Transmit Interrupt */
-#define FALCON_IRQ_DFEV0_2TX			(INT_NUM_IM3_IRL0 + 26)
-/* DFEV0, Channel 1 Receive Interrupt */
-#define FALCON_IRQ_DFEV0_2RX			(INT_NUM_IM3_IRL0 + 27)
-/* DFEV0, Channel 1 General Purpose Interrupt */
-#define FALCON_IRQ_DFEV0_2GP			(INT_NUM_IM3_IRL0 + 28)
-/* DFEV0, Channel 0 Transmit Interrupt */
-#define FALCON_IRQ_DFEV0_1TX			(INT_NUM_IM3_IRL0 + 29)
-/* DFEV0, Channel 0 Receive Interrupt */
-#define FALCON_IRQ_DFEV0_1RX			(INT_NUM_IM3_IRL0 + 30)
-/* DFEV0, Channel 0 General Purpose Interrupt */
-#define FALCON_IRQ_DFEV0_1GP			(INT_NUM_IM3_IRL0 + 31)
-
-/* ICTRLL 0 Error */
-#define FALCON_IRQ_ICTRLL0_ERR			(INT_NUM_IM4_IRL0 + 0)
-/* ICTRLL 1 Error */
-#define FALCON_IRQ_ICTRLL1_ERR			(INT_NUM_IM4_IRL0 + 1)
-/* ICTRLL 2 Error */
-#define FALCON_IRQ_ICTRLL2_ERR			(INT_NUM_IM4_IRL0 + 2)
-/* ICTRLL 3 Error */
-#define FALCON_IRQ_ICTRLL3_ERR			(INT_NUM_IM4_IRL0 + 3)
-/* OCTRLL 0 Error */
-#define FALCON_IRQ_OCTRLL0_ERR			(INT_NUM_IM4_IRL0 + 4)
-/* OCTRLL 1 Error */
-#define FALCON_IRQ_OCTRLL1_ERR			(INT_NUM_IM4_IRL0 + 5)
-/* OCTRLL 2 Error */
-#define FALCON_IRQ_OCTRLL2_ERR			(INT_NUM_IM4_IRL0 + 6)
-/* OCTRLL 3 Error */
-#define FALCON_IRQ_OCTRLL3_ERR			(INT_NUM_IM4_IRL0 + 7)
-/* ICTRLG Error */
-#define FALCON_IRQ_ICTRLG_ERR			(INT_NUM_IM4_IRL0 + 8)
-/* OCTRLG Error */
-#define FALCON_IRQ_OCTRLG_ERR			(INT_NUM_IM4_IRL0 + 9)
-/* IQM Error */
-#define FALCON_IRQ_IQM_ERR			(INT_NUM_IM4_IRL0 + 10)
-/* FSQM Error */
-#define FALCON_IRQ_FSQM_ERR			(INT_NUM_IM4_IRL0 + 11)
-/* TMU Error */
-#define FALCON_IRQ_TMU_ERR			(INT_NUM_IM4_IRL0 + 12)
-/* MPS Status Interrupt #0 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR0			(INT_NUM_IM4_IRL0 + 14)
-/* MPS Status Interrupt #1 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR1			(INT_NUM_IM4_IRL0 + 15)
-/* MPS Status Interrupt #2 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR2			(INT_NUM_IM4_IRL0 + 16)
-/* MPS Status Interrupt #3 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR3			(INT_NUM_IM4_IRL0 + 17)
-/* MPS Status Interrupt #4 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR4			(INT_NUM_IM4_IRL0 + 18)
-/* MPS Status Interrupt #5 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR5			(INT_NUM_IM4_IRL0 + 19)
-/* MPS Status Interrupt #6 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR6			(INT_NUM_IM4_IRL0 + 20)
-/* MPS Status Interrupt #7 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR7			(INT_NUM_IM4_IRL0 + 21)
-/* MPS Status Interrupt #8 (VPE1 to VPE0) */
-#define FALCON_IRQ_MPS_IR8			(INT_NUM_IM4_IRL0 + 22)
-/* VPE0 Exception Level Flag Interrupt */
-#define FALCON_IRQ_VPE0_EXL			(INT_NUM_IM4_IRL0 + 29)
-/* VPE0 Error Level Flag Interrupt */
-#define FALCON_IRQ_VPE0_ERL			(INT_NUM_IM4_IRL0 + 30)
-/* VPE0 Performance Monitoring Counter Interrupt */
-#define FALCON_IRQ_VPE0_PMCIR			(INT_NUM_IM4_IRL0 + 31)
-
-#endif /* _FALCON_IRQ__ */
diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h
deleted file mode 100644
index 2caccd9f9..000000000
--- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
- */
-
-#ifndef __FALCON_IRQ_H
-#define __FALCON_IRQ_H
-
-#include <falcon_irq.h>
-
-#define NR_IRQS 328
-
-#include_next <irq.h>
-
-#endif
diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
deleted file mode 100644
index fff5ecdbe..000000000
--- a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#ifndef _LTQ_FALCON_H__
-#define _LTQ_FALCON_H__
-
-#ifdef CONFIG_SOC_FALCON
-
-#include <lantiq.h>
-
-/* Chip IDs */
-#define SOC_ID_FALCON		0x01B8
-
-/* SoC Types */
-#define SOC_TYPE_FALCON		0x01
-
-/* ASC0/1 - serial port */
-#define LTQ_ASC0_BASE_ADDR	0x1E100C00
-#define LTQ_ASC1_BASE_ADDR	0x1E100B00
-#define LTQ_ASC_SIZE		0x100
-
-#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8))
-#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1)
-#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2)
-
-/*
- * during early_printk no ioremap possible at this early stage
- * lets use KSEG1 instead
- */
-#define LTQ_EARLY_ASC		KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
-
-/* ICU - interrupt control unit */
-#define LTQ_ICU_BASE_ADDR	0x1F880200
-#define LTQ_ICU_SIZE		0x100
-
-/* WDT */
-#define LTQ_WDT_BASE_ADDR	0x1F8803F0
-#define LTQ_WDT_SIZE		0x10
-
-#define LTQ_RST_CAUSE_WDTRST	0x0002
-
-/* EBU - external bus unit */
-#define LTQ_EBU_BASE_ADDR       0x18000000
-#define LTQ_EBU_SIZE            0x0100
-
-#define LTQ_EBU_MODCON  0x000C
-
-/* GPIO */
-#define LTQ_GPIO0_BASE_ADDR     0x1D810000
-#define LTQ_GPIO0_SIZE          0x0080
-#define LTQ_GPIO1_BASE_ADDR     0x1E800100
-#define LTQ_GPIO1_SIZE          0x0080
-#define LTQ_GPIO2_BASE_ADDR     0x1D810100
-#define LTQ_GPIO2_SIZE          0x0080
-#define LTQ_GPIO3_BASE_ADDR     0x1E800200
-#define LTQ_GPIO3_SIZE          0x0080
-#define LTQ_GPIO4_BASE_ADDR     0x1E800300
-#define LTQ_GPIO4_SIZE          0x0080
-#define LTQ_PADCTRL0_BASE_ADDR  0x1DB01000
-#define LTQ_PADCTRL0_SIZE       0x0100
-#define LTQ_PADCTRL1_BASE_ADDR  0x1E800400
-#define LTQ_PADCTRL1_SIZE       0x0100
-#define LTQ_PADCTRL2_BASE_ADDR  0x1DB02000
-#define LTQ_PADCTRL2_SIZE       0x0100
-#define LTQ_PADCTRL3_BASE_ADDR  0x1E800500
-#define LTQ_PADCTRL3_SIZE       0x0100
-#define LTQ_PADCTRL4_BASE_ADDR  0x1E800600
-#define LTQ_PADCTRL4_SIZE       0x0100
-
-/* I2C */
-#define GPON_I2C_BASE		0x1E200000
-#define GPON_I2C_SIZE		0x00010000
-
-/* CHIP ID */
-#define LTQ_STATUS_BASE_ADDR	0x1E802000
-
-#define LTQ_FALCON_CHIPID	((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
-#define LTQ_FALCON_CHIPTYPE	((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
-#define LTQ_FALCON_CHIPCONF	((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
-
-/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
-#define LTQ_SYS1_BASE_ADDR      0x1EF00000
-#define LTQ_SYS1_SIZE           0x0100
-#define LTQ_STATUS_BASE_ADDR	0x1E802000
-#define LTQ_STATUS_SIZE		0x0080
-#define LTQ_SYS_ETH_BASE_ADDR	0x1DB00000
-#define LTQ_SYS_ETH_SIZE	0x0100
-#define LTQ_SYS_GPE_BASE_ADDR	0x1D700000
-#define LTQ_SYS_GPE_SIZE	0x0100
-
-#define SYSCTL_SYS1		0
-#define SYSCTL_SYSETH		1
-#define SYSCTL_SYSGPE		2
-
-/* Activation Status Register */
-#define ACTS_ASC1_ACT	0x00000800
-#define ACTS_I2C_ACT	0x00004000
-#define ACTS_P0		0x00010000
-#define ACTS_P1		0x00010000
-#define ACTS_P2		0x00020000
-#define ACTS_P3		0x00020000
-#define ACTS_P4		0x00040000
-#define ACTS_PADCTRL0	0x00100000
-#define ACTS_PADCTRL1	0x00100000
-#define ACTS_PADCTRL2	0x00200000
-#define ACTS_PADCTRL3	0x00200000
-#define ACTS_PADCTRL4	0x00400000
-#define ACTS_I2C_ACT	0x00004000
-
-/* global register ranges */
-extern __iomem void *ltq_ebu_membase;
-extern __iomem void *ltq_sys1_membase;
-#define ltq_ebu_w32(x, y)	ltq_w32((x), ltq_ebu_membase + (y))
-#define ltq_ebu_r32(x)		ltq_r32(ltq_ebu_membase + (x))
-#define ltq_ebu_w32_mask(clear, set, reg)   \
-	ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
-
-#define ltq_sys1_w32(x, y)	ltq_w32((x), ltq_sys1_membase + (y))
-#define ltq_sys1_r32(x)		ltq_r32(ltq_sys1_membase + (x))
-#define ltq_sys1_w32_mask(clear, set, reg)   \
-	ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
-
-/* gpio wrapper to help configure the pin muxing */
-extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
-
-/* to keep the irq code generic we need to define these to 0 as falcon
-   has no EIU/EBU */
-#define LTQ_EIU_BASE_ADDR	0
-#define LTQ_EBU_PCC_ISTAT	0
-
-static inline int ltq_is_ar9(void)
-{
-	return 0;
-}
-
-static inline int ltq_is_vr9(void)
-{
-	return 0;
-}
-
-static inline int ltq_is_falcon(void)
-{
-	return 1;
-}
-
-#endif /* CONFIG_SOC_FALCON */
-#endif /* _LTQ_XWAY_H__ */