diff options
| author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-12-15 02:01:08 +0000 |
|---|---|---|
| committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-12-15 02:01:08 +0000 |
| commit | 553786683f6d1316f38c7459fb17f3f88e9c553d (patch) | |
| tree | aa951f60a68199ebc90babec9aa5580a7159e479 /target/linux/lantiq/files-3.3/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h | |
| parent | 5d8e0585ac778f4dde3ead2cee576695c351c628 (diff) | |
[lantiq] remove 3.3 and 3.6
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34699 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/files-3.3/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h')
| -rw-r--r-- | target/linux/lantiq/files-3.3/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/target/linux/lantiq/files-3.3/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h b/target/linux/lantiq/files-3.3/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h deleted file mode 100644 index 9c33516e8..000000000 --- a/target/linux/lantiq/files-3.3/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h +++ /dev/null @@ -1,37 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2007 - Infineon Technologies AG - St. Martin Strasse 53; 81669 Munich, Germany - - Any use of this Software is subject to the conclusion of a respective - License Agreement. Without such a License Agreement no rights to the - Software are granted. - -******************************************************************************/ - -#ifndef __BOOT_REG_H -#define __BOOT_REG_H - -#define LTQ_BOOT_CPU_OFFSET 0x20 - -#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x00) -#define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x04) -#define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x08) -#define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C) -#define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x10) -#define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x14) -#define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */ -#define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */ -#define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ - (cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C) - -#endif |