kernel: update bcma and ssb to version master-2012-04-12 from wireless-testing

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31278 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 440 insertions, 62 deletions

diff --git a/target/linux/generic/patches-3.2/020-ssb_update.patch b/target/linux/generic/patches-3.2/020-ssb_update.patch
index 1fe1768f1..1b38e380d 100644
--- a/target/linux/generic/patches-3.2/020-ssb_update.patch
+++ b/target/linux/generic/patches-3.2/020-ssb_update.patch
@@ -1,6 +1,222 @@
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -13,6 +13,9 @@
+ #include <linux/ssb/ssb_driver_chipcommon.h>
+ #include <linux/delay.h>
+ #include <linux/export.h>
++#ifdef CONFIG_BCM47XX
++#include <asm/mach-bcm47xx/nvram.h>
++#endif
+ 
+ #include "ssb_private.h"
+ 
+@@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
+ 	u32 pmuctl, tmp, pllctl;
+ 	unsigned int i;
+ 
+-	if ((bus->chip_id == 0x5354) && !crystalfreq) {
+-		/* The 5354 crystal freq is 25MHz */
+-		crystalfreq = 25000;
+-	}
+ 	if (crystalfreq)
+ 		e = pmu0_plltab_find_entry(crystalfreq);
+ 	if (!e)
+@@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
+ 	u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
+ 
+ 	if (bus->bustype == SSB_BUSTYPE_SSB) {
+-		/* TODO: The user may override the crystal frequency. */
++#ifdef CONFIG_BCM47XX
++		char buf[20];
++		if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
++			crystalfreq = simple_strtoul(buf, NULL, 0);
++#endif
+ 	}
+ 
+ 	switch (bus->chip_id) {
+@@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
+ 		ssb_pmu1_pllinit_r0(cc, crystalfreq);
+ 		break;
+ 	case 0x4328:
++		ssb_pmu0_pllinit_r0(cc, crystalfreq);
++		break;
+ 	case 0x5354:
++		if (crystalfreq == 0)
++			crystalfreq = 25000;
+ 		ssb_pmu0_pllinit_r0(cc, crystalfreq);
+ 		break;
+ 	case 0x4322:
+@@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
+ 
+ EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
+ EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
++
++u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
++{
++	struct ssb_bus *bus = cc->dev->bus;
++
++	switch (bus->chip_id) {
++	case 0x5354:
++		/* 5354 chip uses a non programmable PLL of frequency 240MHz */
++		return 240000000;
++	default:
++		ssb_printk(KERN_ERR PFX
++			   "ERROR: PMU cpu clock unknown for device %04X\n",
++			   bus->chip_id);
++		return 0;
++	}
++}
++
++u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
++{
++	struct ssb_bus *bus = cc->dev->bus;
++
++	switch (bus->chip_id) {
++	case 0x5354:
++		return 120000000;
++	default:
++		ssb_printk(KERN_ERR PFX
++			   "ERROR: PMU controlclock unknown for device %04X\n",
++			   bus->chip_id);
++		return 0;
++	}
++}
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+ 	struct ssb_bus *bus = mcore->dev->bus;
+ 	u32 pll_type, n, m, rate = 0;
+ 
++	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
++		return ssb_pmu_get_cpu_clock(&bus->chipco);
++
+ 	if (bus->extif.dev) {
+ 		ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
+ 	} else if (bus->chipco.dev) {
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -75,7 +75,7 @@ static u32 get_cfgspace_addr(struct ssb_
+ 	u32 tmp;
+ 
+ 	/* We do only have one cardbus device behind the bridge. */
+-	if (pc->cardbusmode && (dev >= 1))
++	if (pc->cardbusmode && (dev > 1))
+ 		goto out;
+ 
+ 	if (bus == 0) {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
+ 		put_device(dev->dev);
+ }
+ 
+-static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
+-{
+-	if (drv)
+-		get_driver(&drv->drv);
+-	return drv;
+-}
+-
+-static inline void ssb_driver_put(struct ssb_driver *drv)
+-{
+-	if (drv)
+-		put_driver(&drv->drv);
+-}
+-
+ static int ssb_device_resume(struct device *dev)
+ {
+ 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+@@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
+ 			ssb_device_put(sdev);
+ 			continue;
+ 		}
+-		sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
+-		if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
+-			ssb_device_put(sdev);
++		sdrv = drv_to_ssb_drv(sdev->dev->driver);
++		if (SSB_WARN_ON(!sdrv->remove))
+ 			continue;
+-		}
+ 		sdrv->remove(sdev);
+ 		ctx->device_frozen[i] = 1;
+ 	}
+@@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
+ 				   dev_name(sdev->dev));
+ 			result = err;
+ 		}
+-		ssb_driver_put(sdrv);
+ 		ssb_device_put(sdev);
+ 	}
+ 
+@@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+ 	u32 plltype;
+ 	u32 clkctl_n, clkctl_m;
+ 
++	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
++		return ssb_pmu_get_controlclock(&bus->chipco);
++
+ 	if (ssb_extif_available(&bus->extif))
+ 		ssb_extif_get_clockcontrol(&bus->extif, &plltype,
+ 					   &clkctl_n, &clkctl_m);
 --- a/drivers/ssb/pci.c
 +++ b/drivers/ssb/pci.c
-@@ -523,7 +523,13 @@ static void sprom_extract_r45(struct ssb
+@@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
+ {
+ 	int i;
+ 	u16 v;
+-	s8 gain;
+ 	u16 loc[3];
+ 
+ 	if (out->revision == 3)			/* rev 3 moved MAC */
+@@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ss
+ 		SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
+ 
+ 	/* Extract the antenna gain values. */
+-	gain = r123_extract_antgain(out->revision, in,
+-				    SSB_SPROM1_AGAIN_BG,
+-				    SSB_SPROM1_AGAIN_BG_SHIFT);
+-	out->antenna_gain.ghz24.a0 = gain;
+-	out->antenna_gain.ghz24.a1 = gain;
+-	out->antenna_gain.ghz24.a2 = gain;
+-	out->antenna_gain.ghz24.a3 = gain;
+-	gain = r123_extract_antgain(out->revision, in,
+-				    SSB_SPROM1_AGAIN_A,
+-				    SSB_SPROM1_AGAIN_A_SHIFT);
+-	out->antenna_gain.ghz5.a0 = gain;
+-	out->antenna_gain.ghz5.a1 = gain;
+-	out->antenna_gain.ghz5.a2 = gain;
+-	out->antenna_gain.ghz5.a3 = gain;
++	out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
++						    SSB_SPROM1_AGAIN_BG,
++						    SSB_SPROM1_AGAIN_BG_SHIFT);
++	out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
++						    SSB_SPROM1_AGAIN_A,
++						    SSB_SPROM1_AGAIN_A_SHIFT);
+ }
+ 
+ /* Revs 4 5 and 8 have partially shared layout */
+@@ -504,16 +495,14 @@ static void sprom_extract_r45(struct ssb
+ 	}
+ 
+ 	/* Extract the antenna gain values. */
+-	SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
++	SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
+ 	     SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
+-	SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
++	SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
+ 	     SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
+-	SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
++	SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
+ 	     SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
+-	SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
++	SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
+ 	     SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
+-	memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
+-	       sizeof(out->antenna_gain.ghz5));
+ 
+ 	sprom_extract_r458(out, in);
+ 
+@@ -523,7 +512,13 @@ static void sprom_extract_r45(struct ssb
  static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
  {
  	int i;
@@ -15,10 +231,25 @@
  
  	/* extract the MAC address */
  	for (i = 0; i < 3; i++) {
-@@ -607,6 +613,61 @@ static void sprom_extract_r8(struct ssb_
- 	memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
- 	       sizeof(out->antenna_gain.ghz5));
+@@ -596,16 +591,69 @@ static void sprom_extract_r8(struct ssb_
+ 	SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
  
+ 	/* Extract the antenna gain values. */
+-	SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
++	SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
+ 	     SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
+-	SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
++	SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
+ 	     SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
+-	SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
++	SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
+ 	     SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
+-	SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
++	SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
+ 	     SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
+-	memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
+-	       sizeof(out->antenna_gain.ghz5));
++
 +	/* Extract cores power info info */
 +	for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
 +		o = pwr_info_offset[i];
@@ -73,10 +304,74 @@
 +		SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
 +	SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
 +		SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
-+
+ 
  	sprom_extract_r458(out, in);
  
- 	/* TODO - get remaining rev 8 stuff needed */
+--- a/drivers/ssb/pcmcia.c
++++ b/drivers/ssb/pcmcia.c
+@@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
+ 	case SSB_PCMCIA_CIS_ANTGAIN:
+ 		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
+ 			"antg tpl size");
+-		sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
+-		sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
+-		sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
+-		sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
+-		sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
+-		sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
+-		sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
+-		sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
++		sprom->antenna_gain.a0 = tuple->TupleData[1];
++		sprom->antenna_gain.a1 = tuple->TupleData[1];
++		sprom->antenna_gain.a2 = tuple->TupleData[1];
++		sprom->antenna_gain.a3 = tuple->TupleData[1];
+ 		break;
+ 	case SSB_PCMCIA_CIS_BFLAGS:
+ 		GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
+--- a/drivers/ssb/scan.c
++++ b/drivers/ssb/scan.c
+@@ -318,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 			bus->chip_package = 0;
+ 		}
+ 	}
++	ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
++		   "package 0x%02X\n", bus->chip_id, bus->chip_rev,
++		   bus->chip_package);
+ 	if (!bus->nr_devices)
+ 		bus->nr_devices = chipid_to_nrcores(bus->chip_id);
+ 	if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
+--- a/drivers/ssb/sdio.c
++++ b/drivers/ssb/sdio.c
+@@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
+ 			case SSB_SDIO_CIS_ANTGAIN:
+ 				GOTO_ERROR_ON(tuple->size != 2,
+ 					      "antg tpl size");
+-				sprom->antenna_gain.ghz24.a0 = tuple->data[1];
+-				sprom->antenna_gain.ghz24.a1 = tuple->data[1];
+-				sprom->antenna_gain.ghz24.a2 = tuple->data[1];
+-				sprom->antenna_gain.ghz24.a3 = tuple->data[1];
+-				sprom->antenna_gain.ghz5.a0 = tuple->data[1];
+-				sprom->antenna_gain.ghz5.a1 = tuple->data[1];
+-				sprom->antenna_gain.ghz5.a2 = tuple->data[1];
+-				sprom->antenna_gain.ghz5.a3 = tuple->data[1];
++				sprom->antenna_gain.a0 = tuple->data[1];
++				sprom->antenna_gain.a1 = tuple->data[1];
++				sprom->antenna_gain.a2 = tuple->data[1];
++				sprom->antenna_gain.a3 = tuple->data[1];
+ 				break;
+ 			case SSB_SDIO_CIS_BFLAGS:
+ 				GOTO_ERROR_ON((tuple->size != 3) &&
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
+ }
+ #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
+ 
++/* driver_chipcommon_pmu.c */
++extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
++extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
++
+ #endif /* LINUX_SSB_PRIVATE_H_ */
 --- a/include/linux/ssb/ssb.h
 +++ b/include/linux/ssb/ssb.h
 @@ -16,6 +16,12 @@ struct pcmcia_device;
@@ -86,13 +381,54 @@
 +struct ssb_sprom_core_pwr_info {
 +	u8 itssi_2g, itssi_5g;
 +	u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
-+	u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
++	u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
 +};
 +
  struct ssb_sprom {
  	u8 revision;
  	u8 il0mac[6];		/* MAC address for 802.11b/g */
-@@ -82,6 +88,8 @@ struct ssb_sprom {
+@@ -26,9 +32,12 @@ struct ssb_sprom {
+ 	u8 et0mdcport;		/* MDIO for enet0 */
+ 	u8 et1mdcport;		/* MDIO for enet1 */
+ 	u16 board_rev;		/* Board revision number from SPROM. */
++	u16 board_num;		/* Board number from SPROM. */
++	u16 board_type;		/* Board type from SPROM. */
+ 	u8 country_code;	/* Country Code */
+-	u16 leddc_on_time;	/* LED Powersave Duty Cycle On Count */
+-	u16 leddc_off_time;	/* LED Powersave Duty Cycle Off Count */
++	char alpha2[2];		/* Country Code as two chars like EU or US */
++	u8 leddc_on_time;	/* LED Powersave Duty Cycle On Count */
++	u8 leddc_off_time;	/* LED Powersave Duty Cycle Off Count */
+ 	u8 ant_available_a;	/* 2GHz antenna available bits (up to 4) */
+ 	u8 ant_available_bg;	/* 5GHz antenna available bits (up to 4) */
+ 	u16 pa0b0;
+@@ -47,10 +56,10 @@ struct ssb_sprom {
+ 	u8 gpio1;		/* GPIO pin 1 */
+ 	u8 gpio2;		/* GPIO pin 2 */
+ 	u8 gpio3;		/* GPIO pin 3 */
+-	u16 maxpwr_bg;		/* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
+-	u16 maxpwr_al;		/* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
+-	u16 maxpwr_a;		/* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
+-	u16 maxpwr_ah;		/* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
++	u8 maxpwr_bg;		/* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
++	u8 maxpwr_al;		/* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
++	u8 maxpwr_a;		/* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
++	u8 maxpwr_ah;		/* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
+ 	u8 itssi_a;		/* Idle TSSI Target for A-PHY */
+ 	u8 itssi_bg;		/* Idle TSSI Target for B/G-PHY */
+ 	u8 tri2g;		/* 2.4GHz TX isolation */
+@@ -61,8 +70,8 @@ struct ssb_sprom {
+ 	u8 txpid5gl[4];		/* 4.9 - 5.1GHz TX power index */
+ 	u8 txpid5g[4];		/* 5.1 - 5.5GHz TX power index */
+ 	u8 txpid5gh[4];		/* 5.5 - ...GHz TX power index */
+-	u8 rxpo2g;		/* 2GHz RX power offset */
+-	u8 rxpo5g;		/* 5GHz RX power offset */
++	s8 rxpo2g;		/* 2GHz RX power offset */
++	s8 rxpo5g;		/* 5GHz RX power offset */
+ 	u8 rssisav2g;		/* 2GHz RSSI params */
+ 	u8 rssismc2g;
+ 	u8 rssismf2g;
+@@ -82,19 +91,97 @@ struct ssb_sprom {
  	u16 boardflags2_hi;	/* Board flags (bits 48-63) */
  	/* TODO store board flags in a single u64 */
  
@@ -101,22 +437,111 @@
  	/* Antenna gain values for up to 4 antennas
  	 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
  	 * loss in the connectors is bigger than the gain. */
-@@ -94,6 +102,15 @@ struct ssb_sprom {
- 		} ghz5;		/* 5GHz band */
- 	} antenna_gain;
- 
+ 	struct {
++		s8 a0, a1, a2, a3;
++	} antenna_gain;
++
 +	struct {
-+		struct {
+ 		struct {
+-			s8 a0, a1, a2, a3;
+-		} ghz24;	/* 2.4GHz band */
 +			u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
 +		} ghz2;
-+		struct {
+ 		struct {
+-			s8 a0, a1, a2, a3;
+-		} ghz5;		/* 5GHz band */
+-	} antenna_gain;
 +			u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
 +		} ghz5;
 +	} fem;
 +
- 	/* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
++	u16 mcs2gpo[8];
++	u16 mcs5gpo[8];
++	u16 mcs5glpo[8];
++	u16 mcs5ghpo[8];
++	u8 opo;
++
++	u8 rxgainerr2ga[3];
++	u8 rxgainerr5gla[3];
++	u8 rxgainerr5gma[3];
++	u8 rxgainerr5gha[3];
++	u8 rxgainerr5gua[3];
++
++	u8 noiselvl2ga[3];
++	u8 noiselvl5gla[3];
++	u8 noiselvl5gma[3];
++	u8 noiselvl5gha[3];
++	u8 noiselvl5gua[3];
++
++	u8 regrev;
++	u8 txchain;
++	u8 rxchain;
++	u8 antswitch;
++	u16 cddpo;
++	u16 stbcpo;
++	u16 bw40po;
++	u16 bwduppo;
++
++	u8 tempthresh;
++	u8 tempoffset;
++	u16 rawtempsense;
++	u8 measpower;
++	u8 tempsense_slope;
++	u8 tempcorrx;
++	u8 tempsense_option;
++	u8 freqoffset_corr;
++	u8 iqcal_swp_dis;
++	u8 hw_iqcal_en;
++	u8 elna2g;
++	u8 elna5g;
++	u8 phycal_tempdelta;
++	u8 temps_period;
++	u8 temps_hysteresis;
++	u8 measpower1;
++	u8 measpower2;
++	u8 pcieingress_war;
+ 
+-	/* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
++	/* power per rate from sromrev 9 */
++	u16 cckbw202gpo;
++	u16 cckbw20ul2gpo;
++	u32 legofdmbw202gpo;
++	u32 legofdmbw20ul2gpo;
++	u32 legofdmbw205glpo;
++	u32 legofdmbw20ul5glpo;
++	u32 legofdmbw205gmpo;
++	u32 legofdmbw20ul5gmpo;
++	u32 legofdmbw205ghpo;
++	u32 legofdmbw20ul5ghpo;
++	u32 mcsbw202gpo;
++	u32 mcsbw20ul2gpo;
++	u32 mcsbw402gpo;
++	u32 mcsbw205glpo;
++	u32 mcsbw20ul5glpo;
++	u32 mcsbw405glpo;
++	u32 mcsbw205gmpo;
++	u32 mcsbw20ul5gmpo;
++	u32 mcsbw405gmpo;
++	u32 mcsbw205ghpo;
++	u32 mcsbw20ul5ghpo;
++	u32 mcsbw405ghpo;
++	u16 mcs32po;
++	u16 legofdm40duppo;
++	u8 sar2g;
++	u8 sar5g;
  };
  
+ /* Information about the PCB the circuitry is soldered on. */
+--- a/include/linux/ssb/ssb_driver_gige.h
++++ b/include/linux/ssb/ssb_driver_gige.h
+@@ -2,6 +2,7 @@
+ #define LINUX_SSB_DRIVER_GIGE_H_
+ 
+ #include <linux/ssb/ssb.h>
++#include <linux/bug.h>
+ #include <linux/pci.h>
+ #include <linux/spinlock.h>
+ 
 --- a/include/linux/ssb/ssb_regs.h
 +++ b/include/linux/ssb/ssb_regs.h
 @@ -432,6 +432,56 @@
@@ -184,50 +609,3 @@
  #define SSB_SPROM8_CCK2GPO		0x0140	/* CCK power offset */
  #define SSB_SPROM8_OFDM2GPO		0x0142	/* 2.4GHz OFDM power offset */
  #define SSB_SPROM8_OFDM5GPO		0x0146	/* 5.3GHz OFDM power offset */
-@@ -464,6 +515,46 @@
- 
- /* Values for boardflags_lo read from SPROM */
- #define SSB_BFL_BTCOEXIST		0x0001	/* implements Bluetooth coexistance */
-+#define SSB_BFL_PACTRL			0x0002	/* GPIO 9 controlling the PA */
-+#define SSB_BFL_AIRLINEMODE		0x0004	/* implements GPIO 13 radio disable indication */
-+#define SSB_BFL_RSSI			0x0008	/* software calculates nrssi slope. */
-+#define SSB_BFL_ENETSPI			0x0010	/* has ephy roboswitch spi */
-+#define SSB_BFL_XTAL_NOSLOW		0x0020	/* no slow clock available */
-+#define SSB_BFL_CCKHIPWR		0x0040	/* can do high power CCK transmission */
-+#define SSB_BFL_ENETADM			0x0080	/* has ADMtek switch */
-+#define SSB_BFL_ENETVLAN		0x0100	/* can do vlan */
-+#define SSB_BFL_AFTERBURNER		0x0200	/* supports Afterburner mode */
-+#define SSB_BFL_NOPCI			0x0400	/* board leaves PCI floating */
-+#define SSB_BFL_FEM			0x0800	/* supports the Front End Module */
-+#define SSB_BFL_EXTLNA			0x1000	/* has an external LNA */
-+#define SSB_BFL_HGPA			0x2000	/* had high gain PA */
-+#define SSB_BFL_BTCMOD			0x4000	/* BFL_BTCOEXIST is given in alternate GPIOs */
-+#define SSB_BFL_ALTIQ			0x8000	/* alternate I/Q settings */
-+
-+/* Values for boardflags_hi read from SPROM */
-+#define SSB_BFH_NOPA			0x0001	/* has no PA */
-+#define SSB_BFH_RSSIINV			0x0002	/* RSSI uses positive slope (not TSSI) */
-+#define SSB_BFH_PAREF			0x0004	/* uses the PARef LDO */
-+#define SSB_BFH_3TSWITCH		0x0008	/* uses a triple throw switch shared with bluetooth */
-+#define SSB_BFH_PHASESHIFT		0x0010	/* can support phase shifter */
-+#define SSB_BFH_BUCKBOOST		0x0020	/* has buck/booster */
-+#define SSB_BFH_FEM_BT			0x0040	/* has FEM and switch to share antenna with bluetooth */
-+
-+/* Values for boardflags2_lo read from SPROM */
-+#define SSB_BFL2_RXBB_INT_REG_DIS	0x0001	/* external RX BB regulator present */
-+#define SSB_BFL2_APLL_WAR		0x0002	/* alternative A-band PLL settings implemented */
-+#define SSB_BFL2_TXPWRCTRL_EN 		0x0004	/* permits enabling TX Power Control */
-+#define SSB_BFL2_2X4_DIV		0x0008	/* 2x4 diversity switch */
-+#define SSB_BFL2_5G_PWRGAIN		0x0010	/* supports 5G band power gain */
-+#define SSB_BFL2_PCIEWAR_OVR		0x0020	/* overrides ASPM and Clkreq settings */
-+#define SSB_BFL2_CAESERS_BRD		0x0040	/* is Caesers board (unused) */
-+#define SSB_BFL2_BTC3WIRE		0x0080	/* used 3-wire bluetooth coexist */
-+#define SSB_BFL2_SKWRKFEM_BRD		0x0100	/* 4321mcm93 uses Skyworks FEM */
-+#define SSB_BFL2_SPUR_WAR		0x0200	/* has a workaround for clock-harmonic spurs */
-+#define SSB_BFL2_GPLL_WAR		0x0400	/* altenative G-band PLL settings implemented */
-+
-+/* Values for boardflags_lo read from SPROM */
-+#define SSB_BFL_BTCOEXIST		0x0001	/* implements Bluetooth coexistance */
- #define SSB_BFL_PACTRL			0x0002	/* GPIO 9 controlling the PA */
- #define SSB_BFL_AIRLINEMODE		0x0004	/* implements GPIO 13 radio disable indication */
- #define SSB_BFL_RSSI			0x0008	/* software calculates nrssi slope. */