diff options
| author | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-05-01 15:53:56 +0000 |
|---|---|---|
| committer | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-05-01 15:53:56 +0000 |
| commit | f7215e23ebe842d6fee54e887c5d816d7f43a11f (patch) | |
| tree | faf2612b1d31c73b06675da30e5fa81b42159472 /target/linux/cns3xxx/patches-2.6.31/301-dma_cache_ownership_maint.patch | |
| parent | d75d999a720d07495811415ca129727f69c94843 (diff) | |
cns3xxx: fix missing and incomplete cache flushes on DMA cache sync for cpu - fixes some issues with ath9k
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26797 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/cns3xxx/patches-2.6.31/301-dma_cache_ownership_maint.patch')
| -rw-r--r-- | target/linux/cns3xxx/patches-2.6.31/301-dma_cache_ownership_maint.patch | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-2.6.31/301-dma_cache_ownership_maint.patch b/target/linux/cns3xxx/patches-2.6.31/301-dma_cache_ownership_maint.patch new file mode 100644 index 000000000..a52ae2464 --- /dev/null +++ b/target/linux/cns3xxx/patches-2.6.31/301-dma_cache_ownership_maint.patch @@ -0,0 +1,67 @@ +--- a/arch/arm/mm/cache-v6.S ++++ b/arch/arm/mm/cache-v6.S +@@ -179,6 +179,10 @@ ENTRY(v6_flush_kern_dcache_page) + * - end - virtual end address of region + */ + ENTRY(v6_dma_inv_range) ++#ifdef CONFIG_SMP ++ ldrb r2, [r0] ++ strb r2, [r0] ++#endif + tst r0, #D_CACHE_LINE_SIZE - 1 + bic r0, r0, #D_CACHE_LINE_SIZE - 1 + #ifdef HARVARD_CACHE +@@ -187,6 +191,10 @@ ENTRY(v6_dma_inv_range) + mcrne p15, 0, r0, c7, c11, 1 @ clean unified line + #endif + tst r1, #D_CACHE_LINE_SIZE - 1 ++#ifdef CONFIG_SMP ++ ldrneb r2, [r1, #-1] ++ strneb r2, [r1, #-1] ++#endif + bic r1, r1, #D_CACHE_LINE_SIZE - 1 + #ifdef HARVARD_CACHE + mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line +@@ -201,6 +209,10 @@ ENTRY(v6_dma_inv_range) + #endif + add r0, r0, #D_CACHE_LINE_SIZE + cmp r0, r1 ++#ifdef CONFIG_SMP ++ ldrlo r2, [r0] ++ strlo r2, [r0] ++#endif + blo 1b + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer +@@ -214,6 +226,9 @@ ENTRY(v6_dma_inv_range) + ENTRY(v6_dma_clean_range) + bic r0, r0, #D_CACHE_LINE_SIZE - 1 + 1: ++#ifdef CONFIG_SMP ++ ldr r2, [r0] ++#endif + #ifdef HARVARD_CACHE + mcr p15, 0, r0, c7, c10, 1 @ clean D line + #else +@@ -232,6 +247,10 @@ ENTRY(v6_dma_clean_range) + * - end - virtual end address of region + */ + ENTRY(v6_dma_flush_range) ++#ifdef CONFIG_SMP ++ ldrb r2, [r0] ++ strb r2, [r0] ++#endif + bic r0, r0, #D_CACHE_LINE_SIZE - 1 + 1: + #ifdef HARVARD_CACHE +@@ -241,6 +260,10 @@ ENTRY(v6_dma_flush_range) + #endif + add r0, r0, #D_CACHE_LINE_SIZE + cmp r0, r1 ++#ifdef CONFIG_SMP ++ ldrlob r2, [r0] ++ strlob r2, [r0] ++#endif + blo 1b + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |