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authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-03-09 18:51:46 +0000
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-03-09 18:51:46 +0000
commitfc74ddd9808689a2ecfc39ec6b04d2fb8cf4aa8e (patch)
treea6d96d08faa76cb2ef37f2f678ddb2ecd561e4b0 /target/linux/cns3xxx/files/arch/arm/mach-cns3xxx
parentd5d0bd890fba306006563ddb264d51f6466e583e (diff)
cns3xxx: add linux 3.8 support and use it by default
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35908 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/cns3xxx/files/arch/arm/mach-cns3xxx')
-rw-r--r--target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S2
-rw-r--r--target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c21
2 files changed, 12 insertions, 11 deletions
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S
index 456fd67f9..3b46bdc32 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S
@@ -13,7 +13,7 @@
#include <linux/linkage.h>
#include <linux/init.h>
- __INIT
+ __CPUINIT
/*
* CNS3XXX specific entry point for secondary CPUs. This provides
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
index 16ad56265..77ac97a20 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
@@ -49,12 +49,6 @@ struct cpu_cache_fns cpu_cache_save;
#define SCU_CPU_STATUS 0x08
static void __iomem *scu_base;
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
-
static void __init cns3xxx_set_fiq_regs(void)
{
struct pt_regs FIQ_regs;
@@ -108,7 +102,7 @@ static void __cpuinit write_pen_release(int val)
static DEFINE_SPINLOCK(boot_lock);
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit cns3xxx_secondary_init(unsigned int cpu)
{
/*
* if any interrupts are already enabled for the primary
@@ -143,7 +137,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
@@ -192,7 +186,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
-void __init smp_init_cpus(void)
+static void __init cns3xxx_smp_init_cpus(void)
{
unsigned int i, ncores;
unsigned int status;
@@ -214,7 +208,7 @@ void __init smp_init_cpus(void)
set_smp_cross_call(gic_raise_softirq);
}
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
{
int i;
@@ -348,3 +342,10 @@ void smp_dma_flush_range(const void *start, const void *end)
}
raw_local_irq_restore(flags);
}
+
+struct smp_operations cns3xxx_smp_ops __initdata = {
+ .smp_init_cpus = cns3xxx_smp_init_cpus,
+ .smp_prepare_cpus = cns3xxx_smp_prepare_cpus,
+ .smp_secondary_init = cns3xxx_secondary_init,
+ .smp_boot_secondary = cns3xxx_boot_secondary,
+};