[brcm63xx] remove support for 3.6 kernel

Signed-off-by: Florian Fainelli <florian@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35506 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 0 insertions, 211 deletions

diff --git a/target/linux/brcm63xx/patches-3.6/309-MIPS-BCM63XX-add-HSSPI-register-definitions.patch b/target/linux/brcm63xx/patches-3.6/309-MIPS-BCM63XX-add-HSSPI-register-definitions.patch
deleted file mode 100644
index 5e2cd96d3..000000000
--- a/target/linux/brcm63xx/patches-3.6/309-MIPS-BCM63XX-add-HSSPI-register-definitions.patch
+++ /dev/null
@@ -1,211 +0,0 @@
-From 70f970222bc1096689ae1bffeb9ed09a7c4bed07 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sat, 12 Nov 2011 12:19:55 +0100
-Subject: [PATCH 28/60] MIPS: BCM63XX: add HSSPI register definitions
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |   18 ++++++++
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   47 +++++++++++++++++++++
- 2 files changed, 65 insertions(+), 0 deletions(-)
-
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -116,6 +116,7 @@ enum bcm63xx_regs_set {
- 	RSET_UART1,
- 	RSET_GPIO,
- 	RSET_SPI,
-+	RSET_HSSPI,
- 	RSET_UDC0,
- 	RSET_OHCI0,
- 	RSET_OHCI_PRIV,
-@@ -159,6 +160,7 @@ enum bcm63xx_regs_set {
- #define RSET_ENETDMA_SIZE		2048
- #define RSET_ENETSW_SIZE		65536
- #define RSET_UART_SIZE			24
-+#define RSET_HSSPI_SIZE			1536
- #define RSET_UDC_SIZE			256
- #define RSET_OHCI_SIZE			256
- #define RSET_EHCI_SIZE			256
-@@ -182,6 +184,7 @@ enum bcm63xx_regs_set {
- #define BCM_6328_UART1_BASE		(0xb0000120)
- #define BCM_6328_GPIO_BASE		(0xb0000080)
- #define BCM_6328_SPI_BASE		(0xdeadbeef)
-+#define BCM_6328_HSSPI_BASE		(0xb0001000)
- #define BCM_6328_UDC0_BASE		(0xdeadbeef)
- #define BCM_6328_USBDMA_BASE		(0xdeadbeef)
- #define BCM_6328_OHCI0_BASE		(0xb0002600)
-@@ -227,6 +230,7 @@ enum bcm63xx_regs_set {
- #define BCM_6338_UART1_BASE		(0xdeadbeef)
- #define BCM_6338_GPIO_BASE		(0xfffe0400)
- #define BCM_6338_SPI_BASE		(0xfffe0c00)
-+#define BCM_6338_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6338_UDC0_BASE		(0xdeadbeef)
- #define BCM_6338_USBDMA_BASE		(0xfffe2400)
- #define BCM_6338_OHCI0_BASE		(0xdeadbeef)
-@@ -273,6 +277,7 @@ enum bcm63xx_regs_set {
- #define BCM_6345_UART1_BASE		(0xdeadbeef)
- #define BCM_6345_GPIO_BASE		(0xfffe0400)
- #define BCM_6345_SPI_BASE		(0xdeadbeef)
-+#define BCM_6345_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6345_UDC0_BASE		(0xdeadbeef)
- #define BCM_6345_USBDMA_BASE		(0xfffe2800)
- #define BCM_6345_ENET0_BASE		(0xfffe1800)
-@@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
- #define BCM_6348_UART1_BASE		(0xdeadbeef)
- #define BCM_6348_GPIO_BASE		(0xfffe0400)
- #define BCM_6348_SPI_BASE		(0xfffe0c00)
-+#define BCM_6348_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6348_UDC0_BASE		(0xfffe1000)
- #define BCM_6348_OHCI0_BASE		(0xfffe1b00)
- #define BCM_6348_OHCI_PRIV_BASE		(0xfffe1c00)
-@@ -361,6 +367,7 @@ enum bcm63xx_regs_set {
- #define BCM_6358_UART1_BASE		(0xfffe0120)
- #define BCM_6358_GPIO_BASE		(0xfffe0080)
- #define BCM_6358_SPI_BASE		(0xfffe0800)
-+#define BCM_6358_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6358_UDC0_BASE		(0xfffe0800)
- #define BCM_6358_OHCI0_BASE		(0xfffe1400)
- #define BCM_6358_OHCI_PRIV_BASE		(0xdeadbeef)
-@@ -405,6 +412,7 @@ enum bcm63xx_regs_set {
- #define BCM_6368_UART1_BASE		(0xb0000120)
- #define BCM_6368_GPIO_BASE		(0xb0000080)
- #define BCM_6368_SPI_BASE		(0xb0000800)
-+#define BCM_6368_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6368_UDC0_BASE		(0xdeadbeef)
- #define BCM_6368_OHCI0_BASE		(0xb0001600)
- #define BCM_6368_OHCI_PRIV_BASE		(0xdeadbeef)
-@@ -454,6 +462,7 @@ extern const unsigned long *bcm63xx_regs
- 	__GEN_RSET_BASE(__cpu, UART1)					\
- 	__GEN_RSET_BASE(__cpu, GPIO)					\
- 	__GEN_RSET_BASE(__cpu, SPI)					\
-+	__GEN_RSET_BASE(__cpu, HSSPI)					\
- 	__GEN_RSET_BASE(__cpu, UDC0)					\
- 	__GEN_RSET_BASE(__cpu, OHCI0)					\
- 	__GEN_RSET_BASE(__cpu, OHCI_PRIV)				\
-@@ -495,6 +504,7 @@ extern const unsigned long *bcm63xx_regs
- 	[RSET_UART1]		= BCM_## __cpu ##_UART1_BASE,		\
- 	[RSET_GPIO]		= BCM_## __cpu ##_GPIO_BASE,		\
- 	[RSET_SPI]		= BCM_## __cpu ##_SPI_BASE,		\
-+	[RSET_HSSPI]		= BCM_## __cpu ##_HSSPI_BASE,		\
- 	[RSET_UDC0]		= BCM_## __cpu ##_UDC0_BASE,		\
- 	[RSET_OHCI0]		= BCM_## __cpu ##_OHCI0_BASE,		\
- 	[RSET_OHCI_PRIV]	= BCM_## __cpu ##_OHCI_PRIV_BASE,	\
-@@ -567,6 +577,7 @@ enum bcm63xx_irq {
- 	IRQ_ENET0,
- 	IRQ_ENET1,
- 	IRQ_ENET_PHY,
-+	IRQ_HSSPI,
- 	IRQ_OHCI0,
- 	IRQ_EHCI0,
- 	IRQ_ENET0_RXDMA,
-@@ -602,6 +613,7 @@ enum bcm63xx_irq {
- #define BCM_6328_ENET0_IRQ		0
- #define BCM_6328_ENET1_IRQ		0
- #define BCM_6328_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
-+#define BCM_6328_HSSPI_IRQ		(IRQ_INTERNAL_BASE + 29)
- #define BCM_6328_OHCI0_IRQ		(BCM_6328_HIGH_IRQ_BASE + 9)
- #define BCM_6328_EHCI0_IRQ		(BCM_6328_HIGH_IRQ_BASE + 10)
- #define BCM_6328_PCMCIA_IRQ		0
-@@ -640,6 +652,7 @@ enum bcm63xx_irq {
- #define BCM_6338_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
- #define BCM_6338_ENET1_IRQ		0
- #define BCM_6338_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-+#define BCM_6338_HSSPI_IRQ		0
- #define BCM_6338_OHCI0_IRQ		0
- #define BCM_6338_EHCI0_IRQ		0
- #define BCM_6338_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
-@@ -671,6 +684,7 @@ enum bcm63xx_irq {
- #define BCM_6345_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
- #define BCM_6345_ENET1_IRQ		0
- #define BCM_6345_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
-+#define BCM_6345_HSSPI_IRQ		0
- #define BCM_6345_OHCI0_IRQ		0
- #define BCM_6345_EHCI0_IRQ		0
- #define BCM_6345_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 1)
-@@ -702,6 +716,7 @@ enum bcm63xx_irq {
- #define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
- #define BCM_6348_ENET1_IRQ		(IRQ_INTERNAL_BASE + 7)
- #define BCM_6348_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-+#define BCM_6348_HSSPI_IRQ		0
- #define BCM_6348_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 12)
- #define BCM_6348_EHCI0_IRQ		0
- #define BCM_6348_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 20)
-@@ -733,6 +748,7 @@ enum bcm63xx_irq {
- #define BCM_6358_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
- #define BCM_6358_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
- #define BCM_6358_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-+#define BCM_6358_HSSPI_IRQ		0
- #define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
- #define BCM_6358_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
- #define BCM_6358_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
-@@ -773,6 +789,7 @@ enum bcm63xx_irq {
- #define BCM_6368_ENET0_IRQ		0
- #define BCM_6368_ENET1_IRQ		0
- #define BCM_6368_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 15)
-+#define BCM_6368_HSSPI_IRQ		0
- #define BCM_6368_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
- #define BCM_6368_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 7)
- #define BCM_6368_PCMCIA_IRQ		0
-@@ -813,6 +830,7 @@ extern const int *bcm63xx_irqs;
- 	[IRQ_ENET0]		= BCM_## __cpu ##_ENET0_IRQ,		\
- 	[IRQ_ENET1]		= BCM_## __cpu ##_ENET1_IRQ,		\
- 	[IRQ_ENET_PHY]		= BCM_## __cpu ##_ENET_PHY_IRQ,		\
-+	[IRQ_HSSPI]		= BCM_## __cpu ##_HSSPI_IRQ,		\
- 	[IRQ_OHCI0]		= BCM_## __cpu ##_OHCI0_IRQ,		\
- 	[IRQ_EHCI0]		= BCM_## __cpu ##_EHCI0_IRQ,		\
- 	[IRQ_ENET0_RXDMA]	= BCM_## __cpu ##_ENET0_RXDMA_IRQ,	\
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1239,4 +1239,51 @@
- 
- #define PCIE_DEVICE_OFFSET		0x8000
- 
-+/*************************************************************************
-+ * _REG relative to RSET_HSSPI
-+ *************************************************************************/
-+
-+#define HSSPI_GLOBAL_CTRL_REG			0x0
-+#define GLOBAL_CTRL_CLK_POLARITY		(1 << 17)
-+#define GLOBAL_CTRL_CLK_GATE_SSOFF		(1 << 16)
-+
-+#define HSSPI_GLOBAL_EXT_TRIGGER_REG		0x4
-+
-+#define HSSPI_INT_STATUS_REG			0x8
-+#define HSSPI_INT_STATUS_MASKED_REG		0xc
-+#define HSSPI_INT_MASK_REG			0x10
-+
-+#define HSSPI_PING0_CMD_DONE			(1 << 0)
-+
-+#define HSSPI_INT_CLEAR_ALL			0xff001f1f
-+
-+#define HSSPI_PINGPONG_COMMAND_REG(x)		(0x80 + (x) * 0x40)
-+#define PINGPONG_CMD_COMMAND_MASK		0xf
-+#define PINGPONG_COMMAND_NOOP			0
-+#define PINGPONG_COMMAND_START_NOW		1
-+#define PINGPONG_COMMAND_START_TRIGGER		2
-+#define PINGPONG_COMMAND_HALT			3
-+#define PINGPONG_COMMAND_FLUSH			4
-+#define PINGPONG_CMD_PROFILE_SHIFT		8
-+#define PINGPONG_CMD_SS_SHIFT			12
-+
-+#define HSSPI_PINGPONG_STATUS_REG(x)		(0x84 + (x) * 0x40)
-+
-+#define HSSPI_PROFILE_CLK_CTRL_REG(x)		(0x100 + (x) * 0x20)
-+#define CLK_CTRL_ACCUM_RST_ON_LOOP		(1 << 15)
-+
-+#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)	(0x104 + (x) * 0x20)
-+#define SIGNAL_CTRL_LATCH_RISING		(1 << 12)
-+#define SIGNAL_CTRL_LAUNCH_RISING		(1 << 13)
-+#define SIGNAL_CTRL_ASYNC_INPUT_PATH		(1 << 16)
-+
-+#define HSSPI_PROFILE_MODE_CTRL_REG(x)		(0x108 + (x) * 0x20)
-+#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT	8
-+#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT	12
-+#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT	16
-+#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT	18
-+#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT		24
-+
-+#define HSSPI_FIFO_REG(x)			(0x200 + (x) * 0x200)
-+
- #endif /* BCM63XX_REGS_H_ */