bcm47xx: Add driver for the SSB Gigabit Ethernet core.

It doesn't work, yet, but let's commit what we have.


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10509 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 790 insertions, 0 deletions

diff --git a/target/linux/brcm47xx/patches-2.6.23/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-2.6.23/700-ssb-gigabit-ethernet-driver.patch
new file mode 100644
index 000000000..2095765d6
--- /dev/null
+++ b/target/linux/brcm47xx/patches-2.6.23/700-ssb-gigabit-ethernet-driver.patch
@@ -0,0 +1,790 @@
+Index: linux-2.6.23.16/drivers/ssb/Kconfig
+===================================================================
+--- linux-2.6.23.16.orig/drivers/ssb/Kconfig	2008-02-20 18:32:01.000000000 +0100
++++ linux-2.6.23.16/drivers/ssb/Kconfig	2008-02-20 18:32:31.000000000 +0100
+@@ -120,4 +120,13 @@ config SSB_DRIVER_EXTIF
+ 
+ 	  If unsure, say N
+ 
++config SSB_DRIVER_GIGE
++	bool "SSB Broadcom Gigabit Ethernet driver (EXPERIMENTAL)"
++	depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS && EXPERIMENTAL
++	help
++	  Driver the the Sonics Silicon Backplane attached
++	  Broadcom Gigabit Ethernet.
++
++	  If unsure, say N
++
+ endmenu
+Index: linux-2.6.23.16/drivers/ssb/Makefile
+===================================================================
+--- linux-2.6.23.16.orig/drivers/ssb/Makefile	2008-02-20 18:32:01.000000000 +0100
++++ linux-2.6.23.16/drivers/ssb/Makefile	2008-02-20 18:32:31.000000000 +0100
+@@ -11,6 +11,7 @@ ssb-y					+= driver_chipcommon.o
+ ssb-$(CONFIG_SSB_DRIVER_MIPS)		+= driver_mipscore.o
+ ssb-$(CONFIG_SSB_DRIVER_EXTIF)		+= driver_extif.o
+ ssb-$(CONFIG_SSB_DRIVER_PCICORE)	+= driver_pcicore.o
++ssb-$(CONFIG_SSB_DRIVER_GIGE)		+= driver_gige.o
+ 
+ # b43 pci-ssb-bridge driver
+ # Not strictly a part of SSB, but kept here for convenience
+Index: linux-2.6.23.16/drivers/ssb/driver_gige.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.23.16/drivers/ssb/driver_gige.c	2008-02-20 18:32:31.000000000 +0100
+@@ -0,0 +1,268 @@
++/*
++ * Sonics Silicon Backplane
++ * Broadcom Gigabit Ethernet core driver
++ *
++ * Copyright 2008, Broadcom Corporation
++ * Copyright 2008, Michael Buesch <mb@bu3sch.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <linux/ssb/ssb.h>
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/ssb/ssb_driver_gige.h>
++
++
++MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
++MODULE_AUTHOR("Michael Buesch");
++MODULE_LICENSE("GPL");
++
++
++static const struct ssb_device_id ssb_gige_tbl[] = {
++	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
++	SSB_DEVTABLE_END
++};
++MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl);
++
++
++static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
++{
++	return ssb_read8(dev->dev, offset);
++}
++
++static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
++{
++	return ssb_read16(dev->dev, offset);
++}
++
++static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
++{
++	return ssb_read32(dev->dev, offset);
++}
++
++static inline void gige_write8(struct ssb_gige *dev,
++			       u16 offset, u8 value)
++{
++	ssb_write8(dev->dev, offset, value);
++}
++
++static inline void gige_write16(struct ssb_gige *dev,
++				u16 offset, u16 value)
++{
++	ssb_write16(dev->dev, offset, value);
++}
++
++static inline void gige_write32(struct ssb_gige *dev,
++				u16 offset, u32 value)
++{
++	ssb_write32(dev->dev, offset, value);
++}
++
++static inline
++u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
++{
++	BUG_ON(offset >= 256);
++	return gige_read8(dev, SSB_GIGE_PCICFG + offset);
++}
++
++static inline
++u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
++{
++	BUG_ON(offset >= 256);
++	return gige_read16(dev, SSB_GIGE_PCICFG + offset);
++}
++
++static inline
++u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
++{
++	BUG_ON(offset >= 256);
++	return gige_read32(dev, SSB_GIGE_PCICFG + offset);
++}
++
++static inline
++void gige_pcicfg_write8(struct ssb_gige *dev,
++			unsigned int offset, u8 value)
++{
++	BUG_ON(offset >= 256);
++	gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
++}
++
++static inline
++void gige_pcicfg_write16(struct ssb_gige *dev,
++			 unsigned int offset, u16 value)
++{
++	BUG_ON(offset >= 256);
++	gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
++}
++
++static inline
++void gige_pcicfg_write32(struct ssb_gige *dev,
++			 unsigned int offset, u32 value)
++{
++	BUG_ON(offset >= 256);
++	gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
++}
++
++static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
++				    int reg, int size, u32 *val)
++{
++	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
++	unsigned long flags;
++
++	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++	if (reg >= 256)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	spin_lock_irqsave(&dev->lock, flags);
++	switch (size) {
++	case 1:
++		*val = gige_pcicfg_read8(dev, reg);
++		break;
++	case 2:
++		*val = gige_pcicfg_read16(dev, reg);
++		break;
++	case 4:
++		*val = gige_pcicfg_read32(dev, reg);
++		break;
++	default:
++		WARN_ON(1);
++	}
++	spin_unlock_irqrestore(&dev->lock, flags);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
++				     int reg, int size, u32 val)
++{
++	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
++	unsigned long flags;
++
++	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++	if (reg >= 256)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	spin_lock_irqsave(&dev->lock, flags);
++	switch (size) {
++	case 1:
++		gige_pcicfg_write8(dev, reg, val);
++		break;
++	case 2:
++		gige_pcicfg_write16(dev, reg, val);
++		break;
++	case 4:
++		gige_pcicfg_write32(dev, reg, val);
++		break;
++	default:
++		WARN_ON(1);
++	}
++	spin_unlock_irqrestore(&dev->lock, flags);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
++{
++	struct ssb_gige *dev;
++	u32 base;
++
++	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++	if (!dev)
++		return -ENOMEM;
++	dev->dev = sdev;
++
++	spin_lock_init(&dev->lock);
++	dev->pci_controller.pci_ops = &dev->pci_ops;
++	dev->pci_controller.io_resource = &dev->io_resource;
++	dev->pci_controller.mem_resource = &dev->mem_resource;
++	dev->pci_controller.mem_offset = 0x24000000;
++	dev->pci_controller.io_map_base = 0x800;
++	dev->pci_ops.read = ssb_gige_pci_read_config;
++	dev->pci_ops.write = ssb_gige_pci_write_config;
++
++	dev->io_resource.name = "SSB GIGE I/O";
++	dev->io_resource.start = 0x800;
++	dev->io_resource.end = 0x8FF;
++	dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
++
++	if (!ssb_device_is_enabled(sdev))
++		ssb_device_enable(sdev, 0);
++
++	/* Setup BAR0. This is a 64k MMIO region. */
++	base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
++	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
++	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
++
++	dev->mem_resource.name = "SSB GIGE memory";
++	dev->mem_resource.start = base;
++	dev->mem_resource.end = base + SSB_CORE_SIZE - 1;
++	dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
++
++	/* Enable the memory region. */
++	gige_pcicfg_write16(dev, PCI_COMMAND,
++			    gige_pcicfg_read16(dev, PCI_COMMAND)
++			    | PCI_COMMAND_MEMORY);
++
++	/* Write flushing is controlled by the Flush Status Control register.
++	 * We want to flush every register write with a timeout and we want
++	 * to disable the IRQ mask while flushing to avoid concurrency.
++	 * Note that automatic write flushing does _not_ work from
++	 * an IRQ handler. The driver must flush manually by reading a register.
++	 */
++	gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
++
++	//TODO
++
++	ssb_set_drvdata(sdev, dev);
++	register_pci_controller(&dev->pci_controller);
++
++	return 0;
++}
++
++int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
++				   struct pci_dev *pdev)
++{
++	struct ssb_gige *dev = ssb_get_drvdata(sdev);
++	struct resource *res;
++
++	if (pdev->bus->ops != &dev->pci_ops) {
++		/* The PCI device is not on this SSB GigE bridge device. */
++		return -ENODEV;
++	}
++
++	/* Fixup the PCI resources. */
++	res = &(pdev->resource[0]);
++	res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
++	res->name = dev->mem_resource.name;
++	res->start = dev->mem_resource.start;
++	res->end = dev->mem_resource.end;
++
++	return 0;
++}
++
++int ssb_gige_map_irq(struct ssb_device *sdev,
++		     const struct pci_dev *pdev)
++{
++	struct ssb_gige *dev = ssb_get_drvdata(sdev);
++
++	if (pdev->bus->ops != &dev->pci_ops) {
++		/* The PCI device is not on this SSB GigE bridge device. */
++		return -ENODEV;
++	}
++
++	return ssb_mips_irq(sdev) + 2;
++}
++
++static struct ssb_driver ssb_gige_driver = {
++	.name		= "BCM-GigE",
++	.id_table	= ssb_gige_tbl,
++	.probe		= ssb_gige_probe,
++};
++
++int ssb_gige_init(void)
++{
++	return ssb_driver_register(&ssb_gige_driver);
++}
+Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h	2008-02-20 18:32:31.000000000 +0100
+@@ -0,0 +1,70 @@
++#ifndef LINUX_SSB_DRIVER_GIGE_H_
++#define LINUX_SSB_DRIVER_GIGE_H_
++
++#include <linux/pci.h>
++#include <linux/spinlock.h>
++
++#ifdef CONFIG_SSB_DRIVER_GIGE
++
++#define SSB_GIGE_PCIIO			0x0000 /* PCI I/O Registers (1024 bytes) */
++#define SSB_GIGE_RESERVED		0x0400 /* Reserved (1024 bytes) */
++#define SSB_GIGE_PCICFG			0x0800 /* PCI config space (256 bytes) */
++#define SSB_GIGE_SHIM_FLUSHSTAT		0x0C00 /* PCI to OCP: Flush status control (32bit) */
++#define SSB_GIGE_SHIM_FLUSHRDA		0x0C04 /* PCI to OCP: Flush read address (32bit) */
++#define SSB_GIGE_SHIM_FLUSHTO		0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
++#define SSB_GIGE_SHIM_BARRIER		0x0C0C /* PCI to OCP: Barrier register (32bit) */
++#define SSB_GIGE_SHIM_MAOCPSI		0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
++#define SSB_GIGE_SHIM_SIOCPMA		0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
++
++struct ssb_gige {
++	struct ssb_device *dev;
++
++	spinlock_t lock;
++
++	/* The PCI controller device. */
++	struct pci_controller pci_controller;
++	struct pci_ops pci_ops;
++	struct resource mem_resource;
++	struct resource io_resource;
++};
++
++extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
++					  struct pci_dev *pdev);
++extern int ssb_gige_map_irq(struct ssb_device *sdev,
++			    const struct pci_dev *pdev);
++
++/* The GigE driver is not a standalone module, because we don't have support
++ * for unregistering the driver. So we could not unload the module anyway. */
++extern int ssb_gige_init(void);
++static inline void ssb_gige_exit(void)
++{
++	/* Currently we can not unregister the GigE driver,
++	 * because we can not unregister the PCI bridge. */
++	BUG();
++}
++
++
++#else /* CONFIG_SSB_DRIVER_GIGE */
++/* Gigabit Ethernet driver disabled */
++
++
++static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
++						 struct pci_dev *pdev)
++{
++	return -ENOSYS;
++}
++static inline int ssb_gige_map_irq(struct ssb_device *sdev,
++				   const struct pci_dev *pdev)
++{
++	return -ENOSYS;
++}
++static inline int ssb_gige_init(void)
++{
++	return 0;
++}
++static inline void ssb_gige_exit(void)
++{
++}
++
++#endif /* CONFIG_SSB_DRIVER_GIGE */
++#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
+Index: linux-2.6.23.16/drivers/ssb/driver_pcicore.c
+===================================================================
+--- linux-2.6.23.16.orig/drivers/ssb/driver_pcicore.c	2008-02-20 18:32:01.000000000 +0100
++++ linux-2.6.23.16/drivers/ssb/driver_pcicore.c	2008-02-20 18:32:31.000000000 +0100
+@@ -60,74 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
+ /* Core to access the external PCI config space. Can only have one. */
+ static struct ssb_pcicore *extpci_core;
+ 
+-static u32 ssb_pcicore_pcibus_iobase = 0x100;
+-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
+-
+-int pcibios_plat_dev_init(struct pci_dev *d)
+-{
+-	struct resource *res;
+-	int pos, size;
+-	u32 *base;
+-
+-	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
+-		   pci_name(d));
+-
+-	/* Fix up resource bases */
+-	for (pos = 0; pos < 6; pos++) {
+-		res = &d->resource[pos];
+-		if (res->flags & IORESOURCE_IO)
+-			base = &ssb_pcicore_pcibus_iobase;
+-		else
+-			base = &ssb_pcicore_pcibus_membase;
+-		res->flags |= IORESOURCE_PCI_FIXED;
+-		if (res->end) {
+-			size = res->end - res->start + 1;
+-			if (*base & (size - 1))
+-				*base = (*base + size) & ~(size - 1);
+-			res->start = *base;
+-			res->end = res->start + size - 1;
+-			*base += size;
+-			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
+-		}
+-		/* Fix up PCI bridge BAR0 only */
+-		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
+-			break;
+-	}
+-	/* Fix up interrupt lines */
+-	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
+-	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
+-
+-	return 0;
+-}
+-
+-static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
+-{
+-	u8 lat;
+-
+-	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
+-		return;
+-
+-	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
+-
+-	/* Enable PCI bridge bus mastering and memory space */
+-	pci_set_master(dev);
+-	pcibios_enable_device(dev, ~0);
+-
+-	/* Enable PCI bridge BAR1 prefetch and burst */
+-	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
+-
+-	/* Make sure our latency is high enough to handle the devices behind us */
+-	lat = 168;
+-	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
+-		   pci_name(dev), lat);
+-	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+-}
+-DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
+-
+-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+-{
+-	return ssb_mips_irq(extpci_core->dev) + 2;
+-}
+ 
+ static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
+ 			     unsigned int bus, unsigned int dev,
+@@ -317,6 +249,92 @@ static struct pci_controller ssb_pcicore
+ 	.mem_offset	= 0x24000000,
+ };
+ 
++static u32 ssb_pcicore_pcibus_iobase = 0x100;
++static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
++
++/* This function is called when doing a pci_enable_device().
++ * We must first check if the device is a device on the PCI-core bridge. */
++int ssb_pcicore_plat_dev_init(struct pci_dev *d)
++{
++	struct resource *res;
++	int pos, size;
++	u32 *base;
++
++	if (d->bus->ops != &ssb_pcicore_pciops) {
++		/* This is not a device on the PCI-core bridge. */
++		return -ENODEV;
++	}
++
++	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
++		   pci_name(d));
++
++	/* Fix up resource bases */
++	for (pos = 0; pos < 6; pos++) {
++		res = &d->resource[pos];
++		if (res->flags & IORESOURCE_IO)
++			base = &ssb_pcicore_pcibus_iobase;
++		else
++			base = &ssb_pcicore_pcibus_membase;
++		res->flags |= IORESOURCE_PCI_FIXED;
++		if (res->end) {
++			size = res->end - res->start + 1;
++			if (*base & (size - 1))
++				*base = (*base + size) & ~(size - 1);
++			res->start = *base;
++			res->end = res->start + size - 1;
++			*base += size;
++			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
++		}
++		/* Fix up PCI bridge BAR0 only */
++		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
++			break;
++	}
++	/* Fix up interrupt lines */
++	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
++	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
++
++	return 0;
++}
++
++/* Early PCI fixup for a device on the PCI-core bridge. */
++static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
++{
++	u8 lat;
++
++	if (dev->bus->ops != &ssb_pcicore_pciops) {
++		/* This is not a device on the PCI-core bridge. */
++		return;
++	}
++	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
++		return;
++
++	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
++
++	/* Enable PCI bridge bus mastering and memory space */
++	pci_set_master(dev);
++	pcibios_enable_device(dev, ~0);
++
++	/* Enable PCI bridge BAR1 prefetch and burst */
++	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
++
++	/* Make sure our latency is high enough to handle the devices behind us */
++	lat = 168;
++	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
++		   pci_name(dev), lat);
++	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
++}
++DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
++
++/* PCI device IRQ mapping. */
++int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++	if (dev->bus->ops != &ssb_pcicore_pciops) {
++		/* This is not a device on the PCI-core bridge. */
++		return -ENODEV;
++	}
++	return ssb_mips_irq(extpci_core->dev) + 2;
++}
++
+ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
+ {
+ 	u32 val;
+Index: linux-2.6.23.16/drivers/ssb/embedded.c
+===================================================================
+--- linux-2.6.23.16.orig/drivers/ssb/embedded.c	2008-02-20 18:32:01.000000000 +0100
++++ linux-2.6.23.16/drivers/ssb/embedded.c	2008-02-20 18:32:31.000000000 +0100
+@@ -10,6 +10,9 @@
+ 
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
++#include <linux/ssb/ssb_driver_pci.h>
++#include <linux/ssb/ssb_driver_gige.h>
++#include <linux/pci.h>
+ 
+ #include "ssb_private.h"
+ 
+@@ -130,3 +133,90 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
+ 	return res;
+ }
+ EXPORT_SYMBOL(ssb_gpio_polarity);
++
++#ifdef CONFIG_SSB_DRIVER_GIGE
++static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
++{
++	struct pci_dev *pdev = (struct pci_dev *)data;
++	struct ssb_device *dev;
++	unsigned int i;
++	int res;
++
++	for (i = 0; i < bus->nr_devices; i++) {
++		dev = &(bus->devices[i]);
++		if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
++			continue;
++		if (!dev->dev ||
++		    !dev->dev->driver ||
++		    !device_is_registered(dev->dev))
++			continue;
++		res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
++		if (res >= 0)
++			return res;
++	}
++
++	return -ENODEV;
++}
++#endif /* CONFIG_SSB_DRIVER_GIGE */
++
++int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	int err;
++
++	err = ssb_pcicore_plat_dev_init(dev);
++	if (!err)
++		return 0;
++#ifdef CONFIG_SSB_DRIVER_GIGE
++	err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
++	if (err >= 0)
++		return err;
++#endif
++	/* This is not a PCI device on any SSB device. */
++
++	return -ENODEV;
++}
++
++#ifdef CONFIG_SSB_DRIVER_GIGE
++static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
++{
++	const struct pci_dev *pdev = (const struct pci_dev *)data;
++	struct ssb_device *dev;
++	unsigned int i;
++	int res;
++
++	for (i = 0; i < bus->nr_devices; i++) {
++		dev = &(bus->devices[i]);
++		if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
++			continue;
++		if (!dev->dev ||
++		    !dev->dev->driver ||
++		    !device_is_registered(dev->dev))
++			continue;
++		res = ssb_gige_map_irq(dev, pdev);
++		if (res >= 0)
++			return res;
++	}
++
++	return -ENODEV;
++}
++#endif /* CONFIG_SSB_DRIVER_GIGE */
++
++int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++	int res;
++
++	/* Check if this PCI device is a device on a SSB bus or device
++	 * and return the IRQ number for it. */
++
++	res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
++	if (res >= 0)
++		return res;
++#ifdef CONFIG_SSB_DRIVER_GIGE
++	res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
++	if (res >= 0)
++		return res;
++#endif
++	/* This is not a PCI device on any SSB device. */
++
++	return -ENODEV;
++}
+Index: linux-2.6.23.16/include/linux/ssb/ssb.h
+===================================================================
+--- linux-2.6.23.16.orig/include/linux/ssb/ssb.h	2008-02-20 18:32:01.000000000 +0100
++++ linux-2.6.23.16/include/linux/ssb/ssb.h	2008-02-20 18:32:31.000000000 +0100
+@@ -422,5 +422,12 @@ extern int ssb_bus_powerup(struct ssb_bu
+ extern u32 ssb_admatch_base(u32 adm);
+ extern u32 ssb_admatch_size(u32 adm);
+ 
++/* PCI device mapping and fixup routines.
++ * Called from the architecture pcibios init code.
++ * These are only available on SSB_EMBEDDED configurations. */
++#ifdef CONFIG_SSB_EMBEDDED
++int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
++int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
++#endif /* CONFIG_SSB_EMBEDDED */
+ 
+ #endif /* LINUX_SSB_H_ */
+Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h
+===================================================================
+--- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_pci.h	2008-02-20 18:32:01.000000000 +0100
++++ linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h	2008-02-20 18:32:31.000000000 +0100
+@@ -1,6 +1,11 @@
+ #ifndef LINUX_SSB_PCICORE_H_
+ #define LINUX_SSB_PCICORE_H_
+ 
++#include <linux/types.h>
++
++struct pci_dev;
++
++
+ #ifdef CONFIG_SSB_DRIVER_PCICORE
+ 
+ /* PCI core registers. */
+@@ -88,6 +93,9 @@ extern void ssb_pcicore_init(struct ssb_
+ extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+ 					  struct ssb_device *dev);
+ 
++int ssb_pcicore_plat_dev_init(struct pci_dev *d);
++int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
++
+ 
+ #else /* CONFIG_SSB_DRIVER_PCICORE */
+ 
+@@ -107,5 +115,16 @@ int ssb_pcicore_dev_irqvecs_enable(struc
+ 	return 0;
+ }
+ 
++static inline
++int ssb_pcicore_plat_dev_init(struct pci_dev *d)
++{
++	return -ENODEV;
++}
++static inline
++int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++	return -ENODEV;
++}
++
+ #endif /* CONFIG_SSB_DRIVER_PCICORE */
+ #endif /* LINUX_SSB_PCICORE_H_ */
+Index: linux-2.6.23.16/drivers/ssb/main.c
+===================================================================
+--- linux-2.6.23.16.orig/drivers/ssb/main.c	2008-02-20 18:32:01.000000000 +0100
++++ linux-2.6.23.16/drivers/ssb/main.c	2008-02-20 18:32:31.000000000 +0100
+@@ -14,6 +14,7 @@
+ #include <linux/io.h>
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_regs.h>
++#include <linux/ssb/ssb_driver_gige.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/pci.h>
+ 
+@@ -68,6 +69,25 @@ found:
+ }
+ #endif /* CONFIG_SSB_PCIHOST */
+ 
++int ssb_for_each_bus_call(unsigned long data,
++			  int (*func)(struct ssb_bus *bus, unsigned long data))
++{
++	struct ssb_bus *bus;
++	int res;
++
++	ssb_buses_lock();
++	list_for_each_entry(bus, &buses, list) {
++		res = func(bus, data);
++		if (res >= 0) {
++			ssb_buses_unlock();
++			return res;
++		}
++	}
++	ssb_buses_unlock();
++
++	return -ENODEV;
++}
++
+ static struct ssb_device *ssb_device_get(struct ssb_device *dev)
+ {
+ 	if (dev)
+@@ -1175,7 +1195,14 @@ static int __init ssb_modinit(void)
+ 	err = b43_pci_ssb_bridge_init();
+ 	if (err) {
+ 		ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
+-			   "initialization failed");
++			   "initialization failed\n");
++		/* don't fail SSB init because of this */
++		err = 0;
++	}
++	err = ssb_gige_init();
++	if (err) {
++		ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
++			   "driver initialization failed\n");
+ 		/* don't fail SSB init because of this */
+ 		err = 0;
+ 	}
+@@ -1189,6 +1216,7 @@ fs_initcall(ssb_modinit);
+ 
+ static void __exit ssb_modexit(void)
+ {
++	ssb_gige_exit();
+ 	b43_pci_ssb_bridge_exit();
+ 	bus_unregister(&ssb_bustype);
+ }
+Index: linux-2.6.23.16/drivers/ssb/ssb_private.h
+===================================================================
+--- linux-2.6.23.16.orig/drivers/ssb/ssb_private.h	2008-02-20 18:32:01.000000000 +0100
++++ linux-2.6.23.16/drivers/ssb/ssb_private.h	2008-02-20 18:32:31.000000000 +0100
+@@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty
+ extern int ssb_devices_freeze(struct ssb_bus *bus);
+ extern int ssb_devices_thaw(struct ssb_bus *bus);
+ extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
++int ssb_for_each_bus_call(unsigned long data,
++			  int (*func)(struct ssb_bus *bus, unsigned long data));
+ 
+ /* b43_pci_bridge.c */
+ #ifdef CONFIG_SSB_PCIHOST