diff options
| author | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-01-06 19:28:07 +0000 |
|---|---|---|
| committer | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-01-06 19:28:07 +0000 |
| commit | 90fba37c49479ed4e5233dc0d348cdf7d24c9ee1 (patch) | |
| tree | 58af9e3b3204308a2b7853127331f4d693e1b744 /target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h | |
| parent | b59f896089edf83ce4cd1951001b6cc889bdd287 (diff) | |
update brcm-2.4 to 2.4.35.4, integrate new broadcom system code, update broadcom-wl to a contributed version (v4.150.10.5) - no bcm57xx support yet, will follow shortly
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10137 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h')
| -rw-r--r-- | target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h index dec6c2928..615edabb8 100644 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h +++ b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsdram.h @@ -1,7 +1,7 @@ /* * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions. * - * Copyright 2006, Broadcom Corporation + * Copyright 2007, Broadcom Corporation * All Rights Reserved. * * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY @@ -9,7 +9,7 @@ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. * - * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $ + * $Id$ */ #ifndef _SBSDRAM_H @@ -26,16 +26,7 @@ typedef volatile struct sbsdramregs { uint32 pad2; } sbsdramregs_t; -/* SDRAM simulation */ -#ifdef RAMSZ -#define SDRAMSZ RAMSZ -#else -#define SDRAMSZ (4 * 1024 * 1024) -#endif - -extern uchar sdrambuf[SDRAMSZ]; - -#endif /* _LANGUAGE_ASSEMBLY */ +#endif /* !_LANGUAGE_ASSEMBLY */ /* SDRAM initialization control (initcontrol) register bits */ #define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */ |