diff options
| author | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-01-06 19:28:07 +0000 |
|---|---|---|
| committer | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-01-06 19:28:07 +0000 |
| commit | 90fba37c49479ed4e5233dc0d348cdf7d24c9ee1 (patch) | |
| tree | 58af9e3b3204308a2b7853127331f4d693e1b744 /target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h | |
| parent | b59f896089edf83ce4cd1951001b6cc889bdd287 (diff) | |
update brcm-2.4 to 2.4.35.4, integrate new broadcom system code, update broadcom-wl to a contributed version (v4.150.10.5) - no bcm57xx support yet, will follow shortly
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10137 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h')
| -rw-r--r-- | target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h index 8bb45957a..dd468db76 100644 --- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h +++ b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/pcicfg.h @@ -1,7 +1,7 @@ /* * pcicfg.h: PCI configuration constants and structures. * - * Copyright 2006, Broadcom Corporation + * Copyright 2007, Broadcom Corporation * All Rights Reserved. * * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY @@ -9,7 +9,7 @@ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. * - * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $ + * $Id$ */ #ifndef _h_pcicfg_ @@ -170,6 +170,14 @@ typedef struct _pci_config_regs { #undef PCI_CLASS_DOCK #endif /* __NetBSD__ */ +#ifdef EFI +#undef PCI_CLASS_BRIDGE +#undef PCI_CLASS_OLD +#undef PCI_CLASS_DISPLAY +#undef PCI_CLASS_SERIAL +#undef PCI_CLASS_SATELLITE +#endif /* EFI */ + /* Classes and subclasses */ typedef enum { @@ -406,6 +414,11 @@ typedef struct _pciconfig_cap_pwrmgmt { unsigned char data; } pciconfig_cap_pwrmgmt; +#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ +#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ +#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ +#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ + /* Data structure to define the PCIE capability */ typedef struct _pciconfig_cap_pcie { unsigned char capID; @@ -463,7 +476,7 @@ typedef struct _pcie_enhanced_caphdr { * 8KB window, so their address is the "regular" * address plus 4K */ -#define PCI_BAR0_WINSZ 8192 /* bar0 window size */ +#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ |