diff options
| author | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-05-04 22:13:42 +0000 |
|---|---|---|
| committer | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-05-04 22:13:42 +0000 |
| commit | 7ed9009bbdf799be5f9f1446c264b8504f483beb (patch) | |
| tree | ad8e8fd539edd85b202b0fa6a94ffc1dd8a50f39 /target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h | |
| parent | 6c640d00dec772eb9651e25eedbe032e1e802e33 (diff) | |
convert brcm-2.4 to the new target structure
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7092 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h')
| -rw-r--r-- | target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h new file mode 100644 index 000000000..cd771cac3 --- /dev/null +++ b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/hndmips.h @@ -0,0 +1,45 @@ +/* + * HND SiliconBackplane MIPS core software interface. + * + * Copyright 2006, Broadcom Corporation + * All Rights Reserved. + * + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. + * + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $ + */ + +#ifndef _hndmips_h_ +#define _hndmips_h_ + +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base); +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock); +extern void enable_pfc(uint32 mode); +extern uint32 sb_memc_get_ncdl(sb_t *sbh); + +#if defined(BCMPERFSTATS) +/* enable counting - exclusive version. Only one set of counters allowed at a time */ +extern void hndmips_perf_instrcount_enable(void); +extern void hndmips_perf_icachecount_enable(void); +extern void hndmips_perf_dcachecount_enable(void); +/* start and stop counting */ +#define hndmips_perf_start01() \ + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000) +#define hndmips_perf_stop01() \ + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000) +/* retrieve coutners - counters *decrement* */ +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0)) +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1)) +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2)) +/* enable counting - modular version. Each counters can be enabled separately. */ +extern void hndmips_perf_icache_hit_enable(void); +extern void hndmips_perf_icache_miss_enable(void); +extern uint32 hndmips_perf_read_instrcount(void); +extern uint32 hndmips_perf_read_cache_miss(void); +extern uint32 hndmips_perf_read_cache_hit(void); +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */ + +#endif /* _hndmips_h_ */ |