diff options
| author | matteo <matteo@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2010-02-04 10:22:25 +0000 |
|---|---|---|
| committer | matteo <matteo@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2010-02-04 10:22:25 +0000 |
| commit | b1d4c14fc25492c4f08e041bc40507691c5795c5 (patch) | |
| tree | 1476ceb960b16a5ea4ce62f1c7b34861ba5b1dda /target/linux/atheros/patches-2.6.32/002-mips_clocksource_init_war.patch | |
| parent | 0f2836ea5320a63bfde814337dbcfcde2a0821d6 (diff) | |
atheros: 2.6.32 support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19516 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/atheros/patches-2.6.32/002-mips_clocksource_init_war.patch')
| -rw-r--r-- | target/linux/atheros/patches-2.6.32/002-mips_clocksource_init_war.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/target/linux/atheros/patches-2.6.32/002-mips_clocksource_init_war.patch b/target/linux/atheros/patches-2.6.32/002-mips_clocksource_init_war.patch new file mode 100644 index 000000000..3f9970f99 --- /dev/null +++ b/target/linux/atheros/patches-2.6.32/002-mips_clocksource_init_war.patch @@ -0,0 +1,58 @@ +Index: linux-2.6.32.7/arch/mips/kernel/cevt-r4k.c +=================================================================== +--- linux-2.6.32.7.orig/arch/mips/kernel/cevt-r4k.c 2010-02-03 16:59:28.310430064 +0100 ++++ linux-2.6.32.7/arch/mips/kernel/cevt-r4k.c 2010-02-03 16:59:54.578430015 +0100 +@@ -16,6 +16,22 @@ + #include <asm/cevt-r4k.h> + + /* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ ++/* + * The SMTC Kernel for the 34K, 1004K, et. al. replaces several + * of these routines with SMTC-specific variants. + */ +@@ -31,6 +47,7 @@ + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } +@@ -100,22 +117,6 @@ + return (read_c0_cause() >> cp0_compare_irq) & 0x100; + } + +-/* +- * Compare interrupt can be routed and latched outside the core, +- * so a single execution hazard barrier may not be enough to give +- * it time to clear as seen in the Cause register. 4 time the +- * pipeline depth seems reasonably conservative, and empirically +- * works better in configurations with high CPU/bus clock ratios. +- */ +- +-#define compare_change_hazard() \ +- do { \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- } while (0) +- + int c0_compare_int_usable(void) + { + unsigned int delta; |