diff options
author | hauke <hauke@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2009-02-20 16:14:01 +0000 |
---|---|---|
committer | hauke <hauke@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2009-02-20 16:14:01 +0000 |
commit | 58b41997f202fb24c4556fe295ea33ee83d9c5af (patch) | |
tree | d7ae99137bb8279fe45e16ae9d0752b83c295f15 /target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch | |
parent | 099b7c06385d3852363461a08d3804b2845a4698 (diff) |
[atheros]: remove atheros target for kernel 2.6.27.
When support for kernel 2.6.28 is added this is not needed any more.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14582 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch b/target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch deleted file mode 100644 index 03a66ff13..000000000 --- a/target/linux/atheros/patches-2.6.27/902-mips_clocksource_init_war.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -15,6 +15,22 @@ - #include <asm/cevt-r4k.h> - - /* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ -+/* - * The SMTC Kernel for the 34K, 1004K, et. al. replaces several - * of these routines with SMTC-specific variants. - */ -@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } -@@ -99,22 +116,6 @@ static int c0_compare_int_pending(void) - return (read_c0_cause() >> cp0_compare_irq) & 0x100; - } - --/* -- * Compare interrupt can be routed and latched outside the core, -- * so a single execution hazard barrier may not be enough to give -- * it time to clear as seen in the Cause register. 4 time the -- * pipeline depth seems reasonably conservative, and empirically -- * works better in configurations with high CPU/bus clock ratios. -- */ -- --#define compare_change_hazard() \ -- do { \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- } while (0) -- - int c0_compare_int_usable(void) - { - unsigned int delta; |