ar71xx: add kernel support for the QCA9556 SoC

Based on http://patchwork.openwrt.org/patch/3162/

Signed-off-by: Embedded Wireless GmbH <info at embeddedwireless.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35393 3c298f89-4303-0410-b956-a3cf2f4a3e73

7 files changed, 63 insertions, 7 deletions

diff --git a/target/linux/ar71xx/patches-3.7/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch b/target/linux/ar71xx/patches-3.7/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch
new file mode 100644
index 000000000..2d039cb42
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.7/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch
@@ -0,0 +1,56 @@
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -164,6 +164,12 @@ static void __init ath79_detect_sys_type
+ 		rev = id & AR934X_REV_ID_REVISION_MASK;
+ 		break;
+ 
++	case REV_ID_MAJOR_QCA9556:
++		ath79_soc = ATH79_SOC_QCA9556;
++		chip = "9556";
++		rev = id & AR944X_REV_ID_REVISION_MASK;
++		break;
++
+ 	case REV_ID_MAJOR_QCA9558:
+ 		ath79_soc = ATH79_SOC_QCA9558;
+ 		chip = "9558";
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -460,6 +460,7 @@
+ #define REV_ID_MAJOR_AR9341		0x0120
+ #define REV_ID_MAJOR_AR9342		0x1120
+ #define REV_ID_MAJOR_AR9344		0x2120
++#define REV_ID_MAJOR_QCA9556		0x0130
+ #define REV_ID_MAJOR_QCA9558		0x1130
+ 
+ #define AR71XX_REV_ID_MINOR_MASK	0x3
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,7 @@ enum ath79_soc_type {
+ 	ATH79_SOC_AR9341,
+ 	ATH79_SOC_AR9342,
+ 	ATH79_SOC_AR9344,
++	ATH79_SOC_QCA9556,
+ 	ATH79_SOC_QCA9558,
+ };
+ 
+@@ -99,6 +100,11 @@ static inline int soc_is_ar934x(void)
+ 	return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
+ 
++static inline int soc_is_qca9556(void)
++{
++	return ath79_soc == ATH79_SOC_QCA9556;
++}
++
+ static inline int soc_is_qca9558(void)
+ {
+ 	return ath79_soc == ATH79_SOC_QCA9558;
+@@ -106,7 +112,7 @@ static inline int soc_is_qca9558(void)
+ 
+ static inline int soc_is_qca955x(void)
+ {
+-	return soc_is_qca9558();
++	return soc_is_qca9556() || soc_is_qca9558();
+ }
+ 
+ extern void __iomem *ath79_ddr_base;
diff --git a/target/linux/ar71xx/patches-3.7/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch b/target/linux/ar71xx/patches-3.7/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch
index a9845baba..5df56e4eb 100644
--- a/target/linux/ar71xx/patches-3.7/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch
+++ b/target/linux/ar71xx/patches-3.7/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch
@@ -95,7 +95,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  }
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -520,6 +520,8 @@
+@@ -521,6 +521,8 @@
  #define AR71XX_GPIO_REG_INT_ENABLE	0x24
  #define AR71XX_GPIO_REG_FUNC		0x28
  
diff --git a/target/linux/ar71xx/patches-3.7/502-MIPS-ath79-export-ath79_gpio_base.patch b/target/linux/ar71xx/patches-3.7/502-MIPS-ath79-export-ath79_gpio_base.patch
index 0a218a684..73eb8e106 100644
--- a/target/linux/ar71xx/patches-3.7/502-MIPS-ath79-export-ath79_gpio_base.patch
+++ b/target/linux/ar71xx/patches-3.7/502-MIPS-ath79-export-ath79_gpio_base.patch
@@ -13,7 +13,7 @@
  
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -110,6 +110,7 @@ static inline int soc_is_qca955x(void)
+@@ -116,6 +116,7 @@ static inline int soc_is_qca955x(void)
  }
  
  extern void __iomem *ath79_ddr_base;
diff --git a/target/linux/ar71xx/patches-3.7/503-MIPS-ath79-add-flash-acquire-release.patch b/target/linux/ar71xx/patches-3.7/503-MIPS-ath79-add-flash-acquire-release.patch
index 81350ca3b..15e7faac1 100644
--- a/target/linux/ar71xx/patches-3.7/503-MIPS-ath79-add-flash-acquire-release.patch
+++ b/target/linux/ar71xx/patches-3.7/503-MIPS-ath79-add-flash-acquire-release.patch
@@ -27,7 +27,7 @@
 +
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -137,4 +137,7 @@ static inline u32 ath79_reset_rr(unsigne
+@@ -143,4 +143,7 @@ static inline u32 ath79_reset_rr(unsigne
  void ath79_device_reset_set(u32 mask);
  void ath79_device_reset_clear(u32 mask);
  
diff --git a/target/linux/ar71xx/patches-3.7/504-MIPS-ath79-add-ath79_device_reset_get.patch b/target/linux/ar71xx/patches-3.7/504-MIPS-ath79-add-ath79_device_reset_get.patch
index 55780996f..e99b66faa 100644
--- a/target/linux/ar71xx/patches-3.7/504-MIPS-ath79-add-ath79_device_reset_get.patch
+++ b/target/linux/ar71xx/patches-3.7/504-MIPS-ath79-add-ath79_device_reset_get.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -136,6 +136,7 @@ static inline u32 ath79_reset_rr(unsigne
+@@ -142,6 +142,7 @@ static inline u32 ath79_reset_rr(unsigne
  
  void ath79_device_reset_set(u32 mask);
  void ath79_device_reset_clear(u32 mask);
diff --git a/target/linux/ar71xx/patches-3.7/509-MIPS-ath79-process-board-kernel-option.patch b/target/linux/ar71xx/patches-3.7/509-MIPS-ath79-process-board-kernel-option.patch
index 9236c6686..7858a9054 100644
--- a/target/linux/ar71xx/patches-3.7/509-MIPS-ath79-process-board-kernel-option.patch
+++ b/target/linux/ar71xx/patches-3.7/509-MIPS-ath79-process-board-kernel-option.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
-@@ -225,6 +225,8 @@ void __init plat_time_init(void)
+@@ -231,6 +231,8 @@ void __init plat_time_init(void)
  	mips_hpt_frequency = clk_get_rate(clk) / 2;
  }
  
diff --git a/target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch
index aa962059b..fb7d169ad 100644
--- a/target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch
@@ -189,7 +189,7 @@
  #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
-@@ -528,6 +625,12 @@
+@@ -529,6 +626,12 @@
  #define AR71XX_GPIO_REG_INT_ENABLE	0x24
  #define AR71XX_GPIO_REG_FUNC		0x28
  
@@ -202,7 +202,7 @@
  #define AR934X_GPIO_REG_FUNC		0x6c
  
  #define AR71XX_GPIO_COUNT		16
-@@ -559,4 +662,133 @@
+@@ -560,4 +663,133 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7