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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-03-27 19:38:15 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-03-27 19:38:15 +0000
commitac19ad9ae47b97d9e0cd9d7775cbb3589c5602bf (patch)
tree1617354b9a4eab29fd1256dbf2d0d09235fb061d /target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
parentad01160aa28cdabb28fe7357193db82c66a65846 (diff)
ar71xx: improve SPI flash read/write performance
mtd_speedtest results: page write speed old new delta DB120 209 KiB/s 226 KiB/s +8.13% TL-WR1043ND v1 122 KiB/s 148 KiB/s +21.31% TL-WR703N v1 153 KiB/s 194 KiB/s +26.80% TL-MR3220 v1 130 KiB/s 156 KiB/s +20.00% TL-WR2543ND v1 158 KiB/s 202 KiB/s +27.85% TL-WR741ND v2 122 KiB/s 152 KiB/s +24.59% ALFA AP96 229 KiB/s 260 KiB/s +13.54% WNDR3700 202 KiB/s 223 KiB/s +10.40% page read speed old new delta DB120 691 KiB/s 929 KiB/s +34.44% TL-WR1043ND v1 372 KiB/s 754 KiB/s +102.69% TL-WR703N v1 375 KiB/s 745 KiB/s +98.67% TL-MR3220 v1 372 KiB/s 752 KiB/s +102.15% TL-WR2543ND v1 307 KiB/s 564 KiB/s +83.71% TL-WR741ND v2 315 KiB/s 525 KiB/s +66.67% ALFA AP96 515 KiB/s 702 KiB/s +36.31% WNDR3700 515 KiB/s 697 KiB/s +35.34% git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31117 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch')
-rw-r--r--target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch108
1 files changed, 108 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch b/target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
new file mode 100644
index 000000000..6230e5d97
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.2/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
@@ -0,0 +1,108 @@
+From 25e681989198e94656eab9df22b8b761abd2ae26 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 9 Jan 2012 15:00:46 +0100
+Subject: [PATCH 5/7] spi/ath79: avoid multiple initialization of the SPI controller
+
+Currently we are initializing the SPI controller in
+the chip select line function, and that function is
+called once for each SPI device on the bus. If a
+board has multiple SPI devices, the controller will
+be initialized multiple times.
+
+Introduce ath79_spi_{en,dis}able helper functions,
+and call those from probe/response in order to avoid
+the mutliple initialization of the controller.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c | 41 ++++++++++++++++++++++++-----------------
+ 1 files changed, 24 insertions(+), 17 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct
+
+ }
+
+-static int ath79_spi_setup_cs(struct spi_device *spi)
++static void ath79_spi_enable(struct ath79_spi *sp)
+ {
+- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+- struct ath79_spi_controller_data *cdata;
+- int status;
+-
+- cdata = spi->controller_data;
+- if (spi->chip_select && !cdata)
+- return -EINVAL;
+-
+ /* enable GPIO mode */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+
+@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi
+
+ /* TODO: setup speed? */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
++}
++
++static void ath79_spi_disable(struct ath79_spi *sp)
++{
++ /* restore CTRL register */
++ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
++ /* disable GPIO mode */
++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++}
++
++static int ath79_spi_setup_cs(struct spi_device *spi)
++{
++ struct ath79_spi_controller_data *cdata;
++ int status;
++
++ cdata = spi->controller_data;
++ if (spi->chip_select && !cdata)
++ return -EINVAL;
+
+ status = 0;
+ if (spi->chip_select) {
+@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi
+
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-
+ if (spi->chip_select) {
+ struct ath79_spi_controller_data *cdata = spi->controller_data;
+ gpio_free(cdata->gpio);
+ }
+-
+- /* restore CTRL register */
+- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
+- /* disable GPIO mode */
+- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
+ }
+
+ static int ath79_spi_setup(struct spi_device *spi)
+@@ -271,12 +274,15 @@ static __devinit int ath79_spi_probe(str
+ dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
+ sp->rrw_delay);
+
++ ath79_spi_enable(sp);
+ ret = spi_bitbang_start(&sp->bitbang);
+ if (ret)
+- goto err_clk_disable;
++ goto err_disable;
+
+ return 0;
+
++err_disable:
++ ath79_spi_disable(sp);
+ err_clk_disable:
+ clk_disable(sp->clk);
+ err_clk_put:
+@@ -295,6 +301,7 @@ static __devexit int ath79_spi_remove(st
+ struct ath79_spi *sp = platform_get_drvdata(pdev);
+
+ spi_bitbang_stop(&sp->bitbang);
++ ath79_spi_disable(sp);
+ clk_disable(sp->clk);
+ clk_put(sp->clk);
+ iounmap(sp->base);