summaryrefslogtreecommitdiffstats
path: root/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
diff options
context:
space:
mode:
authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2008-11-26 20:00:41 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2008-11-26 20:00:41 +0000
commit7188638a39a72f181e017cb6b33afe758d389068 (patch)
treeddc6afd4848b31cdcabf6123a2b911aa10ae71f8 /target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
parentaedeeb1874e872189927c3c73cc039a2eb250586 (diff)
[ar71xx] ag71xx: introduce SoC specific fuctions for DDR flush and PLL setup
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13369 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h')
-rw-r--r--target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h22
1 files changed, 15 insertions, 7 deletions
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index f68bfff19..e9a69cd56 100644
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -106,13 +106,10 @@ extern enum ar71xx_soc_type ar71xx_soc;
/*
* PLL block
*/
-#define PLL_REG_CPU_PLL_CFG 0x00
-#define PLL_REG_SEC_PLL_CFG 0x04
-#define PLL_REG_CPU_CLK_CTRL 0x08
-#define PLL_REG_ETH_INT0_CLK 0x10
-#define PLL_REG_ETH_INT1_CLK 0x14
-#define PLL_REG_ETH_EXT_CLK 0x18
-#define PLL_REG_PCI_CLK 0x1c
+#define AR71XX_PLL_REG_CPU_CONFIG 0x00
+#define AR71XX_PLL_REG_SEC_CONFIG 0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
#define AR71XX_PLL_DIV_SHIFT 3
#define AR71XX_PLL_DIV_MASK 0x1f
@@ -123,6 +120,14 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
+#define AR71XX_ETH0_PLL_SHIFT 17
+#define AR71XX_ETH1_PLL_SHIFT 19
+
+#define AR91XX_PLL_REG_CPU_CONFIG 0x00
+#define AR91XX_PLL_REG_ETH_CONFIG 0x04
+#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
+#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
+
#define AR91XX_PLL_DIV_SHIFT 0
#define AR91XX_PLL_DIV_MASK 0x3ff
#define AR91XX_DDR_DIV_SHIFT 22
@@ -130,6 +135,9 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR91XX_AHB_DIV_SHIFT 19
#define AR91XX_AHB_DIV_MASK 0x1
+#define AR91XX_ETH0_PLL_SHIFT 20
+#define AR91XX_ETH1_PLL_SHIFT 22
+
extern void __iomem *ar71xx_pll_base;
static inline void ar71xx_pll_wr(unsigned reg, u32 val)