diff options
author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-01-22 22:38:19 +0000 |
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committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-01-22 22:38:19 +0000 |
commit | e0b80e41eb0b24e76285b9355725d2f4f66ada50 (patch) | |
tree | dccbb34ba7bd86e0b13abd8226004f09f5766847 /target/linux/ar71xx/files-3.2/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h | |
parent | 22b99f32a13348502bc0f33b93b70565e941d99c (diff) |
ar71xx: add initial support for 3.2
Tested on the following boards:
ALFA AP96
TL-MR3220 v1
TL-WR1043ND v1
TL-WR2543ND v1
TL-WR703N v1
TL-WR741ND v1
TL-WR741ND v4
WNDR3700 v1
WZR-HP-G300NH
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files-3.2/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h')
-rw-r--r-- | target/linux/ar71xx/files-3.2/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files-3.2/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h b/target/linux/ar71xx/files-3.2/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h new file mode 100644 index 000000000..5b17e94b6 --- /dev/null +++ b/target/linux/ar71xx/files-3.2/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h @@ -0,0 +1,48 @@ +/* + * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define CPLD_GPIO_nLED1 0 +#define CPLD_GPIO_nLED2 1 +#define CPLD_GPIO_nLED3 2 +#define CPLD_GPIO_nLED4 3 +#define CPLD_GPIO_FAN 4 +#define CPLD_GPIO_ALE 5 +#define CPLD_GPIO_CLE 6 +#define CPLD_GPIO_nCE 7 +#define CPLD_GPIO_nLED5 8 + +#define CPLD_NUM_GPIOS 9 + +#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1) +#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2) +#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3) +#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4) +#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN) +#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE) +#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE) +#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE) +#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5) + +struct rb4xx_cpld_platform_data { + unsigned gpio_base; +}; + +extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value); +extern int rb4xx_cpld_read(unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_read_from(unsigned addr, + unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count); |