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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2008-12-09 08:11:49 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2008-12-09 08:11:49 +0000
commit33ffee781631c3aceb764d88b8e13e8d38f573a5 (patch)
tree33a0a021935a16418a6150ccd941849c344526b3 /target/linux/ar71xx/files-2.6.28/arch
parent303c9d4114b984cac9fb61efa47870daaf33d452 (diff)
[ar71xx] preliminary 2.6.28 support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13559 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files-2.6.28/arch')
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/fw/myloader/myloader.h34
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/ar71xx.h424
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h56
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/gpio.h53
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/irq.h17
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/mangle-port.h45
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/pci.h28
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/platform.h77
-rw-r--r--target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/war.h25
9 files changed, 759 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/fw/myloader/myloader.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/fw/myloader/myloader.h
new file mode 100644
index 000000000..8a99d566d
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/fw/myloader/myloader.h
@@ -0,0 +1,34 @@
+/*
+ * Compex's MyLoader specific definitions
+ *
+ * Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ASM_MIPS_FW_MYLOADER_H
+#define _ASM_MIPS_FW_MYLOADER_H
+
+#include <linux/myloader.h>
+
+struct myloader_info {
+ uint32_t vid;
+ uint32_t did;
+ uint32_t svid;
+ uint32_t sdid;
+ uint8_t macs[MYLO_ETHADDR_COUNT][6];
+};
+
+#ifdef CONFIG_MYLOADER
+extern struct myloader_info *myloader_get_info(void) __init;
+#else
+static inline struct myloader_info *myloader_get_info(void)
+{
+ return NULL;
+}
+#endif /* CONFIG_MYLOADER */
+
+#endif /* _ASM_MIPS_FW_MYLOADER_H */
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/ar71xx.h
new file mode 100644
index 000000000..42db7cc24
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -0,0 +1,424 @@
+/*
+ * Atheros AR71xx SoC specific definitions
+ *
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_H
+#define __ASM_MACH_AR71XX_H
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+
+#ifndef __ASSEMBLER__
+
+#define AR71XX_PCI_MEM_BASE 0x10000000
+#define AR71XX_PCI_MEM_SIZE 0x08000000
+#define AR71XX_APB_BASE 0x18000000
+#define AR71XX_GE0_BASE 0x19000000
+#define AR71XX_GE0_SIZE 0x01000000
+#define AR71XX_GE1_BASE 0x1a000000
+#define AR71XX_GE1_SIZE 0x01000000
+#define AR71XX_EHCI_BASE 0x1b000000
+#define AR71XX_EHCI_SIZE 0x01000000
+#define AR71XX_OHCI_BASE 0x1c000000
+#define AR71XX_OHCI_SIZE 0x01000000
+#define AR71XX_SPI_BASE 0x1f000000
+#define AR71XX_SPI_SIZE 0x01000000
+
+#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE 0x10000
+#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
+#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE 0x10000
+#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE 0x10000
+#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE 0x10000
+#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE 0x10000
+#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE 0x10000
+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE 0x10000
+#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
+#define AR71XX_SLIC_SIZE 0x10000
+#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
+#define AR71XX_DMA_SIZE 0x10000
+#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
+#define AR71XX_STEREO_SIZE 0x10000
+
+#define AR71XX_CPU_IRQ_BASE 0
+#define AR71XX_MISC_IRQ_BASE 8
+#define AR71XX_MISC_IRQ_COUNT 8
+#define AR71XX_GPIO_IRQ_BASE 16
+#define AR71XX_GPIO_IRQ_COUNT 16
+#define AR71XX_PCI_IRQ_BASE 32
+#define AR71XX_PCI_IRQ_COUNT 4
+
+#define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
+#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
+#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
+#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
+#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
+#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
+
+#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
+#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
+#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
+#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
+#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
+#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
+#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
+#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
+
+#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
+
+#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
+#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
+#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
+#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 3)
+
+extern u32 ar71xx_ahb_freq;
+extern u32 ar71xx_cpu_freq;
+extern u32 ar71xx_ddr_freq;
+
+enum ar71xx_soc_type {
+ AR71XX_SOC_UNKNOWN,
+ AR71XX_SOC_AR7130,
+ AR71XX_SOC_AR7141,
+ AR71XX_SOC_AR7161,
+ AR71XX_SOC_AR9130,
+ AR71XX_SOC_AR9132
+};
+
+extern enum ar71xx_soc_type ar71xx_soc;
+
+extern unsigned long ar71xx_mach_type;
+
+#define AR71XX_MACH_GENERIC 0
+#define AR71XX_MACH_WP543 1 /* Compex WP543 */
+#define AR71XX_MACH_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */
+#define AR71XX_MACH_RB_433 3 /* MikroTik RouterBOARD 433/433AH */
+#define AR71XX_MACH_RB_450 4 /* MikroTik RouterBOARD 450 */
+#define AR71XX_MACH_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */
+#define AR71XX_MACH_AW_NR580 6 /* AzureWave AW-NR580 */
+#define AR71XX_MACH_AP83 7 /* Atheros AP83 */
+#define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG 0x00
+#define AR71XX_PLL_REG_SEC_CONFIG 0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
+
+#define AR71XX_PLL_DIV_SHIFT 3
+#define AR71XX_PLL_DIV_MASK 0x1f
+#define AR71XX_CPU_DIV_SHIFT 16
+#define AR71XX_CPU_DIV_MASK 0x3
+#define AR71XX_DDR_DIV_SHIFT 18
+#define AR71XX_DDR_DIV_MASK 0x3
+#define AR71XX_AHB_DIV_SHIFT 20
+#define AR71XX_AHB_DIV_MASK 0x7
+
+#define AR71XX_ETH0_PLL_SHIFT 17
+#define AR71XX_ETH1_PLL_SHIFT 19
+
+#define AR91XX_PLL_REG_CPU_CONFIG 0x00
+#define AR91XX_PLL_REG_ETH_CONFIG 0x04
+#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
+#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
+
+#define AR91XX_PLL_DIV_SHIFT 0
+#define AR91XX_PLL_DIV_MASK 0x3ff
+#define AR91XX_DDR_DIV_SHIFT 22
+#define AR91XX_DDR_DIV_MASK 0x3
+#define AR91XX_AHB_DIV_SHIFT 19
+#define AR91XX_AHB_DIV_MASK 0x1
+
+#define AR91XX_ETH0_PLL_SHIFT 20
+#define AR91XX_ETH1_PLL_SHIFT 22
+
+extern void __iomem *ar71xx_pll_base;
+
+static inline void ar71xx_pll_wr(unsigned reg, u32 val)
+{
+ __raw_writel(val, ar71xx_pll_base + reg);
+}
+
+static inline u32 ar71xx_pll_rr(unsigned reg)
+{
+ return __raw_readl(ar71xx_pll_base + reg);
+}
+
+/*
+ * USB_CONFIG block
+ */
+#define USB_CTRL_REG_FLADJ 0x00
+#define USB_CTRL_REG_CONFIG 0x04
+
+extern void __iomem *ar71xx_usb_ctrl_base;
+
+static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
+{
+ __raw_writel(val, ar71xx_usb_ctrl_base + reg);
+}
+
+static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
+{
+ return __raw_readl(ar71xx_usb_ctrl_base + reg);
+}
+
+extern void ar71xx_add_device_usb(void) __init;
+
+/*
+ * GPIO block
+ */
+#define GPIO_REG_OE 0x00
+#define GPIO_REG_IN 0x04
+#define GPIO_REG_OUT 0x08
+#define GPIO_REG_SET 0x0c
+#define GPIO_REG_CLEAR 0x10
+#define GPIO_REG_INT_MODE 0x14
+#define GPIO_REG_INT_TYPE 0x18
+#define GPIO_REG_INT_POLARITY 0x1c
+#define GPIO_REG_INT_PENDING 0x20
+#define GPIO_REG_INT_ENABLE 0x24
+#define GPIO_REG_FUNC 0x28
+
+#define GPIO_FUNC_STEREO_EN BIT(17)
+#define GPIO_FUNC_SLIC_EN BIT(16)
+#define GPIO_FUNC_SPI_CS1_EN BIT(15)
+#define GPIO_FUNC_SPI_CS0_EN BIT(14)
+#define GPIO_FUNC_SPI_EN BIT(13)
+#define GPIO_FUNC_UART_EN BIT(8)
+#define GPIO_FUNC_USB_OC_EN BIT(4)
+#define GPIO_FUNC_USB_CLK_EN BIT(0)
+
+#define AR71XX_GPIO_COUNT 16
+#define AR91XX_GPIO_COUNT 22
+
+extern void __iomem *ar71xx_gpio_base;
+
+static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
+{
+ __raw_writel(value, ar71xx_gpio_base + reg);
+}
+
+static inline u32 ar71xx_gpio_rr(unsigned reg)
+{
+ return __raw_readl(ar71xx_gpio_base + reg);
+}
+
+extern void ar71xx_gpio_init(void) __init;
+extern void ar71xx_gpio_function_enable(u32 mask);
+extern void ar71xx_gpio_function_disable(u32 mask);
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_PCI_WIN0 0x7c
+#define AR71XX_DDR_REG_PCI_WIN1 0x80
+#define AR71XX_DDR_REG_PCI_WIN2 0x84
+#define AR71XX_DDR_REG_PCI_WIN3 0x88
+#define AR71XX_DDR_REG_PCI_WIN4 0x8c
+#define AR71XX_DDR_REG_PCI_WIN5 0x90
+#define AR71XX_DDR_REG_PCI_WIN6 0x94
+#define AR71XX_DDR_REG_PCI_WIN7 0x98
+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
+#define AR71XX_DDR_REG_FLUSH_USB 0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
+
+#define AR91XX_DDR_REG_FLUSH_GE0 0x7c
+#define AR91XX_DDR_REG_FLUSH_GE1 0x80
+#define AR91XX_DDR_REG_FLUSH_USB 0x84
+#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
+
+#define PCI_WIN0_OFFS 0x10000000
+#define PCI_WIN1_OFFS 0x11000000
+#define PCI_WIN2_OFFS 0x12000000
+#define PCI_WIN3_OFFS 0x13000000
+#define PCI_WIN4_OFFS 0x14000000
+#define PCI_WIN5_OFFS 0x15000000
+#define PCI_WIN6_OFFS 0x16000000
+#define PCI_WIN7_OFFS 0x07000000
+
+extern void __iomem *ar71xx_ddr_base;
+
+static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
+{
+ __raw_writel(val, ar71xx_ddr_base + reg);
+}
+
+static inline u32 ar71xx_ddr_rr(unsigned reg)
+{
+ return __raw_readl(ar71xx_ddr_base + reg);
+}
+
+extern void ar71xx_ddr_flush(u32 reg);
+
+/*
+ * PCI block
+ */
+#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE 0x100
+
+#define PCI_REG_CRP_AD_CBE 0x00
+#define PCI_REG_CRP_WRDATA 0x04
+#define PCI_REG_CRP_RDDATA 0x08
+#define PCI_REG_CFG_AD 0x0c
+#define PCI_REG_CFG_CBE 0x10
+#define PCI_REG_CFG_WRDATA 0x14
+#define PCI_REG_CFG_RDDATA 0x18
+#define PCI_REG_PCI_ERR 0x1c
+#define PCI_REG_PCI_ERR_ADDR 0x20
+#define PCI_REG_AHB_ERR 0x24
+#define PCI_REG_AHB_ERR_ADDR 0x28
+
+#define PCI_CRP_CMD_WRITE 0x00010000
+#define PCI_CRP_CMD_READ 0x00000000
+#define PCI_CFG_CMD_READ 0x0000000a
+#define PCI_CFG_CMD_WRITE 0x0000000b
+
+#define PCI_IDSEL_ADL_START 17
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
+#define AR71XX_RESET_REG_WDOG_CTRL 0x08
+#define AR71XX_RESET_REG_WDOG 0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
+#define AR71XX_RESET_REG_RESET_MODULE 0x24
+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
+#define AR71XX_RESET_REG_PERFC0 0x30
+#define AR71XX_RESET_REG_PERFC1 0x34
+#define AR71XX_RESET_REG_REV_ID 0x90
+
+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
+#define AR91XX_RESET_REG_RESET_MODULE 0x1c
+#define AR91XX_RESET_REG_PERF_CTRL 0x20
+#define AR91XX_RESET_REG_PERFC0 0x24
+#define AR91XX_RESET_REG_PERFC1 0x28
+
+#define WDOG_CTRL_LAST_RESET BIT(31)
+#define WDOG_CTRL_ACTION_MASK 3
+#define WDOG_CTRL_ACTION_NONE 0 /* no action */
+#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
+#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
+#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
+
+#define MISC_INT_DMA BIT(7)
+#define MISC_INT_OHCI BIT(6)
+#define MISC_INT_PERFC BIT(5)
+#define MISC_INT_WDOG BIT(4)
+#define MISC_INT_UART BIT(3)
+#define MISC_INT_GPIO BIT(2)
+#define MISC_INT_ERROR BIT(1)
+#define MISC_INT_TIMER BIT(0)
+
+#define PCI_INT_CORE BIT(4)
+#define PCI_INT_DEV2 BIT(2)
+#define PCI_INT_DEV1 BIT(1)
+#define PCI_INT_DEV0 BIT(0)
+
+#define RESET_MODULE_EXTERNAL BIT(28)
+#define RESET_MODULE_FULL_CHIP BIT(24)
+#define RESET_MODULE_CPU_NMI BIT(21)
+#define RESET_MODULE_CPU_COLD BIT(20)
+#define RESET_MODULE_DMA BIT(19)
+#define RESET_MODULE_SLIC BIT(18)
+#define RESET_MODULE_STEREO BIT(17)
+#define RESET_MODULE_DDR BIT(16)
+#define RESET_MODULE_GE1_MAC BIT(13)
+#define RESET_MODULE_GE1_PHY BIT(12)
+#define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
+#define RESET_MODULE_GE0_MAC BIT(9)
+#define RESET_MODULE_GE0_PHY BIT(8)
+#define RESET_MODULE_USB_OHCI_DLL BIT(6)
+#define RESET_MODULE_USB_HOST BIT(5)
+#define RESET_MODULE_USB_PHY BIT(4)
+#define RESET_MODULE_PCI_BUS BIT(1)
+#define RESET_MODULE_PCI_CORE BIT(0)
+
+#define REV_ID_MASK 0xff
+#define REV_ID_CHIP_MASK 0xf3
+#define REV_ID_CHIP_AR7130 0xa0
+#define REV_ID_CHIP_AR7141 0xa1
+#define REV_ID_CHIP_AR7161 0xa2
+#define REV_ID_CHIP_AR9130 0xb0
+#define REV_ID_CHIP_AR9132 0xb1
+
+#define REV_ID_REVISION_MASK 0x3
+#define REV_ID_REVISION_SHIFT 2
+
+extern void __iomem *ar71xx_reset_base;
+
+static inline void ar71xx_reset_wr(unsigned reg, u32 val)
+{
+ __raw_writel(val, ar71xx_reset_base + reg);
+}
+
+static inline u32 ar71xx_reset_rr(unsigned reg)
+{
+ return __raw_readl(ar71xx_reset_base + reg);
+}
+
+extern void ar71xx_device_stop(u32 mask);
+extern void ar71xx_device_start(u32 mask);
+
+/*
+ * SPI block
+ */
+#define SPI_REG_FS 0x00 /* Function Select */
+#define SPI_REG_CTRL 0x04 /* SPI Control */
+#define SPI_REG_IOC 0x08 /* SPI I/O Control */
+#define SPI_REG_RDS 0x0c /* Read Data Shift */
+
+#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
+
+#define SPI_CTRL_RD BIT(6) /* Remap Disable */
+#define SPI_CTRL_DIV_MASK 0x3f
+
+#define SPI_IOC_DO BIT(0) /* Data Out pin */
+#define SPI_IOC_CLK BIT(8) /* CLK pin */
+#define SPI_IOC_CS(n) BIT(16 + (n))
+#define SPI_IOC_CS0 SPI_IOC_CS(0)
+#define SPI_IOC_CS1 SPI_IOC_CS(1)
+#define SPI_IOC_CS2 SPI_IOC_CS(2)
+#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
+
+/*
+ * MII_CTRL block
+ */
+#define MII_REG_MII0_CTRL 0x00
+#define MII_REG_MII1_CTRL 0x04
+
+#define MII0_CTRL_IF_GMII 0
+#define MII0_CTRL_IF_MII 1
+#define MII0_CTRL_IF_RGMII 2
+#define MII0_CTRL_IF_RMII 3
+
+#define MII1_CTRL_IF_RGMII 0
+#define MII1_CTRL_IF_RMII 1
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __ASM_MACH_AR71XX_H */
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h
new file mode 100644
index 000000000..d3560e59b
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
+/*
+ * Atheros AR71xx specific CPU feature overrides
+ *
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 0
+#define cpu_has_32fpr 0
+#define cpu_has_counter 1
+#define cpu_has_watch 1
+#define cpu_has_divec 1
+
+#define cpu_has_prefetch 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc 1
+
+#define cpu_has_mips16 1
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+
+#define cpu_has_mips32r1 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#define cpu_has_dsp 0
+#define cpu_has_mipsmt 0
+
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_64bit_gp_regs 0
+#define cpu_has_64bit_addresses 0
+
+#define cpu_dcache_line_size() 32
+#define cpu_icache_line_size() 32
+
+#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/gpio.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/gpio.h
new file mode 100644
index 000000000..6354d68cf
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/gpio.h
@@ -0,0 +1,53 @@
+/*
+ * Atheros AR71xx GPIO API definitions
+ *
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_MACH_AR71XX_GPIO_H
+#define __ASM_MACH_AR71XX_GPIO_H
+
+#define ARCH_NR_GPIOS 64
+#include <asm-generic/gpio.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+
+extern unsigned long ar71xx_gpio_count;
+extern void __ar71xx_gpio_set_value(unsigned gpio, int value);
+extern int __ar71xx_gpio_get_value(unsigned gpio);
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+ return AR71XX_GPIO_IRQ(gpio);
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return irq - AR71XX_GPIO_IRQ_BASE;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ if (gpio < ar71xx_gpio_count)
+ return __ar71xx_gpio_get_value(gpio);
+
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ if (gpio < ar71xx_gpio_count)
+ __ar71xx_gpio_set_value(gpio, value);
+ else
+ __gpio_set_value(gpio, value);
+}
+
+#define gpio_cansleep __gpio_cansleep
+
+#endif /* __ASM_MACH_AR71XX_GPIO_H */
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/irq.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/irq.h
new file mode 100644
index 000000000..fe6cfeb77
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/irq.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_AR71XX_IRQ_H
+#define __ASM_MACH_AR71XX_IRQ_H
+
+#define MIPS_CPU_IRQ_BASE 0
+#define NR_IRQS 36
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_AR71XX_IRQ_H */
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/mangle-port.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/mangle-port.h
new file mode 100644
index 000000000..126d5b3e6
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/mangle-port.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H
+#define __ASM_MACH_AR71XX_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port) ((port) ^ 3)
+#define __swizzle_addr_w(port) ((port) ^ 2)
+#define __swizzle_addr_l(port) (port)
+#define __swizzle_addr_q(port) (port)
+
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) le16_to_cpu(x)
+# define __mem_ioswabw(a, x) (x)
+# define ioswabl(a, x) le32_to_cpu(x)
+# define __mem_ioswabl(a, x) (x)
+# define ioswabq(a, x) le64_to_cpu(x)
+# define __mem_ioswabq(a, x) (x)
+
+#else
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (x)
+# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define ioswabl(a, x) (x)
+# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define ioswabq(a, x) (x)
+# define __mem_ioswabq(a, x) cpu_to_le64(x)
+
+#endif
+
+#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/pci.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/pci.h
new file mode 100644
index 000000000..9cf536de4
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/pci.h
@@ -0,0 +1,28 @@
+/*
+ * Atheros AR71xx SoC specific PCI definitions
+ *
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_PCI_H
+#define __ASM_MACH_AR71XX_PCI_H
+
+struct ar71xx_pci_irq {
+ int irq;
+ u8 slot;
+ u8 pin;
+};
+
+extern int (*ar71xx_pci_be_handler)(int is_fixup);
+extern int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
+ struct ar71xx_pci_irq *map) __initdata;
+
+extern int ar71xx_pci_init(unsigned nr_irqs,
+ struct ar71xx_pci_irq *map) __init;
+
+#endif /* __ASM_MACH_AR71XX_PCI_H */
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/platform.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/platform.h
new file mode 100644
index 000000000..750418a79
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/platform.h
@@ -0,0 +1,77 @@
+/*
+ * Atheros AR71xx SoC specific platform definitions
+ *
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_PLATFORM_H
+#define __ASM_MACH_AR71XX_PLATFORM_H
+
+#include <linux/if_ether.h>
+#include <linux/skbuff.h>
+#include <linux/phy.h>
+#include <linux/spi/spi.h>
+#include <linux/leds.h>
+#include <linux/gpio_buttons.h>
+
+struct ag71xx_platform_data {
+ phy_interface_t phy_if_mode;
+ u32 phy_mask;
+ int speed;
+ int duplex;
+ u32 reset_bit;
+ u32 mii_if;
+ u8 mac_addr[ETH_ALEN];
+
+ u8 has_gbit:1;
+ u8 is_ar91xx:1;
+
+ void (* ddr_flush)(void);
+ void (* set_pll)(u32 pll);
+};
+
+struct ag71xx_mdio_platform_data {
+ u32 phy_mask;
+};
+
+struct ar71xx_ehci_platform_data {
+ u8 is_ar91xx;
+};
+
+struct ar71xx_spi_platform_data {
+ unsigned bus_num;
+ unsigned num_chipselect;
+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on);
+};
+
+#define AR71XX_SPI_CS_INACTIVE 0
+#define AR71XX_SPI_CS_ACTIVE 1
+
+extern void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
+ struct spi_board_info const *info,
+ unsigned n) __init;
+
+extern void ar71xx_set_mac_base(unsigned char *mac) __init;
+extern void ar71xx_parse_mac_addr(char *mac_str) __init;
+
+extern struct ag71xx_platform_data ar71xx_eth0_data;
+extern struct ag71xx_platform_data ar71xx_eth1_data;
+extern void ar71xx_add_device_eth(unsigned int id) __init;
+
+extern void ar71xx_add_device_mdio(u32 phy_mask) __init;
+
+extern void ar71xx_add_device_leds_gpio(int id,
+ unsigned num_leds,
+ struct gpio_led *leds) __init;
+
+extern void ar71xx_add_device_gpio_buttons(int id,
+ unsigned poll_interval,
+ unsigned nbuttons,
+ struct gpio_button *buttons) __init;
+
+#endif /* __ASM_MACH_AR71XX_PLATFORM_H */
diff --git a/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/war.h b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/war.h
new file mode 100644
index 000000000..1ca6ffdc6
--- /dev/null
+++ b/target/linux/ar71xx/files-2.6.28/arch/mips/include/asm/mach-ar71xx/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_AR71XX_WAR_H
+#define __ASM_MACH_AR71XX_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MACH_AR71XX_WAR_H */