diff options
| author | florian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-07-31 15:52:06 +0000 |
|---|---|---|
| committer | florian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-07-31 15:52:06 +0000 |
| commit | 247c33e26da97e26cc6dde23aad675c8c63d2050 (patch) | |
| tree | d37a75cf59e9fffe2977b01920cefb2f0d3ab534 /target/linux/ar7-2.6/files/include/asm-mips/ar7 | |
| parent | 174f70763e657424848a1b4ebc0835e4d5a204ea (diff) | |
Register the second uart on tnetd7300 and fix the watchdog register for 7200/7300, thanks to DerAgo (#2149)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8280 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar7-2.6/files/include/asm-mips/ar7')
| -rw-r--r-- | target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h b/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h index 9a8348b5b..49e66ff3a 100644 --- a/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h +++ b/target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h @@ -28,27 +28,21 @@ #define AR7_REGS_BASE 0x08610000 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000) -#define AR7_REGS_EMIF (AR7_REGS_BASE + 0x0800) #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900) -#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) -#define AR7_REGS_WDT (AR7_REGS_BASE + 0x0b00) -#define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00) -#define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00) +#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) // 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) -#define AR7_REGS_UART1 (AR7_REGS_BASE + 0x0f00) -#define AR7_REGS_I2C (AR7_REGS_BASE + 0x1000) -#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) -#define AR7_REGS_DMA (AR7_REGS_BASE + 0x1400) #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) -#define AR7_REGS_BIST (AR7_REGS_BASE + 0x1700) #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1A00) #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00) #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1E00) -#define AR7_REGS_FSER (AR7_REGS_BASE + 0x2000) #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) +#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00) +#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) +#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) + #define AR7_RESET_PEREPHERIAL 0x0 #define AR7_RESET_SOFTWARE 0x4 #define AR7_RESET_STATUS 0x8 @@ -64,8 +58,6 @@ #define AR7_GPIO_DIR 0x8 #define AR7_GPIO_ENABLE 0xC -#define AR7_GPIO_BIT_STATUS_LED 8 - #define AR7_CHIP_7100 0x18 #define AR7_CHIP_7200 0x2b #define AR7_CHIP_7300 0x05 @@ -131,6 +123,7 @@ static inline int ar7_has_high_cpmac(void) } } #define ar7_has_high_vlynq ar7_has_high_cpmac +#define ar7_has_second_uart ar7_has_high_cpmac static inline void ar7_device_enable(u32 bit) { |