[mac80211] Update to compat-wireless-2009-05-01

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15536 3c298f89-4303-0410-b956-a3cf2f4a3e73
author: hauke <hauke@3c298f89-4303-0410-b956-a3cf2f4a3e73> 2009-05-01 13:43:12 +0000
committer: hauke <hauke@3c298f89-4303-0410-b956-a3cf2f4a3e73> 2009-05-01 13:43:12 +0000
commit: 80be62eefc21797174acf9bfc9c98a2110b0f856 (patch)
tree: d6243c804c302dcd159ddf3745d614ceb300b6f4 /package
parent: 21dcc33bffe7fff29fe97f91c05ec76de920e545 (diff)
24 files changed, 397 insertions, 6468 deletions
diff --git a/package/mac80211/Makefile b/package/mac80211/Makefile
index ac65da2a8..d3f9e83af 100644
--- a/package/mac80211/Makefile
+++ b/package/mac80211/Makefile
@@ -17,12 +17,12 @@ ifneq ($(CONFIG_LINUX_2_6_21)$(CONFIG_LINUX_2_6_23)$(CONFIG_LINUX_2_6_24)$(CONFI
   PKG_MD5SUM:=9563ceeed86bca0859ad5f010623277c
   PATCH_DIR:=./patches-old
 else
-  PKG_VERSION:=2009-03-31
-  PKG_RELEASE:=2
+  PKG_VERSION:=2009-05-01
+  PKG_RELEASE:=1
   PKG_SOURCE_URL:= \
-	http://www.orbit-lab.org/kernel/compat-wireless-2.6/2009/03 \
+	http://www.orbit-lab.org/kernel/compat-wireless-2.6/2009/05 \
 	http://wireless.kernel.org/download/compat-wireless-2.6
-  PKG_MD5SUM:=b5b2159081c36dd6c318a28eddf7e646
+  PKG_MD5SUM:=abc949ec3f7cc57302cca814d9b9c6cd
 endif
 
 PKG_SOURCE:=compat-wireless-$(PKG_VERSION).tar.bz2
@@ -234,12 +234,25 @@ define KernelPackage/zd1211rw
   AUTOLOAD:=$(call AutoLoad,60,zd1211rw)
 endef
 
+
+define KernelPackage/ath
+  $(call KernelPackage/mac80211/Default)
+  TITLE:=Atheros common driver part
+  DEPENDS+= @PCI_SUPPORT +kmod-mac80211
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,26,ath)
+endef
+
+define KernelPackage/ath/description
+ This module contains some common parts needed by Atheros Wireless drivers.
+endef
+
 define KernelPackage/ath5k
   $(call KernelPackage/mac80211/Default)
   TITLE:=Atheros 5xxx wireless cards support
   URL:=http://linuxwireless.org/en/users/Drivers/ath5k
-  DEPENDS+= @PCI_SUPPORT +kmod-mac80211
-  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath5k/ath5k.$(LINUX_KMOD_SUFFIX)
+  DEPENDS+= +kmod-ath
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath5k/ath5k.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,27,ath5k)
 endef
 
@@ -252,8 +265,8 @@ define KernelPackage/ath9k
   $(call KernelPackage/mac80211/Default)
   TITLE:=Atheros 802.11n wireless cards support
   URL:=http://linuxwireless.org/en/users/Drivers/ath9k
-  DEPENDS+= @PCI_SUPPORT +kmod-mac80211 @!LINUX_2_6_21||!LINUX_2_6_23||!LINUX_2_6_24||!LINUX_2_6_25||!LINUX_2_6_26
-  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath9k/ath9k.$(LINUX_KMOD_SUFFIX)
+  DEPENDS+= +kmod-ath @!LINUX_2_6_21||!LINUX_2_6_23||!LINUX_2_6_24||!LINUX_2_6_25||!LINUX_2_6_26
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k.$(LINUX_KMOD_SUFFIX)
   AUTOLOAD:=$(call AutoLoad,27,ath9k)
 endef
 
@@ -386,7 +399,7 @@ BUILDFLAGS:= \
 	$(if $(CONFIG_PCI),-DCONFIG_SSB_SPROM) \
 	$(if $(CONFIG_LEDS_TRIGGERS), -DCONFIG_MAC80211_LEDS -DCONFIG_LEDS_TRIGGERS -DCONFIG_B43_LEDS -DCONFIG_B43LEGACY_LEDS) \
 	$(if $(CONFIG_RFKILL),-DCONFIG_B43_RFKILL -DCONFIG_B43LEGACY_RFKILL) \
-	$(if $(CONFIG_HW_RANDOM),-DCONFIG_B43_HWRNG) \
+	$(if $(CONFIG_HW_RANDOM),-DCONFIG_B43_HWRNG -DCONFIG_B43LEGACY_HWRNG) \
 	$(if $(CONFIG_PCMCIA),-DCONFIG_SSB_PCMCIAHOST_POSSIBLE -DCONFIG_SSB_PCMCIAHOST -DCONFIG_B43_PCMCIA -DCONFIG_B43_PIO) \
 	$(if $(CONFIG_DEBUG_FS), -DCONFIG_MAC80211_DEBUGFS) \
 	-D__CONFIG_MAC80211_RC_DEFAULT=minstrel \
@@ -416,6 +429,7 @@ MAKE_OPTS:= \
 	CONFIG_B43LEGACY_LEDS=$(CONFIG_LEDS_TRIGGERS) \
 	CONFIG_B43_LEDS=$(CONFIG_LEDS_TRIGGERS) \
 	$(if $(CONFIG_HW_RANDOM),CONFIG_B43_HWRNG=y,CONFIG_B43_HWRNG=n) \
+	$(if $(CONFIG_HW_RANDOM),CONFIG_B43LEGACY_HWRNG=y,CONFIG_B43LEGACY_HWRNG=n) \
 	$(if $(CONFIG_PACKAGE_kmod-b43),CONFIG_B43=m) \
 	$(if $(CONFIG_PACKAGE_kmod-b43legacy),CONFIG_B43LEGACY=m) \
 	KLIB_BUILD="$(LINUX_DIR)" \
@@ -549,5 +563,6 @@ $(eval $(call KernelPackage,rt2800-usb))
 $(eval $(call KernelPackage,zd1211rw))
 $(eval $(call KernelPackage,mac80211-hwsim))
 $(eval $(call KernelPackage,ath9k))
+$(eval $(call KernelPackage,ath))
 $(eval $(call KernelPackage,b43))
 $(eval $(call KernelPackage,b43legacy))
diff --git a/package/mac80211/patches/007-remove_unused_stuff.patch b/package/mac80211/patches/007-remove_unused_stuff.patch
index dc93a7f1d..e22b91f1d 100644
--- a/package/mac80211/patches/007-remove_unused_stuff.patch
+++ b/package/mac80211/patches/007-remove_unused_stuff.patch
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -104,10 +104,10 @@ CONFIG_MAC80211_MESH=y
+@@ -107,10 +107,10 @@ CONFIG_MAC80211_MESH=y
  CONFIG_CFG80211=m
  # CONFIG_CFG80211_REG_DEBUG=y
  
@@ -14,8 +14,8 @@
 +# CONFIG_LIB80211_CRYPT_TKIP=m
  # CONFIG_LIB80211_DEBUG=y
  
- CONFIG_NL80211=y
-@@ -128,54 +128,54 @@ CONFIG_ATH9K=m
+ CONFIG_WIRELESS_OLD_REGULATORY=n
+@@ -127,56 +127,56 @@ CONFIG_ATH9K=m
  # CONFIG_ATH9K_DEBUG=y
  
  
@@ -41,12 +41,14 @@
  
  
 -CONFIG_B43=m
+-CONFIG_B43_HWRNG=y
 -CONFIG_B43_PCI_AUTOSELECT=y
 -CONFIG_B43_PCICORE_AUTOSELECT=y
 -CONFIG_B43_PCMCIA=y
 -CONFIG_B43_PIO=y
 -CONFIG_B43_LEDS=y
 +# CONFIG_B43=m
++# CONFIG_B43_HWRNG=y
 +# CONFIG_B43_PCI_AUTOSELECT=y
 +# CONFIG_B43_PCICORE_AUTOSELECT=y
 +# CONFIG_B43_PCMCIA=y
@@ -57,10 +59,12 @@
  # CONFIG_B43_FORCE_PIO=y
  
 -CONFIG_B43LEGACY=m
+-CONFIG_B43LEGACY_HWRNG=y
 -CONFIG_B43LEGACY_PCI_AUTOSELECT=y
 -CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
 -CONFIG_B43LEGACY_LEDS=y
 +# CONFIG_B43LEGACY=m
++# CONFIG_B43LEGACY_HWRNG=y
 +# CONFIG_B43LEGACY_PCI_AUTOSELECT=y
 +# CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
 +# CONFIG_B43LEGACY_LEDS=y
@@ -99,7 +103,7 @@
  # CONFIG_IPW2200_DEBUG=y
  # The above enables use a second interface prefixed 'rtap'.
  #           Example usage:
-@@ -190,27 +190,27 @@ CONFIG_IPW2200_QOS=y
+@@ -191,27 +191,27 @@ CONFIG_IPW2200_QOS=y
  #
  # % echo 1 > /sys/bus/pci/drivers/ipw2200/*/rtap_iface
  
@@ -142,7 +146,7 @@
  
  CONFIG_RT2X00_LIB_PCI=m
  CONFIG_RT2400PCI=m
-@@ -226,16 +226,16 @@ CONFIG_RT61PCI=m
+@@ -227,16 +227,16 @@ CONFIG_RT61PCI=m
  NEED_RT2X00_FIRMWARE=y
  endif
  
@@ -163,7 +167,7 @@
  
  # USB Drivers
  ifneq ($(CONFIG_USB),)
-@@ -249,21 +249,21 @@ CONFIG_ZD1211RW=m
+@@ -250,21 +250,21 @@ CONFIG_ZD1211RW=m
  # is only wireless RNDIS chip known to date.
  # Note: this depends on CONFIG_USB_NET_RNDIS_HOST and CONFIG_USB_NET_CDCETHER
  # it also requires new RNDIS_HOST and CDC_ETHER modules which we add
@@ -192,7 +196,7 @@
  endif
  
  # RT2500USB does not require firmware
-@@ -301,20 +301,20 @@ CONFIG_P54_COMMON=m
+@@ -306,20 +306,20 @@ CONFIG_ATH_COMMON=m
  
  
  # Sonics Silicon Backplane
diff --git a/package/mac80211/patches/300-rt2x00-Move-Move-pci_dev-specific-access-to-rt2x00p.patch b/package/mac80211/patches/300-rt2x00-Move-Move-pci_dev-specific-access-to-rt2x00p.patch
deleted file mode 100644
index 6ef7637b1..000000000
--- a/package/mac80211/patches/300-rt2x00-Move-Move-pci_dev-specific-access-to-rt2x00p.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-From 9ed8a41a30916a79529552872e8d1a6175d37398 Mon Sep 17 00:00:00 2001
-From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:30:14 +0100
-Subject: [PATCH 1/9] rt2x00: Move Move pci_dev specific access to rt2x00pci
-
-pci_dev->irq and pci_name(pci_dev) access should be limited
-to rt2x00pci only. This is more generic and allows a rt2x00 pci
-driver to be controlled as PCI device but also as platform driver
-(needed for rt2800pci SoC support).
-
-Signed-off-by: Felix Fietkau <nbd@openwrt.org>
-Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
----
- drivers/net/wireless/rt2x00/rt2400pci.c |    2 +-
- drivers/net/wireless/rt2x00/rt2500pci.c |    2 +-
- drivers/net/wireless/rt2x00/rt2x00.h    |   18 ++++++++++++++++++
- drivers/net/wireless/rt2x00/rt2x00pci.c |   16 ++++++++++++----
- drivers/net/wireless/rt2x00/rt61pci.c   |    7 +------
- drivers/net/wireless/rt2x00/rt61pci.h   |    6 ------
- 6 files changed, 33 insertions(+), 18 deletions(-)
-
---- a/drivers/net/wireless/rt2x00/rt2400pci.c
-+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
-@@ -1361,7 +1361,7 @@ static int rt2400pci_init_eeprom(struct 
- 	 */
- 	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
- 	rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
--	rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
-+	rt2x00_set_chip_rf(rt2x00dev, value, reg);
- 
- 	if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
- 	    !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
---- a/drivers/net/wireless/rt2x00/rt2500pci.c
-+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
-@@ -1525,7 +1525,7 @@ static int rt2500pci_init_eeprom(struct 
- 	 */
- 	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
- 	rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
--	rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
-+	rt2x00_set_chip_rf(rt2x00dev, value, reg);
- 
- 	if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
- 	    !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
---- a/drivers/net/wireless/rt2x00/rt2x00.h
-+++ b/drivers/net/wireless/rt2x00/rt2x00.h
-@@ -672,6 +672,12 @@ struct rt2x00_dev {
- 	unsigned long flags;
- 
- 	/*
-+	 * Device information, Bus IRQ and name (PCI, SoC)
-+	 */
-+	int irq;
-+	const char *name;
-+
-+	/*
- 	 * Chipset identification.
- 	 */
- 	struct rt2x00_chip chip;
-@@ -860,6 +866,18 @@ static inline void rt2x00_set_chip(struc
- 	rt2x00dev->chip.rev = rev;
- }
- 
-+static inline void rt2x00_set_chip_rt(struct rt2x00_dev *rt2x00dev,
-+				      const u16 rt)
-+{
-+	rt2x00dev->chip.rt = rt;
-+}
-+
-+static inline void rt2x00_set_chip_rf(struct rt2x00_dev *rt2x00dev,
-+				      const u16 rf, const u32 rev)
-+{
-+	rt2x00_set_chip(rt2x00dev, rt2x00dev->chip.rt, rf, rev);
-+}
-+
- static inline char rt2x00_rt(const struct rt2x00_chip *chipset, const u16 chip)
- {
- 	return (chipset->rt == chip);
---- a/drivers/net/wireless/rt2x00/rt2x00pci.c
-+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
-@@ -170,7 +170,6 @@ static void rt2x00pci_free_queue_dma(str
- 
- int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
- {
--	struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
- 	struct data_queue *queue;
- 	int status;
- 
-@@ -186,11 +185,11 @@ int rt2x00pci_initialize(struct rt2x00_d
- 	/*
- 	 * Register interrupt handler.
- 	 */
--	status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
--			     IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
-+	status = request_irq(rt2x00dev->irq, rt2x00dev->ops->lib->irq_handler,
-+			     IRQF_SHARED, rt2x00dev->name, rt2x00dev);
- 	if (status) {
- 		ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
--		      pci_dev->irq, status);
-+		      rt2x00dev->irq, status);
- 		goto exit;
- 	}
- 
-@@ -270,6 +269,7 @@ int rt2x00pci_probe(struct pci_dev *pci_
- 	struct ieee80211_hw *hw;
- 	struct rt2x00_dev *rt2x00dev;
- 	int retval;
-+	u16 chip;
- 
- 	retval = pci_request_regions(pci_dev, pci_name(pci_dev));
- 	if (retval) {
-@@ -307,6 +307,14 @@ int rt2x00pci_probe(struct pci_dev *pci_
- 	rt2x00dev->dev = &pci_dev->dev;
- 	rt2x00dev->ops = ops;
- 	rt2x00dev->hw = hw;
-+	rt2x00dev->irq = pci_dev->irq;
-+	rt2x00dev->name = pci_name(pci_dev);
-+
-+	/*
-+	 * Determine RT chipset by reading PCI header.
-+	 */
-+	pci_read_config_word(pci_dev, PCI_DEVICE_ID, &chip);
-+	rt2x00_set_chip_rt(rt2x00dev, chip);
- 
- 	retval = rt2x00pci_alloc_reg(rt2x00dev);
- 	if (retval)
---- a/drivers/net/wireless/rt2x00/rt61pci.c
-+++ b/drivers/net/wireless/rt2x00/rt61pci.c
-@@ -2308,7 +2308,6 @@ static int rt61pci_init_eeprom(struct rt
- 	u32 reg;
- 	u16 value;
- 	u16 eeprom;
--	u16 device;
- 
- 	/*
- 	 * Read EEPROM word for configuration.
-@@ -2317,14 +2316,10 @@ static int rt61pci_init_eeprom(struct rt
- 
- 	/*
- 	 * Identify RF chipset.
--	 * To determine the RT chip we have to read the
--	 * PCI header of the device.
- 	 */
--	pci_read_config_word(to_pci_dev(rt2x00dev->dev),
--			     PCI_CONFIG_HEADER_DEVICE, &device);
- 	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
- 	rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
--	rt2x00_set_chip(rt2x00dev, device, value, reg);
-+	rt2x00_set_chip_rf(rt2x00dev, value, reg);
- 
- 	if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
- 	    !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
---- a/drivers/net/wireless/rt2x00/rt61pci.h
-+++ b/drivers/net/wireless/rt2x00/rt61pci.h
-@@ -63,12 +63,6 @@
-  */
- 
- /*
-- * PCI Configuration Header
-- */
--#define PCI_CONFIG_HEADER_VENDOR	0x0000
--#define PCI_CONFIG_HEADER_DEVICE	0x0002
--
--/*
-  * HOST_CMD_CSR: For HOST to interrupt embedded processor
-  */
- #define HOST_CMD_CSR			0x0008
diff --git a/package/mac80211/patches/305-rt2x00-Add-rt2x00soc-bus-module.patch b/package/mac80211/patches/301-rt2x00-Add-rt2x00soc-bus-module.patch
index b09b0d639..bacc1d75a 100644
--- a/package/mac80211/patches/305-rt2x00-Add-rt2x00soc-bus-module.patch
+++ b/package/mac80211/patches/301-rt2x00-Add-rt2x00soc-bus-module.patch
@@ -1,12 +1,14 @@
-From 18b2be31a35dc8bd216e60e3c9d8d8e7b2179aed Mon Sep 17 00:00:00 2001
+From ff22aa7443c57f49f9fdaf703aa7035c1b13d7f4 Mon Sep 17 00:00:00 2001
 From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:38:40 +0100
-Subject: [PATCH 6/9] rt2x00: Add rt2x00soc bus module
+Date: Sun, 26 Apr 2009 15:49:55 +0200
+Subject: [PATCH 1/4] rt2x00: Add rt2x00soc bus module
 
 Add new library module for SoC drivers.
 This is needed to fully support the platform
 driver part of rt2800pci.
 
+Based on original patch from Felix.
+
 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 ---
diff --git a/package/mac80211/patches/301-rt2x00-Fix-Sparse-warning.patch b/package/mac80211/patches/301-rt2x00-Fix-Sparse-warning.patch
deleted file mode 100644
index caac9a409..000000000
--- a/package/mac80211/patches/301-rt2x00-Fix-Sparse-warning.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 0a807e9fbd915d2c0cc30870403a571478a9191b Mon Sep 17 00:00:00 2001
-From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:31:25 +0100
-Subject: [PATCH 2/9] rt2x00: Fix Sparse warning
-
-rt2x00link_reset_qual() is not declared in a header,
-and is only internally used within rt2x00link.c.
-It should be declared as static.
-
-Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
----
- drivers/net/wireless/rt2x00/rt2x00link.c |    2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
---- a/drivers/net/wireless/rt2x00/rt2x00link.c
-+++ b/drivers/net/wireless/rt2x00/rt2x00link.c
-@@ -387,7 +387,7 @@ void rt2x00link_reset_tuner(struct rt2x0
- 		rt2x00link_antenna_reset(rt2x00dev);
- }
- 
--void rt2x00link_reset_qual(struct rt2x00_dev *rt2x00dev)
-+static void rt2x00link_reset_qual(struct rt2x00_dev *rt2x00dev)
- {
- 	struct link_qual *qual = &rt2x00dev->link.qual;
- 
diff --git a/package/mac80211/patches/302-rt2x00-Don-t-free-register-information-on-suspend.patch b/package/mac80211/patches/302-rt2x00-Don-t-free-register-information-on-suspend.patch
deleted file mode 100644
index 11ad79d08..000000000
--- a/package/mac80211/patches/302-rt2x00-Don-t-free-register-information-on-suspend.patch
+++ /dev/null
@@ -1,95 +0,0 @@
-From 76b0fa91af8ca33cd68f52f2d02a05c488777f58 Mon Sep 17 00:00:00 2001
-From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:32:07 +0100
-Subject: [PATCH 3/9] rt2x00: Don't free register information on suspend
-
-After suspend & resume the rt2x00 devices won't wakeup
-anymore due to a broken register information setup.
-The most important problem is the release of the EEPROM
-buffer which is completely cleared and never read again
-after the suspend.
-
-Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
----
- drivers/net/wireless/rt2x00/rt2x00pci.c |   18 +-----------------
- drivers/net/wireless/rt2x00/rt2x00usb.c |   18 +-----------------
- 2 files changed, 2 insertions(+), 34 deletions(-)
-
---- a/drivers/net/wireless/rt2x00/rt2x00pci.c
-+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
-@@ -377,8 +377,6 @@ int rt2x00pci_suspend(struct pci_dev *pc
- 	if (retval)
- 		return retval;
- 
--	rt2x00pci_free_reg(rt2x00dev);
--
- 	pci_save_state(pci_dev);
- 	pci_disable_device(pci_dev);
- 	return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
-@@ -389,7 +387,6 @@ int rt2x00pci_resume(struct pci_dev *pci
- {
- 	struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
- 	struct rt2x00_dev *rt2x00dev = hw->priv;
--	int retval;
- 
- 	if (pci_set_power_state(pci_dev, PCI_D0) ||
- 	    pci_enable_device(pci_dev) ||
-@@ -398,20 +395,7 @@ int rt2x00pci_resume(struct pci_dev *pci
- 		return -EIO;
- 	}
- 
--	retval = rt2x00pci_alloc_reg(rt2x00dev);
--	if (retval)
--		return retval;
--
--	retval = rt2x00lib_resume(rt2x00dev);
--	if (retval)
--		goto exit_free_reg;
--
--	return 0;
--
--exit_free_reg:
--	rt2x00pci_free_reg(rt2x00dev);
--
--	return retval;
-+	return rt2x00lib_resume(rt2x00dev);
- }
- EXPORT_SYMBOL_GPL(rt2x00pci_resume);
- #endif /* CONFIG_PM */
---- a/drivers/net/wireless/rt2x00/rt2x00usb.c
-+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
-@@ -702,8 +702,6 @@ int rt2x00usb_suspend(struct usb_interfa
- 	if (retval)
- 		return retval;
- 
--	rt2x00usb_free_reg(rt2x00dev);
--
- 	/*
- 	 * Decrease usbdev refcount.
- 	 */
-@@ -717,24 +715,10 @@ int rt2x00usb_resume(struct usb_interfac
- {
- 	struct ieee80211_hw *hw = usb_get_intfdata(usb_intf);
- 	struct rt2x00_dev *rt2x00dev = hw->priv;
--	int retval;
- 
- 	usb_get_dev(interface_to_usbdev(usb_intf));
- 
--	retval = rt2x00usb_alloc_reg(rt2x00dev);
--	if (retval)
--		return retval;
--
--	retval = rt2x00lib_resume(rt2x00dev);
--	if (retval)
--		goto exit_free_reg;
--
--	return 0;
--
--exit_free_reg:
--	rt2x00usb_free_reg(rt2x00dev);
--
--	return retval;
-+	return rt2x00lib_resume(rt2x00dev);
- }
- EXPORT_SYMBOL_GPL(rt2x00usb_resume);
- #endif /* CONFIG_PM */
diff --git a/package/mac80211/patches/307-rt2x00-Implement-support-for-rt2800pci.patch b/package/mac80211/patches/302-rt2x00-Implement-support-for-rt2800pci.patch
index 6b66d8523..7584e5a7d 100644
--- a/package/mac80211/patches/307-rt2x00-Implement-support-for-rt2800pci.patch
+++ b/package/mac80211/patches/302-rt2x00-Implement-support-for-rt2800pci.patch
@@ -1,7 +1,7 @@
-From b7dcb460c4c441ce52b3c5ce30d65e1ecfbb30ad Mon Sep 17 00:00:00 2001
+From 67432230daedc23f808b79173703e27675fd0659 Mon Sep 17 00:00:00 2001
 From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:46:46 +0100
-Subject: [PATCH 8/9] rt2x00: Implement support for rt2800pci
+Date: Sun, 26 Apr 2009 15:54:03 +0200
+Subject: [PATCH 2/4] rt2x00: Implement support for rt2800pci
 
 Add support for the rt2800pci chipset.
 
@@ -15,25 +15,26 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 ---
  drivers/net/wireless/rt2x00/Kconfig     |   26 +
  drivers/net/wireless/rt2x00/Makefile    |    1 +
- drivers/net/wireless/rt2x00/rt2800pci.c | 3244 +++++++++++++++++++++++++++++++
+ drivers/net/wireless/rt2x00/rt2800pci.c | 3245 +++++++++++++++++++++++++++++++
  drivers/net/wireless/rt2x00/rt2800pci.h | 1927 ++++++++++++++++++
  drivers/net/wireless/rt2x00/rt2x00.h    |    6 +
- 5 files changed, 5204 insertions(+), 0 deletions(-)
+ 5 files changed, 5205 insertions(+), 0 deletions(-)
  create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
  create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
 
 --- a/drivers/net/wireless/rt2x00/Makefile
 +++ b/drivers/net/wireless/rt2x00/Makefile
-@@ -17,5 +17,6 @@ obj-$(CONFIG_RT2X00_LIB_USB)		+= rt2x00u
+@@ -17,6 +17,7 @@ obj-$(CONFIG_RT2X00_LIB_USB)		+= rt2x00u
  obj-$(CONFIG_RT2400PCI)			+= rt2400pci.o
  obj-$(CONFIG_RT2500PCI)			+= rt2500pci.o
  obj-$(CONFIG_RT61PCI)			+= rt61pci.o
 +obj-$(CONFIG_RT2800PCI)			+= rt2800pci.o
  obj-$(CONFIG_RT2500USB)			+= rt2500usb.o
  obj-$(CONFIG_RT73USB)			+= rt73usb.o
+ obj-$(CONFIG_RT2800USB)			+= rt2800usb.o
 --- /dev/null
 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
-@@ -0,0 +1,3244 @@
+@@ -0,0 +1,3245 @@
 +/*
 +	Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
 +	<http://rt2x00.serialmonkey.com>
@@ -759,23 +760,16 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
 +				 struct antenna_setup *ant)
 +{
-+	u16 eeprom;
 +	u8 r1;
 +	u8 r3;
 +
-+	/*
-+	 * FIXME: Use requested antenna configuration.
-+	 */
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-+
 +	rt2800pci_bbp_read(rt2x00dev, 1, &r1);
 +	rt2800pci_bbp_read(rt2x00dev, 3, &r3);
 +
 +	/*
 +	 * Configure the TX antenna.
 +	 */
-+	switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
++	switch ((int)ant->tx) {
 +	case 1:
 +		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 +		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
@@ -791,7 +785,7 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +	/*
 +	 * Configure the RX antenna.
 +	 */
-+	switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
++	switch ((int)ant->rx) {
 +	case 1:
 +		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 +		break;
@@ -835,22 +829,15 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +					  struct rf_channel *rf,
 +					  struct channel_info *info)
 +{
-+	u16 eeprom;
-+
 +	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 +
-+	/*
-+	 * Determine antenna settings from EEPROM
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-+
-+	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
++	if (rt2x00dev->default_ant.tx == 1)
 +		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 +
-+	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
++	if (rt2x00dev->default_ant.rx == 1) {
 +		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 +		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
-+	} else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
++	} else if (rt2x00dev->default_ant.rx == 2)
 +		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 +
 +	if (rf->channel > 14) {
@@ -929,12 +916,8 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 +	rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
 +
-+	if (conf_is_ht40(conf))
-+		rt2800pci_rfcsr_write(rt2x00dev, 24,
-+				      rt2x00dev->calibration_bw40);
-+	else
-+		rt2800pci_rfcsr_write(rt2x00dev, 24,
-+				      rt2x00dev->calibration_bw20);
++	rt2800pci_rfcsr_write(rt2x00dev, 24,
++			      rt2x00dev->calibration[conf_is_ht40(conf)]);
 +
 +	rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
 +	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
@@ -948,14 +931,8 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +{
 +	u32 reg;
 +	unsigned int tx_pin;
-+	u16 eeprom;
 +	u8 bbp;
 +
-+	/*
-+	 * Determine antenna settings from EEPROM
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-+
 +	if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 +		rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
 +	else
@@ -995,13 +972,13 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +	tx_pin = 0;
 +
 +	/* Turn on unused PA or LNA when not using 1T or 1R */
-+	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
++	if (rt2x00dev->default_ant.tx != 1) {
 +		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 +		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 +	}
 +
 +	/* Turn on unused PA or LNA when not using 1T or 1R */
-+	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
++	if (rt2x00dev->default_ant.rx != 1) {
 +		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 +		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 +	}
@@ -1930,9 +1907,9 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +	/*
 +	 * Set RX Filter calibration for 20MHz and 40MHz
 +	 */
-+	rt2x00dev->calibration_bw20 =
++	rt2x00dev->calibration[0] =
 +	    rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
-+	rt2x00dev->calibration_bw40 =
++	rt2x00dev->calibration[1] =
 +	    rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
 +
 +	/*
@@ -2215,7 +2192,8 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +	rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 +			   test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 +			       txdesc->key_idx : 0xff);
-+	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
++	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
++			   skb->len - txdesc->l2pad);
 +	rt2x00_set_field32(&word, TXWI_W1_PACKETID,
 +			   skbdesc->entry->queue->qid);
 +	rt2x00_desc_write(txwi, 1, word);
@@ -2403,6 +2381,9 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +	if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
 +		rxdesc->dev_flags |= RXDONE_MY_BSS;
 +
++	if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
++		rxdesc->dev_flags |= RXDONE_L2PAD;
++
 +	if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
 +		rxdesc->flags |= RX_FLAG_SHORT_GI;
 +
@@ -2712,6 +2693,14 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +	}
 +
 +	/*
++	 * Identify default antenna configuration.
++	 */
++	rt2x00dev->default_ant.tx =
++	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
++	rt2x00dev->default_ant.rx =
++	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
++
++	/*
 +	 * Read frequency offset and RF programming sequence.
 +	 */
 +	rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
@@ -2954,6 +2943,7 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +	if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
 +	    !rt2x00_rt(&rt2x00dev->chip, RT3052))
 +		__set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
++	__set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
 +	if (!modparam_nohwcrypt)
 +		__set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
 +
@@ -3192,13 +3182,25 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 + * RT2800pci module information.
 + */
 +static struct pci_device_id rt2800pci_device_table[] = {
++	/* Edimax */
++	{ PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
 +	{ PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
 +	{ PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
 +	{ PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
 +	{ PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
 +	{ PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
 +	{ PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
 +	{ PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	{ PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
++	/* Awt */
 +	{ PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
 +	{ 0, }
 +};
@@ -5210,7 +5212,7 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +#endif /* RT2800PCI_H */
 --- a/drivers/net/wireless/rt2x00/rt2x00.h
 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
-@@ -138,6 +138,12 @@ struct rt2x00_chip {
+@@ -147,6 +147,12 @@ struct rt2x00_chip {
  #define RT2561		0x0302
  #define RT2661		0x0401
  #define RT2571		0x1300
@@ -5220,6 +5222,6 @@ Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
 +#define RT2890D		0x0781	/* 2.4GHz, 5GHz PCIe */
 +#define RT2880		0x2880	/* WSOC */
 +#define RT3052		0x3052	/* WSOC */
+ #define RT2870		0x1600
  
  	u16 rf;
- 	u32 rev;
diff --git a/package/mac80211/patches/303-rt2x00-Add-rt73usb-USB-IDs.patch b/package/mac80211/patches/303-rt2x00-Add-rt73usb-USB-IDs.patch
deleted file mode 100644
index 7b66c6c25..000000000
--- a/package/mac80211/patches/303-rt2x00-Add-rt73usb-USB-IDs.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From b587a44d6cf038cac3ce194c49196f501fa4bb48 Mon Sep 17 00:00:00 2001
-From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:32:50 +0100
-Subject: [PATCH 4/9] rt2x00: Add rt73usb USB IDs
-
-Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
----
- drivers/net/wireless/rt2x00/rt73usb.c |    2 ++
- 1 files changed, 2 insertions(+), 0 deletions(-)
-
---- a/drivers/net/wireless/rt2x00/rt73usb.c
-+++ b/drivers/net/wireless/rt2x00/rt73usb.c
-@@ -2369,6 +2369,8 @@ static struct usb_device_id rt73usb_devi
- 	/* Buffalo */
- 	{ USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
- 	{ USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
-+	{ USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
-+	{ USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
- 	/* CNet */
- 	{ USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
- 	{ USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
diff --git a/package/mac80211/patches/303-rt2x00-Allocate-DMA-rt2800pci.patch b/package/mac80211/patches/303-rt2x00-Allocate-DMA-rt2800pci.patch
new file mode 100644
index 000000000..7c623a542
--- /dev/null
+++ b/package/mac80211/patches/303-rt2x00-Allocate-DMA-rt2800pci.patch
@@ -0,0 +1,21 @@
+From ff3453072abf45ccf05e83f69c69951f3d7f7160 Mon Sep 17 00:00:00 2001
+From: Ivo van Doorn <IvDoorn@gmail.com>
+Date: Sun, 26 Apr 2009 17:35:38 +0200
+Subject: [PATCH 3/4] rt2x00: Allocate DMA (rt2800pci)
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
+---
+ drivers/net/wireless/rt2x00/rt2800pci.c |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/rt2x00/rt2800pci.c
++++ b/drivers/net/wireless/rt2x00/rt2800pci.c
+@@ -2906,6 +2906,7 @@ static int rt2800pci_probe_hw(struct rt2
+ 	if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
+ 	    !rt2x00_rt(&rt2x00dev->chip, RT3052))
+ 		__set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
++	__set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
+ 	__set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
+ 	if (!modparam_nohwcrypt)
+ 		__set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
diff --git a/package/mac80211/patches/304-rt2x00-Implement-support-for-802.11n.patch b/package/mac80211/patches/304-rt2x00-Implement-support-for-802.11n.patch
deleted file mode 100644
index b1b75751b..000000000
--- a/package/mac80211/patches/304-rt2x00-Implement-support-for-802.11n.patch
+++ /dev/null
@@ -1,522 +0,0 @@
-From 0f4396e5a4351ccd48256407b4a606d6c33a94cb Mon Sep 17 00:00:00 2001
-From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:37:26 +0100
-Subject: [PATCH 5/9] rt2x00: Implement support for 802.11n
-
-Extend rt2x00lib capabilities to support 802.11n,
-it still lacks aggregation support, but that can
-be added in the future.
-
-Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
----
- drivers/net/wireless/rt2x00/Kconfig        |    3 +
- drivers/net/wireless/rt2x00/Makefile       |    1 +
- drivers/net/wireless/rt2x00/rt2x00.h       |    4 +
- drivers/net/wireless/rt2x00/rt2x00config.c |    5 ++
- drivers/net/wireless/rt2x00/rt2x00dev.c    |   91 ++++++++++++++++++++-------
- drivers/net/wireless/rt2x00/rt2x00ht.c     |   69 +++++++++++++++++++++
- drivers/net/wireless/rt2x00/rt2x00lib.h    |   24 +++++++
- drivers/net/wireless/rt2x00/rt2x00queue.c  |    1 +
- drivers/net/wireless/rt2x00/rt2x00queue.h  |   33 ++++++++--
- 9 files changed, 201 insertions(+), 30 deletions(-)
- create mode 100644 drivers/net/wireless/rt2x00/rt2x00ht.c
-
---- a/drivers/net/wireless/rt2x00/Makefile
-+++ b/drivers/net/wireless/rt2x00/Makefile
-@@ -8,6 +8,7 @@ rt2x00lib-$(CONFIG_RT2X00_LIB_CRYPTO)	+=
- rt2x00lib-$(CONFIG_RT2X00_LIB_RFKILL)	+= rt2x00rfkill.o
- rt2x00lib-$(CONFIG_RT2X00_LIB_FIRMWARE)	+= rt2x00firmware.o
- rt2x00lib-$(CONFIG_RT2X00_LIB_LEDS)	+= rt2x00leds.o
-+rt2x00lib-$(CONFIG_RT2X00_LIB_HT)	+= rt2x00ht.o
- 
- obj-$(CONFIG_RT2X00_LIB)		+= rt2x00lib.o
- obj-$(CONFIG_RT2X00_LIB_PCI)		+= rt2x00pci.o
---- a/drivers/net/wireless/rt2x00/rt2x00.h
-+++ b/drivers/net/wireless/rt2x00/rt2x00.h
-@@ -357,6 +357,7 @@ static inline struct rt2x00_intf* vif_to
-  *	for @tx_power_a, @tx_power_bg and @channels.
-  * @channels: Device/chipset specific channel values (See &struct rf_channel).
-  * @channels_info: Additional information for channels (See &struct channel_info).
-+ * @ht: Driver HT Capabilities (See &ieee80211_sta_ht_cap).
-  */
- struct hw_mode_spec {
- 	unsigned int supported_bands;
-@@ -370,6 +371,8 @@ struct hw_mode_spec {
- 	unsigned int num_channels;
- 	const struct rf_channel *channels;
- 	const struct channel_info *channels_info;
-+
-+	struct ieee80211_sta_ht_cap ht;
- };
- 
- /*
-@@ -606,6 +609,7 @@ enum rt2x00_flags {
- 	CONFIG_EXTERNAL_LNA_BG,
- 	CONFIG_DOUBLE_ANTENNA,
- 	CONFIG_DISABLE_LINK_TUNING,
-+	CONFIG_CHANNEL_HT40,
- };
- 
- /*
---- a/drivers/net/wireless/rt2x00/rt2x00config.c
-+++ b/drivers/net/wireless/rt2x00/rt2x00config.c
-@@ -173,6 +173,11 @@ void rt2x00lib_config(struct rt2x00_dev 
- 	libconf.conf = conf;
- 
- 	if (ieee80211_flags & IEEE80211_CONF_CHANGE_CHANNEL) {
-+		if (conf_is_ht40(conf))
-+			__set_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags);
-+		else
-+			__clear_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags);
-+
- 		memcpy(&libconf.rf,
- 		       &rt2x00dev->spec.channels[conf->channel->hw_value],
- 		       sizeof(libconf.rf));
---- a/drivers/net/wireless/rt2x00/rt2x00dev.c
-+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
-@@ -316,18 +316,54 @@ void rt2x00lib_txdone(struct queue_entry
- }
- EXPORT_SYMBOL_GPL(rt2x00lib_txdone);
- 
-+static int rt2x00lib_rxdone_read_signal(struct rt2x00_dev *rt2x00dev,
-+					struct rxdone_entry_desc *rxdesc)
-+{
-+	struct ieee80211_supported_band *sband;
-+	const struct rt2x00_rate *rate;
-+	unsigned int i;
-+	int signal;
-+	int type;
-+
-+	/*
-+	 * For non-HT rates the MCS value needs to contain the
-+	 * actually used rate modulation (CCK or OFDM).
-+	 */
-+	if (rxdesc->dev_flags & RXDONE_SIGNAL_MCS)
-+		signal = RATE_MCS(rxdesc->rate_mode, rxdesc->signal);
-+	else
-+		signal = rxdesc->signal;
-+
-+	type = (rxdesc->dev_flags & RXDONE_SIGNAL_MASK);
-+
-+	sband = &rt2x00dev->bands[rt2x00dev->curr_band];
-+	for (i = 0; i < sband->n_bitrates; i++) {
-+		rate = rt2x00_get_rate(sband->bitrates[i].hw_value);
-+
-+		if (((type == RXDONE_SIGNAL_PLCP) &&
-+		     (rate->plcp == signal)) ||
-+		    ((type == RXDONE_SIGNAL_BITRATE) &&
-+		      (rate->bitrate == signal)) ||
-+		    ((type == RXDONE_SIGNAL_MCS) &&
-+		      (rate->mcs == signal))) {
-+			return i;
-+		}
-+	}
-+
-+	WARNING(rt2x00dev, "Frame received with unrecognized signal, "
-+		"signal=0x%.4x, type=%d.\n", signal, type);
-+	return 0;
-+}
-+
- void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
- 		      struct queue_entry *entry)
- {
- 	struct rxdone_entry_desc rxdesc;
- 	struct sk_buff *skb;
- 	struct ieee80211_rx_status *rx_status = &rt2x00dev->rx_status;
--	struct ieee80211_supported_band *sband;
--	const struct rt2x00_rate *rate;
- 	unsigned int header_length;
- 	unsigned int align;
--	unsigned int i;
--	int idx = -1;
-+	int rate_idx;
- 
- 	/*
- 	 * Allocate a new sk_buffer. If no new buffer available, drop the
-@@ -376,26 +412,17 @@ void rt2x00lib_rxdone(struct rt2x00_dev 
- 	skb_trim(entry->skb, rxdesc.size);
- 
- 	/*
--	 * Update RX statistics.
--	 */
--	sband = &rt2x00dev->bands[rt2x00dev->curr_band];
--	for (i = 0; i < sband->n_bitrates; i++) {
--		rate = rt2x00_get_rate(sband->bitrates[i].hw_value);
--
--		if (((rxdesc.dev_flags & RXDONE_SIGNAL_PLCP) &&
--		     (rate->plcp == rxdesc.signal)) ||
--		    ((rxdesc.dev_flags & RXDONE_SIGNAL_BITRATE) &&
--		      (rate->bitrate == rxdesc.signal))) {
--			idx = i;
--			break;
--		}
--	}
--
--	if (idx < 0) {
--		WARNING(rt2x00dev, "Frame received with unrecognized signal,"
--			"signal=0x%.2x, type=%d.\n", rxdesc.signal,
--			(rxdesc.dev_flags & RXDONE_SIGNAL_MASK));
--		idx = 0;
-+	 * Check if the frame was received using HT. In that case,
-+	 * the rate is the MCS index and should be passed to mac80211
-+	 * directly. Otherwise we need to translate the signal to
-+	 * the correct bitrate index.
-+	 */
-+	if (rxdesc.rate_mode == RATE_MODE_CCK ||
-+	    rxdesc.rate_mode == RATE_MODE_OFDM) {
-+		rate_idx = rt2x00lib_rxdone_read_signal(rt2x00dev, &rxdesc);
-+	} else {
-+		rxdesc.flags |= RX_FLAG_HT;
-+		rate_idx = rxdesc.signal;
- 	}
- 
- 	/*
-@@ -405,7 +432,7 @@ void rt2x00lib_rxdone(struct rt2x00_dev 
- 	rt2x00debug_update_crypto(rt2x00dev, &rxdesc);
- 
- 	rx_status->mactime = rxdesc.timestamp;
--	rx_status->rate_idx = idx;
-+	rx_status->rate_idx = rate_idx;
- 	rx_status->qual = rt2x00link_calculate_signal(rt2x00dev, rxdesc.rssi);
- 	rx_status->signal = rxdesc.rssi;
- 	rx_status->noise = rxdesc.noise;
-@@ -440,72 +467,84 @@ const struct rt2x00_rate rt2x00_supporte
- 		.bitrate = 10,
- 		.ratemask = BIT(0),
- 		.plcp = 0x00,
-+		.mcs = RATE_MCS(RATE_MODE_CCK, 0),
- 	},
- 	{
- 		.flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
- 		.bitrate = 20,
- 		.ratemask = BIT(1),
- 		.plcp = 0x01,
-+		.mcs = RATE_MCS(RATE_MODE_CCK, 1),
- 	},
- 	{
- 		.flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
- 		.bitrate = 55,
- 		.ratemask = BIT(2),
- 		.plcp = 0x02,
-+		.mcs = RATE_MCS(RATE_MODE_CCK, 2),
- 	},
- 	{
- 		.flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
- 		.bitrate = 110,
- 		.ratemask = BIT(3),
- 		.plcp = 0x03,
-+		.mcs = RATE_MCS(RATE_MODE_CCK, 3),
- 	},
- 	{
- 		.flags = DEV_RATE_OFDM,
- 		.bitrate = 60,
- 		.ratemask = BIT(4),
- 		.plcp = 0x0b,
-+		.mcs = RATE_MCS(RATE_MODE_OFDM, 0),
- 	},
- 	{
- 		.flags = DEV_RATE_OFDM,
- 		.bitrate = 90,
- 		.ratemask = BIT(5),
- 		.plcp = 0x0f,
-+		.mcs = RATE_MCS(RATE_MODE_OFDM, 1),
- 	},
- 	{
- 		.flags = DEV_RATE_OFDM,
- 		.bitrate = 120,
- 		.ratemask = BIT(6),
- 		.plcp = 0x0a,
-+		.mcs = RATE_MCS(RATE_MODE_OFDM, 2),
- 	},
- 	{
- 		.flags = DEV_RATE_OFDM,
- 		.bitrate = 180,
- 		.ratemask = BIT(7),
- 		.plcp = 0x0e,
-+		.mcs = RATE_MCS(RATE_MODE_OFDM, 3),
- 	},
- 	{
- 		.flags = DEV_RATE_OFDM,
- 		.bitrate = 240,
- 		.ratemask = BIT(8),
- 		.plcp = 0x09,
-+		.mcs = RATE_MCS(RATE_MODE_OFDM, 4),
- 	},
- 	{
- 		.flags = DEV_RATE_OFDM,
- 		.bitrate = 360,
- 		.ratemask = BIT(9),
- 		.plcp = 0x0d,
-+		.mcs = RATE_MCS(RATE_MODE_OFDM, 5),
- 	},
- 	{
- 		.flags = DEV_RATE_OFDM,
- 		.bitrate = 480,
- 		.ratemask = BIT(10),
- 		.plcp = 0x08,
-+		.mcs = RATE_MCS(RATE_MODE_OFDM, 6),
- 	},
- 	{
- 		.flags = DEV_RATE_OFDM,
- 		.bitrate = 540,
- 		.ratemask = BIT(11),
- 		.plcp = 0x0c,
-+		.mcs = RATE_MCS(RATE_MODE_OFDM, 7),
- 	},
- };
- 
-@@ -581,6 +620,8 @@ static int rt2x00lib_probe_hw_modes(stru
- 		rt2x00dev->bands[IEEE80211_BAND_2GHZ].bitrates = rates;
- 		hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
- 		    &rt2x00dev->bands[IEEE80211_BAND_2GHZ];
-+		memcpy(&rt2x00dev->bands[IEEE80211_BAND_2GHZ].ht_cap,
-+		       &spec->ht, sizeof(spec->ht));
- 	}
- 
- 	/*
-@@ -597,6 +638,8 @@ static int rt2x00lib_probe_hw_modes(stru
- 		rt2x00dev->bands[IEEE80211_BAND_5GHZ].bitrates = &rates[4];
- 		hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
- 		    &rt2x00dev->bands[IEEE80211_BAND_5GHZ];
-+		memcpy(&rt2x00dev->bands[IEEE80211_BAND_5GHZ].ht_cap,
-+		       &spec->ht, sizeof(spec->ht));
- 	}
- 
- 	return 0;
---- /dev/null
-+++ b/drivers/net/wireless/rt2x00/rt2x00ht.c
-@@ -0,0 +1,69 @@
-+/*
-+	Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
-+	<http://rt2x00.serialmonkey.com>
-+
-+	This program is free software; you can redistribute it and/or modify
-+	it under the terms of the GNU General Public License as published by
-+	the Free Software Foundation; either version 2 of the License, or
-+	(at your option) any later version.
-+
-+	This program is distributed in the hope that it will be useful,
-+	but WITHOUT ANY WARRANTY; without even the implied warranty of
-+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+	GNU General Public License for more details.
-+
-+	You should have received a copy of the GNU General Public License
-+	along with this program; if not, write to the
-+	Free Software Foundation, Inc.,
-+	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+/*
-+	Module: rt2x00lib
-+	Abstract: rt2x00 HT specific routines.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+
-+#include "rt2x00.h"
-+#include "rt2x00lib.h"
-+
-+void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
-+				   struct txentry_desc *txdesc,
-+				   const struct rt2x00_rate *hwrate)
-+{
-+	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
-+	struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
-+
-+	if (tx_info->control.sta)
-+		txdesc->mpdu_density =
-+		    tx_info->control.sta->ht_cap.ampdu_density;
-+	else
-+		txdesc->mpdu_density = 0;
-+
-+	txdesc->ba_size = 7;	/* FIXME: What value is needed? */
-+	txdesc->stbc = 0;	/* FIXME: What value is needed? */
-+
-+	txdesc->mcs = rt2x00_get_rate_mcs(hwrate->mcs);
-+	if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
-+		txdesc->mcs |= 0x08;
-+
-+	/*
-+	 * Convert flags
-+	 */
-+	if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
-+		__set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
-+
-+	/*
-+	 * Determine HT Mix/Greenfield rate mode
-+	 */
-+	if (txrate->flags & IEEE80211_TX_RC_MCS)
-+		txdesc->rate_mode = RATE_MODE_HT_MIX;
-+	if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
-+		txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
-+	if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
-+		__set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
-+	if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
-+		__set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
-+}
---- a/drivers/net/wireless/rt2x00/rt2x00lib.h
-+++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
-@@ -48,6 +48,7 @@ struct rt2x00_rate {
- 	unsigned short ratemask;
- 
- 	unsigned short plcp;
-+	unsigned short mcs;
- };
- 
- extern const struct rt2x00_rate rt2x00_supported_rates[12];
-@@ -57,6 +58,14 @@ static inline const struct rt2x00_rate *
- 	return &rt2x00_supported_rates[hw_value & 0xff];
- }
- 
-+#define RATE_MCS(__mode, __mcs) \
-+	( (((__mode) & 0x00ff) << 8) | ((__mcs) & 0x00ff) )
-+
-+static inline int rt2x00_get_rate_mcs(const u16 mcs_value)
-+{
-+	return (mcs_value & 0x00ff);
-+}
-+
- /*
-  * Radio control handlers.
-  */
-@@ -341,6 +350,21 @@ static inline void rt2x00crypto_rx_inser
- #endif /* CONFIG_RT2X00_LIB_CRYPTO */
- 
- /*
-+ * HT handlers.
-+ */
-+#ifdef CONFIG_RT2X00_LIB_HT
-+void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
-+				   struct txentry_desc *txdesc,
-+				   const struct rt2x00_rate *hwrate);
-+#else
-+static inline void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
-+						 struct txentry_desc *txdesc,
-+						 const struct rt2x00_rate *hwrate)
-+{
-+}
-+#endif /* CONFIG_RT2X00_LIB_HT */
-+
-+/*
-  * RFkill handlers.
-  */
- #ifdef CONFIG_RT2X00_LIB_RFKILL
---- a/drivers/net/wireless/rt2x00/rt2x00queue.c
-+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
-@@ -326,6 +326,7 @@ static void rt2x00queue_create_tx_descri
- 	 * Apply TX descriptor handling by components
- 	 */
- 	rt2x00crypto_create_tx_descriptor(entry, txdesc);
-+	rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
- 	rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
- 	rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
- }
---- a/drivers/net/wireless/rt2x00/rt2x00queue.h
-+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
-@@ -35,9 +35,12 @@
-  * for USB devices this restriction does not apply, but the value of
-  * 2432 makes sense since it is big enough to contain the maximum fragment
-  * size according to the ieee802.11 specs.
-+ * The aggregation size depends on support from the driver, but should
-+ * be something around 3840 bytes.
-  */
--#define DATA_FRAME_SIZE	2432
--#define MGMT_FRAME_SIZE	256
-+#define DATA_FRAME_SIZE		2432
-+#define MGMT_FRAME_SIZE		256
-+#define AGGREGATION_SIZE	3840
- 
- /**
-  * DOC: Number of entries per queue
-@@ -145,6 +148,7 @@ static inline struct skb_frame_desc* get
-  *
-  * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value.
-  * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value.
-+ * @RXDONE_SIGNAL_MCS: Signal field contains the mcs value.
-  * @RXDONE_MY_BSS: Does this frame originate from device's BSS.
-  * @RXDONE_CRYPTO_IV: Driver provided IV/EIV data.
-  * @RXDONE_CRYPTO_ICV: Driver provided ICV data.
-@@ -152,9 +156,10 @@ static inline struct skb_frame_desc* get
- enum rxdone_entry_desc_flags {
- 	RXDONE_SIGNAL_PLCP = 1 << 0,
- 	RXDONE_SIGNAL_BITRATE = 1 << 1,
--	RXDONE_MY_BSS = 1 << 2,
--	RXDONE_CRYPTO_IV = 1 << 3,
--	RXDONE_CRYPTO_ICV = 1 << 4,
-+	RXDONE_SIGNAL_MCS = 1 << 2,
-+	RXDONE_MY_BSS = 1 << 3,
-+	RXDONE_CRYPTO_IV = 1 << 4,
-+	RXDONE_CRYPTO_ICV = 1 << 5,
- };
- 
- /**
-@@ -163,7 +168,7 @@ enum rxdone_entry_desc_flags {
-  * from &rxdone_entry_desc to a signal value type.
-  */
- #define RXDONE_SIGNAL_MASK \
--       ( RXDONE_SIGNAL_PLCP | RXDONE_SIGNAL_BITRATE )
-+	( RXDONE_SIGNAL_PLCP | RXDONE_SIGNAL_BITRATE | RXDONE_SIGNAL_MCS )
- 
- /**
-  * struct rxdone_entry_desc: RX Entry descriptor
-@@ -177,6 +182,7 @@ enum rxdone_entry_desc_flags {
-  * @size: Data size of the received frame.
-  * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags).
-  * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags).
-+ * @rate_mode: Rate mode (See @enum rate_modulation).
-  * @cipher: Cipher type used during decryption.
-  * @cipher_status: Decryption status.
-  * @iv: IV/EIV data used during decryption.
-@@ -190,6 +196,7 @@ struct rxdone_entry_desc {
- 	int size;
- 	int flags;
- 	int dev_flags;
-+	u16 rate_mode;
- 	u8 cipher;
- 	u8 cipher_status;
- 
-@@ -243,6 +250,9 @@ struct txdone_entry_desc {
-  * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared).
-  * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware.
-  * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware.
-+ * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU.
-+ * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth.
-+ * @ENTRY_TXD_HT_SHORT_GI: Use short GI.
-  */
- enum txentry_desc_flags {
- 	ENTRY_TXD_RTS_FRAME,
-@@ -258,6 +268,9 @@ enum txentry_desc_flags {
- 	ENTRY_TXD_ENCRYPT_PAIRWISE,
- 	ENTRY_TXD_ENCRYPT_IV,
- 	ENTRY_TXD_ENCRYPT_MMIC,
-+	ENTRY_TXD_HT_AMPDU,
-+	ENTRY_TXD_HT_BW_40,
-+	ENTRY_TXD_HT_SHORT_GI,
- };
- 
- /**
-@@ -271,7 +284,11 @@ enum txentry_desc_flags {
-  * @length_low: PLCP length low word.
-  * @signal: PLCP signal.
-  * @service: PLCP service.
-+ * @msc: MCS.
-+ * @stbc: STBC.
-+ * @ba_size: BA size.
-  * @rate_mode: Rate mode (See @enum rate_modulation).
-+ * @mpdu_density: MDPU density.
-  * @retry_limit: Max number of retries.
-  * @aifs: AIFS value.
-  * @ifs: IFS value.
-@@ -291,7 +308,11 @@ struct txentry_desc {
- 	u16 signal;
- 	u16 service;
- 
-+	u16 mcs;
-+	u16 stbc;
-+	u16 ba_size;
- 	u16 rate_mode;
-+	u16 mpdu_density;
- 
- 	short retry_limit;
- 	short aifs;
diff --git a/package/mac80211/patches/304-rt2x00-Update-from-rt2860-driver-rt2800pci.patch b/package/mac80211/patches/304-rt2x00-Update-from-rt2860-driver-rt2800pci.patch
new file mode 100644
index 000000000..e28bac054
--- /dev/null
+++ b/package/mac80211/patches/304-rt2x00-Update-from-rt2860-driver-rt2800pci.patch
@@ -0,0 +1,52 @@
+From 690559385626e98e2a91c280a8bca195f071756c Mon Sep 17 00:00:00 2001
+From: Ivo van Doorn <IvDoorn@gmail.com>
+Date: Tue, 28 Apr 2009 20:12:43 +0200
+Subject: [PATCH 4/4] rt2x00: Update from rt2860 driver (rt2800pci)
+
+Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
+---
+ drivers/net/wireless/rt2x00/rt2800pci.c |   10 +++++++---
+ drivers/net/wireless/rt2x00/rt2800pci.h |    2 ++
+ 2 files changed, 9 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/wireless/rt2x00/rt2800pci.c
++++ b/drivers/net/wireless/rt2x00/rt2800pci.c
+@@ -2048,13 +2048,17 @@ static void rt2800pci_disable_radio(stru
+ static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
+ 			       enum dev_state state)
+ {
+-	rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
++	/*
++	 * Always put the device to sleep (even when we intend to wakup!)
++	 * if the device is booting and wasn't asleep it will return
++	 * failure when attempting to wakup.
++	 */
++	rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
+ 
+ 	if (state == STATE_AWAKE) {
+ 		rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
+ 		rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
+-	} else
+-		rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
++	}
+ 
+ 	return 0;
+ }
+--- a/drivers/net/wireless/rt2x00/rt2800pci.h
++++ b/drivers/net/wireless/rt2x00/rt2800pci.h
+@@ -1714,6 +1714,7 @@ struct mac_iveiv_entry {
+ #define MCU_SLEEP			0x30
+ #define MCU_WAKEUP			0x31
+ #define MCU_RADIO_OFF			0x35
++#define MCU_CURRENT			0x36
+ #define MCU_LED				0x50
+ #define MCU_LED_STRENGTH		0x51
+ #define MCU_LED_1			0x52
+@@ -1722,6 +1723,7 @@ struct mac_iveiv_entry {
+ #define MCU_RADAR			0x60
+ #define MCU_BOOT_SIGNAL			0x72
+ #define MCU_BBP_SIGNAL			0x80
++#define MCU_POWER_SAVE			0x83
+ 
+ /*
+  * MCU mailbox tokens
diff --git a/package/mac80211/patches/305-rt2x00-unify-config_interface.patch b/package/mac80211/patches/305-rt2x00-unify-config_interface.patch
new file mode 100644
index 000000000..f2d6e83d5
--- /dev/null
+++ b/package/mac80211/patches/305-rt2x00-unify-config_interface.patch
@@ -0,0 +1,10 @@
+--- a/drivers/net/wireless/rt2x00/rt2800pci.c
++++ b/drivers/net/wireless/rt2x00/rt2800pci.c
+@@ -3066,7 +3066,6 @@ static const struct ieee80211_ops rt2800
+ 	.add_interface		= rt2x00mac_add_interface,
+ 	.remove_interface	= rt2x00mac_remove_interface,
+ 	.config			= rt2x00mac_config,
+-	.config_interface	= rt2x00mac_config_interface,
+ 	.configure_filter	= rt2x00mac_configure_filter,
+ 	.set_key		= rt2x00mac_set_key,
+ 	.get_stats		= rt2x00mac_get_stats,
diff --git a/package/mac80211/patches/306-rt2x00-Add-calibration-fields-to-rt2x00dev-rt2x00h.patch b/package/mac80211/patches/306-rt2x00-Add-calibration-fields-to-rt2x00dev-rt2x00h.patch
deleted file mode 100644
index 533c96c9c..000000000
--- a/package/mac80211/patches/306-rt2x00-Add-calibration-fields-to-rt2x00dev-rt2x00h.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 7f759a5e56f64fed24e5eb487003ce455786bc31 Mon Sep 17 00:00:00 2001
-From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:44:18 +0100
-Subject: [PATCH 7/9] rt2x00: Add calibration fields to rt2x00dev (rt2x00ht)
-
-Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
----
- drivers/net/wireless/rt2x00/rt2x00.h |    6 ++++++
- 1 files changed, 6 insertions(+), 0 deletions(-)
-
---- a/drivers/net/wireless/rt2x00/rt2x00.h
-+++ b/drivers/net/wireless/rt2x00/rt2x00.h
-@@ -782,6 +782,12 @@ struct rt2x00_dev {
- 	u8 freq_offset;
- 
- 	/*
-+	 * Calibration information (for rt2800usb).
-+	 */
-+	u8 calibration_bw20;
-+	u8 calibration_bw40;
-+
-+	/*
- 	 * Low level statistics which will have
- 	 * to be kept up to date while device is running.
- 	 */
diff --git a/package/mac80211/patches/308-rt2x00-Implement-support-for-rt2800usb.patch b/package/mac80211/patches/308-rt2x00-Implement-support-for-rt2800usb.patch
deleted file mode 100644
index 946dfa1e0..000000000
--- a/package/mac80211/patches/308-rt2x00-Implement-support-for-rt2800usb.patch
+++ /dev/null
@@ -1,5017 +0,0 @@
-From 3924d0442771e17c26ab10ad53a1807e800ab3f1 Mon Sep 17 00:00:00 2001
-From: Ivo van Doorn <IvDoorn@gmail.com>
-Date: Sat, 28 Mar 2009 20:48:56 +0100
-Subject: [PATCH 9/9] rt2x00: Implement support for rt2800usb
-
-Add support for the rt2800usb chipset.
-
-Includes various patches from Mattias, Felix, Xose and Axel.
-
-Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
-Signed-off-by: Felix Fietkau <nbd@openwrt.org>
-Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
-Signed-off-by: Axel Kollhofer <rain_maker@root-forum.org>
-Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
----
- drivers/net/wireless/rt2x00/Kconfig     |   14 +
- drivers/net/wireless/rt2x00/Makefile    |    1 +
- drivers/net/wireless/rt2x00/rt2800usb.c | 3036 +++++++++++++++++++++++++++++++
- drivers/net/wireless/rt2x00/rt2800usb.h | 1934 ++++++++++++++++++++
- drivers/net/wireless/rt2x00/rt2x00.h    |    1 +
- 5 files changed, 4986 insertions(+), 0 deletions(-)
- create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.c
- create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.h
-
---- a/drivers/net/wireless/rt2x00/Makefile
-+++ b/drivers/net/wireless/rt2x00/Makefile
-@@ -20,3 +20,4 @@ obj-$(CONFIG_RT61PCI)			+= rt61pci.o
- obj-$(CONFIG_RT2800PCI)			+= rt2800pci.o
- obj-$(CONFIG_RT2500USB)			+= rt2500usb.o
- obj-$(CONFIG_RT73USB)			+= rt73usb.o
-+obj-$(CONFIG_RT2800USB)			+= rt2800usb.o
---- /dev/null
-+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
-@@ -0,0 +1,3036 @@
-+/*
-+	Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
-+	<http://rt2x00.serialmonkey.com>
-+
-+	This program is free software; you can redistribute it and/or modify
-+	it under the terms of the GNU General Public License as published by
-+	the Free Software Foundation; either version 2 of the License, or
-+	(at your option) any later version.
-+
-+	This program is distributed in the hope that it will be useful,
-+	but WITHOUT ANY WARRANTY; without even the implied warranty of
-+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+	GNU General Public License for more details.
-+
-+	You should have received a copy of the GNU General Public License
-+	along with this program; if not, write to the
-+	Free Software Foundation, Inc.,
-+	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+/*
-+	Module: rt2800usb
-+	Abstract: rt2800usb device specific routines.
-+	Supported chipsets: RT2800U.
-+ */
-+
-+#include <linux/crc-ccitt.h>
-+#include <linux/delay.h>
-+#include <linux/etherdevice.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/usb.h>
-+
-+#include "rt2x00.h"
-+#include "rt2x00usb.h"
-+#include "rt2800usb.h"
-+
-+/*
-+ * Allow hardware encryption to be disabled.
-+ */
-+static int modparam_nohwcrypt = 0;
-+module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
-+MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
-+
-+/*
-+ * Register access.
-+ * All access to the CSR registers will go through the methods
-+ * rt2x00usb_register_read and rt2x00usb_register_write.
-+ * BBP and RF register require indirect register access,
-+ * and use the CSR registers BBPCSR and RFCSR to achieve this.
-+ * These indirect registers work with busy bits,
-+ * and we will try maximal REGISTER_BUSY_COUNT times to access
-+ * the register while taking a REGISTER_BUSY_DELAY us delay
-+ * between each attampt. When the busy bit is still set at that time,
-+ * the access attempt is considered to have failed,
-+ * and we will print an error.
-+ * The _lock versions must be used if you already hold the csr_mutex
-+ */
-+#define WAIT_FOR_BBP(__dev, __reg) \
-+	rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
-+#define WAIT_FOR_RFCSR(__dev, __reg) \
-+	rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
-+#define WAIT_FOR_RF(__dev, __reg) \
-+	rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
-+#define WAIT_FOR_MCU(__dev, __reg) \
-+	rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
-+			       H2M_MAILBOX_CSR_OWNER, (__reg))
-+
-+static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
-+				const unsigned int word, const u8 value)
-+{
-+	u32 reg;
-+
-+	mutex_lock(&rt2x00dev->csr_mutex);
-+
-+	/*
-+	 * Wait until the BBP becomes available, afterwards we
-+	 * can safely write the new data into the register.
-+	 */
-+	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
-+		reg = 0;
-+		rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
-+		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
-+		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
-+		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
-+
-+		rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
-+	}
-+
-+	mutex_unlock(&rt2x00dev->csr_mutex);
-+}
-+
-+static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
-+			       const unsigned int word, u8 *value)
-+{
-+	u32 reg;
-+
-+	mutex_lock(&rt2x00dev->csr_mutex);
-+
-+	/*
-+	 * Wait until the BBP becomes available, afterwards we
-+	 * can safely write the read request into the register.
-+	 * After the data has been written, we wait until hardware
-+	 * returns the correct value, if at any time the register
-+	 * doesn't become available in time, reg will be 0xffffffff
-+	 * which means we return 0xff to the caller.
-+	 */
-+	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
-+		reg = 0;
-+		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
-+		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
-+		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
-+
-+		rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
-+
-+		WAIT_FOR_BBP(rt2x00dev, &reg);
-+	}
-+
-+	*value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
-+
-+	mutex_unlock(&rt2x00dev->csr_mutex);
-+}
-+
-+static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
-+				  const unsigned int word, const u8 value)
-+{
-+	u32 reg;
-+
-+	mutex_lock(&rt2x00dev->csr_mutex);
-+
-+	/*
-+	 * Wait until the RFCSR becomes available, afterwards we
-+	 * can safely write the new data into the register.
-+	 */
-+	if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
-+		reg = 0;
-+		rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
-+		rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
-+		rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
-+		rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
-+
-+		rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
-+	}
-+
-+	mutex_unlock(&rt2x00dev->csr_mutex);
-+}
-+
-+static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
-+				 const unsigned int word, u8 *value)
-+{
-+	u32 reg;
-+
-+	mutex_lock(&rt2x00dev->csr_mutex);
-+
-+	/*
-+	 * Wait until the RFCSR becomes available, afterwards we
-+	 * can safely write the read request into the register.
-+	 * After the data has been written, we wait until hardware
-+	 * returns the correct value, if at any time the register
-+	 * doesn't become available in time, reg will be 0xffffffff
-+	 * which means we return 0xff to the caller.
-+	 */
-+	if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
-+		reg = 0;
-+		rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
-+		rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
-+		rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
-+
-+		rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
-+
-+		WAIT_FOR_RFCSR(rt2x00dev, &reg);
-+	}
-+
-+	*value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
-+
-+	mutex_unlock(&rt2x00dev->csr_mutex);
-+}
-+
-+static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
-+			       const unsigned int word, const u32 value)
-+{
-+	u32 reg;
-+
-+	mutex_lock(&rt2x00dev->csr_mutex);
-+
-+	/*
-+	 * Wait until the RF becomes available, afterwards we
-+	 * can safely write the new data into the register.
-+	 */
-+	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
-+		reg = 0;
-+		rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
-+		rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
-+		rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
-+		rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
-+
-+		rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
-+		rt2x00_rf_write(rt2x00dev, word, value);
-+	}
-+
-+	mutex_unlock(&rt2x00dev->csr_mutex);
-+}
-+
-+static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
-+				  const u8 command, const u8 token,
-+				  const u8 arg0, const u8 arg1)
-+{
-+	u32 reg;
-+
-+	mutex_lock(&rt2x00dev->csr_mutex);
-+
-+	/*
-+	 * Wait until the MCU becomes available, afterwards we
-+	 * can safely write the new data into the register.
-+	 */
-+	if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
-+		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
-+		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
-+		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
-+		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
-+		rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
-+
-+		reg = 0;
-+		rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
-+		rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
-+	}
-+
-+	mutex_unlock(&rt2x00dev->csr_mutex);
-+}
-+
-+#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-+static const struct rt2x00debug rt2800usb_rt2x00debug = {
-+	.owner	= THIS_MODULE,
-+	.csr	= {
-+		.read		= rt2x00usb_register_read,
-+		.write		= rt2x00usb_register_write,
-+		.flags		= RT2X00DEBUGFS_OFFSET,
-+		.word_base	= CSR_REG_BASE,
-+		.word_size	= sizeof(u32),
-+		.word_count	= CSR_REG_SIZE / sizeof(u32),
-+	},
-+	.eeprom	= {
-+		.read		= rt2x00_eeprom_read,
-+		.write		= rt2x00_eeprom_write,
-+		.word_base	= EEPROM_BASE,
-+		.word_size	= sizeof(u16),
-+		.word_count	= EEPROM_SIZE / sizeof(u16),
-+	},
-+	.bbp	= {
-+		.read		= rt2800usb_bbp_read,
-+		.write		= rt2800usb_bbp_write,
-+		.word_base	= BBP_BASE,
-+		.word_size	= sizeof(u8),
-+		.word_count	= BBP_SIZE / sizeof(u8),
-+	},
-+	.rf	= {
-+		.read		= rt2x00_rf_read,
-+		.write		= rt2800usb_rf_write,
-+		.word_base	= RF_BASE,
-+		.word_size	= sizeof(u32),
-+		.word_count	= RF_SIZE / sizeof(u32),
-+	},
-+};
-+#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-+
-+#ifdef CONFIG_RT2X00_LIB_RFKILL
-+static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
-+{
-+	u32 reg;
-+
-+	rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-+	return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
-+}
-+#else
-+#define rt2800usb_rfkill_poll	NULL
-+#endif /* CONFIG_RT2X00_LIB_RFKILL */
-+
-+#ifdef CONFIG_RT2X00_LIB_LEDS
-+static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
-+				     enum led_brightness brightness)
-+{
-+	struct rt2x00_led *led =
-+	    container_of(led_cdev, struct rt2x00_led, led_dev);
-+	unsigned int enabled = brightness != LED_OFF;
-+	unsigned int bg_mode =
-+	    (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
-+	unsigned int polarity =
-+		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
-+				   EEPROM_FREQ_LED_POLARITY);
-+	unsigned int ledmode =
-+		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
-+				   EEPROM_FREQ_LED_MODE);
-+
-+	if (led->type == LED_TYPE_RADIO) {
-+		rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
-+				      enabled ? 0x20 : 0);
-+	} else if (led->type == LED_TYPE_ASSOC) {
-+		rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
-+				      enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
-+	} else if (led->type == LED_TYPE_QUALITY) {
-+		/*
-+		 * The brightness is divided into 6 levels (0 - 5),
-+		 * The specs tell us the following levels:
-+		 *	0, 1 ,3, 7, 15, 31
-+		 * to determine the level in a simple way we can simply
-+		 * work with bitshifting:
-+		 *	(1 << level) - 1
-+		 */
-+		rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
-+				      (1 << brightness / (LED_FULL / 6)) - 1,
-+				      polarity);
-+	}
-+}
-+
-+static int rt2800usb_blink_set(struct led_classdev *led_cdev,
-+			       unsigned long *delay_on,
-+			       unsigned long *delay_off)
-+{
-+	struct rt2x00_led *led =
-+	    container_of(led_cdev, struct rt2x00_led, led_dev);
-+	u32 reg;
-+
-+	rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
-+	rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
-+	rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
-+	rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
-+	rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
-+	rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
-+	rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
-+	rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
-+	rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
-+
-+	return 0;
-+}
-+
-+static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
-+			       struct rt2x00_led *led,
-+			       enum led_type type)
-+{
-+	led->rt2x00dev = rt2x00dev;
-+	led->type = type;
-+	led->led_dev.brightness_set = rt2800usb_brightness_set;
-+	led->led_dev.blink_set = rt2800usb_blink_set;
-+	led->flags = LED_INITIALIZED;
-+}
-+#endif /* CONFIG_RT2X00_LIB_LEDS */
-+
-+/*
-+ * Configuration handlers.
-+ */
-+static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
-+				       struct rt2x00lib_crypto *crypto,
-+				       struct ieee80211_key_conf *key)
-+{
-+	struct mac_wcid_entry wcid_entry;
-+	struct mac_iveiv_entry iveiv_entry;
-+	u32 offset;
-+	u32 reg;
-+
-+	offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
-+
-+	rt2x00usb_register_read(rt2x00dev, offset, &reg);
-+	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
-+			   !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
-+	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
-+			   (crypto->cmd == SET_KEY) * crypto->cipher);
-+	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
-+			   (crypto->cmd == SET_KEY) * crypto->bssidx);
-+	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
-+	rt2x00usb_register_write(rt2x00dev, offset, reg);
-+
-+	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
-+
-+	memset(&iveiv_entry, 0, sizeof(iveiv_entry));
-+	if ((crypto->cipher == CIPHER_TKIP) ||
-+	    (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
-+	    (crypto->cipher == CIPHER_AES))
-+		iveiv_entry.iv[3] |= 0x20;
-+	iveiv_entry.iv[3] |= key->keyidx << 6;
-+	rt2x00usb_register_multiwrite(rt2x00dev, offset,
-+				      &iveiv_entry, sizeof(iveiv_entry));
-+
-+	offset = MAC_WCID_ENTRY(key->hw_key_idx);
-+
-+	memset(&wcid_entry, 0, sizeof(wcid_entry));
-+	if (crypto->cmd == SET_KEY)
-+		memcpy(&wcid_entry, crypto->address, ETH_ALEN);
-+	rt2x00usb_register_multiwrite(rt2x00dev, offset,
-+				      &wcid_entry, sizeof(wcid_entry));
-+}
-+
-+static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
-+				       struct rt2x00lib_crypto *crypto,
-+				       struct ieee80211_key_conf *key)
-+{
-+	struct hw_key_entry key_entry;
-+	struct rt2x00_field32 field;
-+	int timeout;
-+	u32 offset;
-+	u32 reg;
-+
-+	if (crypto->cmd == SET_KEY) {
-+		key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
-+
-+		memcpy(key_entry.key, crypto->key,
-+		       sizeof(key_entry.key));
-+		memcpy(key_entry.tx_mic, crypto->tx_mic,
-+		       sizeof(key_entry.tx_mic));
-+		memcpy(key_entry.rx_mic, crypto->rx_mic,
-+		       sizeof(key_entry.rx_mic));
-+
-+		offset = SHARED_KEY_ENTRY(key->hw_key_idx);
-+		timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
-+		rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
-+						    USB_VENDOR_REQUEST_OUT,
-+						    offset, &key_entry,
-+						    sizeof(key_entry),
-+						    timeout);
-+	}
-+
-+	/*
-+	 * The cipher types are stored over multiple registers
-+	 * starting with SHARED_KEY_MODE_BASE each word will have
-+	 * 32 bits and contains the cipher types for 2 bssidx each.
-+	 * Using the correct defines correctly will cause overhead,
-+	 * so just calculate the correct offset.
-+	 */
-+	field.bit_offset = 4 * (key->hw_key_idx % 8);
-+	field.bit_mask = 0x7 << field.bit_offset;
-+
-+	offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
-+
-+	rt2x00usb_register_read(rt2x00dev, offset, &reg);
-+	rt2x00_set_field32(&reg, field,
-+			   (crypto->cmd == SET_KEY) * crypto->cipher);
-+	rt2x00usb_register_write(rt2x00dev, offset, reg);
-+
-+	/*
-+	 * Update WCID information
-+	 */
-+	rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
-+
-+	return 0;
-+}
-+
-+static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
-+					 struct rt2x00lib_crypto *crypto,
-+					 struct ieee80211_key_conf *key)
-+{
-+	struct hw_key_entry key_entry;
-+	int timeout;
-+	u32 offset;
-+
-+	if (crypto->cmd == SET_KEY) {
-+		/*
-+		 * 1 pairwise key is possible per AID, this means that the AID
-+		 * equals our hw_key_idx. Make sure the WCID starts _after_ the
-+		 * last possible shared key entry.
-+		 */
-+		if (crypto->aid > (256 - 32))
-+			return -ENOSPC;
-+
-+		key->hw_key_idx = 32 + crypto->aid;
-+
-+		memcpy(key_entry.key, crypto->key,
-+		       sizeof(key_entry.key));
-+		memcpy(key_entry.tx_mic, crypto->tx_mic,
-+		       sizeof(key_entry.tx_mic));
-+		memcpy(key_entry.rx_mic, crypto->rx_mic,
-+		       sizeof(key_entry.rx_mic));
-+
-+		offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
-+		timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
-+		rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
-+						    USB_VENDOR_REQUEST_OUT,
-+						    offset, &key_entry,
-+						    sizeof(key_entry),
-+						    timeout);
-+	}
-+
-+	/*
-+	 * Update WCID information
-+	 */
-+	rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
-+
-+	return 0;
-+}
-+
-+static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
-+				    const unsigned int filter_flags)
-+{
-+	u32 reg;
-+
-+	/*
-+	 * Start configuration steps.
-+	 * Note that the version error will always be dropped
-+	 * and broadcast frames will always be accepted since
-+	 * there is no filter for it at this time.
-+	 */
-+	rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
-+			   !(filter_flags & FIF_FCSFAIL));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
-+			   !(filter_flags & FIF_PLCPFAIL));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
-+			   !(filter_flags & FIF_PROMISC_IN_BSS));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
-+			   !(filter_flags & FIF_ALLMULTI));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
-+			   !(filter_flags & FIF_CONTROL));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
-+			   !(filter_flags & FIF_CONTROL));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
-+			   !(filter_flags & FIF_CONTROL));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
-+			   !(filter_flags & FIF_CONTROL));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
-+			   !(filter_flags & FIF_CONTROL));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
-+			   !(filter_flags & FIF_CONTROL));
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
-+	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
-+			   !(filter_flags & FIF_CONTROL));
-+	rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
-+}
-+
-+static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
-+				  struct rt2x00_intf *intf,
-+				  struct rt2x00intf_conf *conf,
-+				  const unsigned int flags)
-+{
-+	unsigned int beacon_base;
-+	u32 reg;
-+
-+	if (flags & CONFIG_UPDATE_TYPE) {
-+		/*
-+		 * Clear current synchronisation setup.
-+		 * For the Beacon base registers we only need to clear
-+		 * the first byte since that byte contains the VALID and OWNER
-+		 * bits which (when set to 0) will invalidate the entire beacon.
-+		 */
-+		beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
-+		rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
-+
-+		/*
-+		 * Enable synchronisation.
-+		 */
-+		rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
-+		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
-+		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
-+		rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
-+		rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
-+	}
-+
-+	if (flags & CONFIG_UPDATE_MAC) {
-+		reg = le32_to_cpu(conf->mac[1]);
-+		rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
-+		conf->mac[1] = cpu_to_le32(reg);
-+
-+		rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
-+					      conf->mac, sizeof(conf->mac));
-+	}
-+
-+	if (flags & CONFIG_UPDATE_BSSID) {
-+		reg = le32_to_cpu(conf->bssid[1]);
-+		rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
-+		rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
-+		conf->bssid[1] = cpu_to_le32(reg);
-+
-+		rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
-+					      conf->bssid, sizeof(conf->bssid));
-+	}
-+}
-+
-+static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
-+				 struct rt2x00lib_erp *erp)
-+{
-+	u32 reg;
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
-+	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
-+			   DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
-+	rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
-+	rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
-+			   !!erp->short_preamble);
-+	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
-+			   !!erp->short_preamble);
-+	rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
-+			   erp->cts_protection ? 2 : 0);
-+	rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
-+
-+	rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
-+				 erp->basic_rates);
-+	rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
-+
-+	rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
-+	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
-+	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
-+	rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
-+	rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
-+	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
-+	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
-+	rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
-+	rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
-+	rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
-+}
-+
-+static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
-+				 struct antenna_setup *ant)
-+{
-+	u16 eeprom;
-+	u8 r1;
-+	u8 r3;
-+
-+	/*
-+	 * FIXME: Use requested antenna configuration.
-+	 */
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-+
-+	rt2800usb_bbp_read(rt2x00dev, 1, &r1);
-+	rt2800usb_bbp_read(rt2x00dev, 3, &r3);
-+
-+	/*
-+	 * Configure the TX antenna.
-+	 */
-+	switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
-+	case 1:
-+		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
-+		break;
-+	case 2:
-+		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
-+		break;
-+	case 3:
-+		/* Do nothing */
-+		break;
-+	}
-+
-+	/*
-+	 * Configure the RX antenna.
-+	 */
-+	switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
-+	case 1:
-+		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
-+		break;
-+	case 2:
-+		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
-+		break;
-+	case 3:
-+		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
-+		break;
-+	}
-+
-+	rt2800usb_bbp_write(rt2x00dev, 3, r3);
-+	rt2800usb_bbp_write(rt2x00dev, 1, r1);
-+}
-+
-+static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
-+				      struct rt2x00lib_conf *libconf)
-+{
-+	u16 eeprom;
-+	short lna_gain;
-+
-+	if (libconf->rf.channel <= 14) {
-+		rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
-+		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
-+	} else if (libconf->rf.channel <= 64) {
-+		rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
-+		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
-+	} else if (libconf->rf.channel <= 128) {
-+		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
-+		lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
-+	} else {
-+		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
-+		lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
-+	}
-+
-+	rt2x00dev->lna_gain = lna_gain;
-+}
-+
-+static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
-+					  struct ieee80211_conf *conf,
-+					  struct rf_channel *rf,
-+					  struct channel_info *info)
-+{
-+	u16 eeprom;
-+
-+	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
-+
-+	/*
-+	 * Determine antenna settings from EEPROM
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-+
-+	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
-+		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
-+
-+	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
-+		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
-+		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
-+	} else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
-+		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
-+
-+	if (rf->channel > 14) {
-+		/*
-+		 * When TX power is below 0, we should increase it by 7 to
-+		 * make it a positive value (Minumum value is -7).
-+		 * However this means that values between 0 and 7 have
-+		 * double meaning, and we should set a 7DBm boost flag.
-+		 */
-+		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
-+				   (info->tx_power1 >= 0));
-+
-+		if (info->tx_power1 < 0)
-+			info->tx_power1 += 7;
-+
-+		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
-+				   TXPOWER_A_TO_DEV(info->tx_power1));
-+
-+		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
-+				   (info->tx_power2 >= 0));
-+
-+		if (info->tx_power2 < 0)
-+			info->tx_power2 += 7;
-+
-+		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
-+				   TXPOWER_A_TO_DEV(info->tx_power2));
-+	} else {
-+		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
-+				   TXPOWER_G_TO_DEV(info->tx_power1));
-+		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
-+				   TXPOWER_G_TO_DEV(info->tx_power2));
-+	}
-+
-+	rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
-+
-+	rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
-+	rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
-+	rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
-+	rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
-+
-+	udelay(200);
-+
-+	rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
-+	rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
-+	rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
-+	rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
-+
-+	udelay(200);
-+
-+	rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
-+	rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
-+	rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
-+	rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
-+}
-+
-+static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
-+					  struct ieee80211_conf *conf,
-+					  struct rf_channel *rf,
-+					  struct channel_info *info)
-+{
-+	u8 rfcsr;
-+
-+	rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
-+	rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
-+
-+	rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
-+	rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
-+	rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
-+
-+	rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
-+	rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
-+			  TXPOWER_G_TO_DEV(info->tx_power1));
-+	rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
-+
-+	rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
-+	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
-+	rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
-+
-+	if (conf_is_ht40(conf))
-+		rt2800usb_rfcsr_write(rt2x00dev, 24,
-+				      rt2x00dev->calibration_bw40);
-+	else
-+		rt2800usb_rfcsr_write(rt2x00dev, 24,
-+				      rt2x00dev->calibration_bw20);
-+
-+	rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
-+	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
-+	rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
-+}
-+
-+static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
-+				     struct ieee80211_conf *conf,
-+				     struct rf_channel *rf,
-+				     struct channel_info *info)
-+{
-+	u32 reg;
-+	unsigned int tx_pin;
-+	u16 eeprom;
-+	u8 bbp;
-+
-+	/*
-+	 * Determine antenna settings from EEPROM
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-+
-+	if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
-+		rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
-+	else
-+		rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
-+
-+	/*
-+	 * Change BBP settings
-+	 */
-+	rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
-+	rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
-+	rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
-+	rt2800usb_bbp_write(rt2x00dev, 86, 0);
-+
-+	if (rf->channel <= 14) {
-+		if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
-+			rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
-+			rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
-+		} else {
-+			rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
-+			rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
-+		}
-+	} else {
-+		rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
-+
-+		if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
-+			rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
-+		else
-+			rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
-+	}
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
-+	rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
-+	rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
-+	rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
-+	rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
-+
-+	tx_pin = 0;
-+
-+	/* Turn on unused PA or LNA when not using 1T or 1R */
-+	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
-+		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
-+		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
-+	}
-+
-+	/* Turn on unused PA or LNA when not using 1T or 1R */
-+	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
-+		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
-+		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
-+	}
-+
-+	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
-+	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
-+	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
-+	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
-+	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
-+	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
-+
-+	rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
-+
-+	rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
-+	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
-+	rt2800usb_bbp_write(rt2x00dev, 4, bbp);
-+
-+	rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
-+	rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
-+	rt2800usb_bbp_write(rt2x00dev, 3, bbp);
-+
-+	if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
-+		if (conf_is_ht40(conf)) {
-+			rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
-+			rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
-+			rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
-+		} else {
-+			rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
-+			rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
-+			rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
-+		}
-+	}
-+
-+	msleep(1);
-+}
-+
-+static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
-+				     const int txpower)
-+{
-+	u32 reg;
-+	u32 value = TXPOWER_G_TO_DEV(txpower);
-+	u8 r1;
-+
-+	rt2800usb_bbp_read(rt2x00dev, 1, &r1);
-+	rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
-+	rt2800usb_bbp_write(rt2x00dev, 1, r1);
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
-+	rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
-+	rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
-+	rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
-+	rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
-+	rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
-+	rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
-+}
-+
-+static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
-+					 struct rt2x00lib_conf *libconf)
-+{
-+	u32 reg;
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
-+	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
-+			   libconf->conf->short_frame_max_tx_count);
-+	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
-+			   libconf->conf->long_frame_max_tx_count);
-+	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
-+	rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
-+	rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
-+	rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
-+	rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
-+}
-+
-+static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
-+				      struct rt2x00lib_conf *libconf)
-+{
-+	u32 reg;
-+
-+	rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
-+			   libconf->conf->beacon_int * 16);
-+	rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
-+}
-+
-+static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
-+				struct rt2x00lib_conf *libconf)
-+{
-+	enum dev_state state =
-+	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
-+		STATE_SLEEP : STATE_AWAKE;
-+	u32 reg;
-+
-+	if (state == STATE_SLEEP) {
-+		rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
-+
-+		rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
-+		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
-+		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
-+				   libconf->conf->listen_interval - 1);
-+		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
-+		rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
-+
-+		rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
-+	} else {
-+		rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
-+
-+		rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
-+		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
-+		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
-+		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
-+		rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
-+	}
-+}
-+
-+static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
-+			     struct rt2x00lib_conf *libconf,
-+			     const unsigned int flags)
-+{
-+	/* Always recalculate LNA gain before changing configuration */
-+	rt2800usb_config_lna_gain(rt2x00dev, libconf);
-+
-+	if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
-+		rt2800usb_config_channel(rt2x00dev, libconf->conf,
-+					 &libconf->rf, &libconf->channel);
-+	if (flags & IEEE80211_CONF_CHANGE_POWER)
-+		rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
-+	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
-+		rt2800usb_config_retry_limit(rt2x00dev, libconf);
-+	if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
-+		rt2800usb_config_duration(rt2x00dev, libconf);
-+	if (flags & IEEE80211_CONF_CHANGE_PS)
-+		rt2800usb_config_ps(rt2x00dev, libconf);
-+}
-+
-+/*
-+ * Link tuning
-+ */
-+static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
-+				 struct link_qual *qual)
-+{
-+	u32 reg;
-+
-+	/*
-+	 * Update FCS error count from register.
-+	 */
-+	rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
-+	qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
-+}
-+
-+static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
-+{
-+	if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
-+		if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
-+			return 0x1c + (2 * rt2x00dev->lna_gain);
-+		else
-+			return 0x2e + rt2x00dev->lna_gain;
-+	}
-+
-+	if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
-+		return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
-+	else
-+		return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
-+}
-+
-+static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
-+				     struct link_qual *qual, u8 vgc_level)
-+{
-+	if (qual->vgc_level != vgc_level) {
-+		rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
-+		qual->vgc_level = vgc_level;
-+		qual->vgc_level_reg = vgc_level;
-+	}
-+}
-+
-+static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
-+				  struct link_qual *qual)
-+{
-+	rt2800usb_set_vgc(rt2x00dev, qual,
-+			  rt2800usb_get_default_vgc(rt2x00dev));
-+}
-+
-+static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
-+				 struct link_qual *qual, const u32 count)
-+{
-+	if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
-+		return;
-+
-+	/*
-+	 * When RSSI is better then -80 increase VGC level with 0x10
-+	 */
-+	rt2800usb_set_vgc(rt2x00dev, qual,
-+			  rt2800usb_get_default_vgc(rt2x00dev) +
-+			  ((qual->rssi > -80) * 0x10));
-+}
-+
-+/*
-+ * Firmware functions
-+ */
-+static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
-+{
-+	return FIRMWARE_RT2870;
-+}
-+
-+static bool rt2800usb_check_crc(const u8 *data, const size_t len)
-+{
-+	u16 fw_crc;
-+	u16 crc;
-+
-+	/*
-+	 * The last 2 bytes in the firmware array are the crc checksum itself,
-+	 * this means that we should never pass those 2 bytes to the crc
-+	 * algorithm.
-+	 */
-+	fw_crc = (data[len - 2] << 8 | data[len - 1]);
-+
-+	/*
-+	 * Use the crc ccitt algorithm.
-+	 * This will return the same value as the legacy driver which
-+	 * used bit ordering reversion on the both the firmware bytes
-+	 * before input input as well as on the final output.
-+	 * Obviously using crc ccitt directly is much more efficient.
-+	 */
-+	crc = crc_ccitt(~0, data, len - 2);
-+
-+	/*
-+	 * There is a small difference between the crc-itu-t + bitrev and
-+	 * the crc-ccitt crc calculation. In the latter method the 2 bytes
-+	 * will be swapped, use swab16 to convert the crc to the correct
-+	 * value.
-+	 */
-+	crc = swab16(crc);
-+
-+	return fw_crc == crc;
-+}
-+
-+static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
-+				    const u8 *data, const size_t len)
-+{
-+	u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
-+	size_t offset = 0;
-+
-+	/*
-+	 * Firmware files:
-+	 * There are 2 variations of the rt2870 firmware.
-+	 * a) size: 4kb
-+	 * b) size: 8kb
-+	 * Note that (b) contains 2 seperate firmware blobs of 4k
-+	 * within the file. The first blob is the same firmware as (a),
-+	 * but the second blob is for the additional chipsets.
-+	 */
-+	if (len != 4096 && len != 8192)
-+		return FW_BAD_LENGTH;
-+
-+	/*
-+	 * Check if we need the upper 4kb firmware data or not.
-+	 */
-+	if ((len == 4096) &&
-+	    (chipset != 0x2860) &&
-+	    (chipset != 0x2872) &&
-+	    (chipset != 0x3070))
-+		return FW_BAD_VERSION;
-+
-+	/*
-+	 * 8kb firmware files must be checked as if it were
-+	 * 2 seperate firmware files.
-+	 */
-+	while (offset < len) {
-+		if (!rt2800usb_check_crc(data + offset, 4096))
-+			return FW_BAD_CRC;
-+
-+		offset += 4096;
-+	}
-+
-+	return FW_OK;
-+}
-+
-+static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
-+				   const u8 *data, const size_t len)
-+{
-+	unsigned int i;
-+	int status;
-+	u32 reg;
-+	u32 offset;
-+	u32 length;
-+	u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
-+
-+	/*
-+	 * Check which section of the firmware we need.
-+	 */
-+	if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
-+		offset = 0;
-+		length = 4096;
-+	} else {
-+		offset = 4096;
-+		length = 4096;
-+	}
-+
-+	/*
-+	 * Wait for stable hardware.
-+	 */
-+	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-+		rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
-+		if (reg && reg != ~0)
-+			break;
-+		msleep(1);
-+	}
-+
-+	if (i == REGISTER_BUSY_COUNT) {
-+		ERROR(rt2x00dev, "Unstable hardware.\n");
-+		return -EBUSY;
-+	}
-+
-+	/*
-+	 * Write firmware to device.
-+	 */
-+	rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
-+					    USB_VENDOR_REQUEST_OUT,
-+					    FIRMWARE_IMAGE_BASE,
-+					    data + offset, length,
-+					    REGISTER_TIMEOUT32(length));
-+
-+	rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
-+	rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
-+
-+	/*
-+	 * Send firmware request to device to load firmware,
-+	 * we need to specify a long timeout time.
-+	 */
-+	status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
-+					     0, USB_MODE_FIRMWARE,
-+					     REGISTER_TIMEOUT_FIRMWARE);
-+	if (status < 0) {
-+		ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
-+		return status;
-+	}
-+
-+	/*
-+	 * Wait for device to stabilize.
-+	 */
-+	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-+		rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
-+		if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
-+			break;
-+		msleep(1);
-+	}
-+
-+	if (i == REGISTER_BUSY_COUNT) {
-+		ERROR(rt2x00dev, "PBF system register not ready.\n");
-+		return -EBUSY;
-+	}
-+
-+	/*
-+	 * Initialize firmware.
-+	 */
-+	rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
-+	rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
-+	msleep(1);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Initialization functions.
-+ */
-+static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
-+{
-+	u32 reg;
-+	unsigned int i;
-+
-+	/*
-+	 * Wait untill BBP and RF are ready.
-+	 */
-+	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-+		rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
-+		if (reg && reg != ~0)
-+			break;
-+		msleep(1);
-+	}
-+
-+	if (i == REGISTER_BUSY_COUNT) {
-+		ERROR(rt2x00dev, "Unstable hardware.\n");
-+		return -EBUSY;
-+	}
-+
-+	rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
-+	rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
-+
-+	rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
-+	rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
-+	rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
-+	rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
-+
-+	rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
-+
-+	rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
-+				    USB_MODE_RESET, REGISTER_TIMEOUT);
-+
-+	rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
-+
-+	rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
-+	rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
-+	rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
-+	rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
-+	rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
-+	rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
-+	rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
-+	rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
-+	rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
-+	rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
-+	rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
-+
-+	rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
-+	rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
-+
-+	rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
-+
-+	rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
-+	rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
-+
-+	if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
-+		rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
-+		rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
-+		rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
-+	} else {
-+		rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
-+		rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
-+	}
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
-+	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
-+	rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
-+	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
-+	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
-+	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
-+	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
-+	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
-+	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
-+	rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
-+	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
-+	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
-+	rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
-+	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
-+	if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
-+	    rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
-+		rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
-+	else
-+		rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
-+	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
-+	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
-+	rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
-+
-+	rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
-+
-+	rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
-+	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
-+	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
-+	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
-+	rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
-+	rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
-+	rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
-+	rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
-+	rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
-+	rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
-+	rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
-+	rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
-+	rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
-+
-+	rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
-+
-+	rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
-+	rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
-+
-+	rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
-+	rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
-+	rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
-+	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
-+			   IEEE80211_MAX_RTS_THRESHOLD);
-+	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
-+	rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
-+
-+	rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
-+	rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
-+
-+	/*
-+	 * ASIC will keep garbage value after boot, clear encryption keys.
-+	 */
-+	for (i = 0; i < 256; i++) {
-+		u32 wcid[2] = { 0xffffffff, 0x00ffffff };
-+		rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
-+					      wcid, sizeof(wcid));
-+
-+		rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
-+		rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
-+	}
-+
-+	for (i = 0; i < 16; i++)
-+		rt2x00usb_register_write(rt2x00dev,
-+					 SHARED_KEY_MODE_ENTRY(i), 0);
-+
-+	/*
-+	 * Clear all beacons
-+	 * For the Beacon base registers we only need to clear
-+	 * the first byte since that byte contains the VALID and OWNER
-+	 * bits which (when set to 0) will invalidate the entire beacon.
-+	 */
-+	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
-+	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
-+	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
-+	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
-+	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
-+	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
-+	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
-+	rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
-+
-+	rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
-+	rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
-+	rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
-+	rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
-+	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
-+	rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
-+	rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
-+	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
-+	rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
-+
-+	/*
-+	 * We must clear the error counters.
-+	 * These registers are cleared on read,
-+	 * so we may pass a useless variable to store the value.
-+	 */
-+	rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
-+	rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
-+	rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
-+	rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
-+	rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
-+	rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
-+
-+	return 0;
-+}
-+
-+static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
-+{
-+	unsigned int i;
-+	u32 reg;
-+
-+	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-+		rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
-+		if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
-+			return 0;
-+
-+		udelay(REGISTER_BUSY_DELAY);
-+	}
-+
-+	ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
-+	return -EACCES;
-+}
-+
-+static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
-+{
-+	unsigned int i;
-+	u8 value;
-+
-+	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-+		rt2800usb_bbp_read(rt2x00dev, 0, &value);
-+		if ((value != 0xff) && (value != 0x00))
-+			return 0;
-+		udelay(REGISTER_BUSY_DELAY);
-+	}
-+
-+	ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
-+	return -EACCES;
-+}
-+
-+static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
-+{
-+	unsigned int i;
-+	u16 eeprom;
-+	u8 reg_id;
-+	u8 value;
-+
-+	if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
-+		     rt2800usb_wait_bbp_ready(rt2x00dev)))
-+		return -EACCES;
-+
-+	rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
-+	rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
-+	rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
-+	rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
-+	rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
-+	rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
-+	rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
-+	rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
-+	rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
-+	rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
-+	rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
-+	rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
-+	rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
-+	rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
-+
-+	if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
-+		rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
-+		rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
-+	}
-+
-+	if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
-+		rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
-+	}
-+
-+	if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
-+		rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
-+		rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
-+		rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
-+	}
-+
-+	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
-+		rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-+
-+		if (eeprom != 0xffff && eeprom != 0x0000) {
-+			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
-+			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
-+			rt2800usb_bbp_write(rt2x00dev, reg_id, value);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
-+				   bool bw40, u8 rfcsr24, u8 filter_target)
-+{
-+	unsigned int i;
-+	u8 bbp;
-+	u8 rfcsr;
-+	u8 passband;
-+	u8 stopband;
-+	u8 overtuned = 0;
-+
-+	rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
-+
-+	rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
-+	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
-+	rt2800usb_bbp_write(rt2x00dev, 4, bbp);
-+
-+	rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
-+	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
-+	rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
-+
-+	/*
-+	 * Set power & frequency of passband test tone
-+	 */
-+	rt2800usb_bbp_write(rt2x00dev, 24, 0);
-+
-+	for (i = 0; i < 100; i++) {
-+		rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
-+		msleep(1);
-+
-+		rt2800usb_bbp_read(rt2x00dev, 55, &passband);
-+		if (passband)
-+			break;
-+	}
-+
-+	/*
-+	 * Set power & frequency of stopband test tone
-+	 */
-+	rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
-+
-+	for (i = 0; i < 100; i++) {
-+		rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
-+		msleep(1);
-+
-+		rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
-+
-+		if ((passband - stopband) <= filter_target) {
-+			rfcsr24++;
-+			overtuned += ((passband - stopband) == filter_target);
-+		} else
-+			break;
-+
-+		rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
-+	}
-+
-+	rfcsr24 -= !!overtuned;
-+
-+	rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
-+	return rfcsr24;
-+}
-+
-+static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
-+{
-+	u8 rfcsr;
-+	u8 bbp;
-+
-+	if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
-+		return 0;
-+
-+	/*
-+	 * Init RF calibration.
-+	 */
-+	rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
-+	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
-+	rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
-+	msleep(1);
-+	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
-+	rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
-+
-+	rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
-+	rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
-+	rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
-+	rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
-+	rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
-+	rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
-+	rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
-+	rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
-+	rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
-+	rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
-+	rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
-+	rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
-+	rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
-+	rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
-+	rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
-+	rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
-+	rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
-+	rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
-+	rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
-+	rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
-+
-+	/*
-+	 * Set RX Filter calibration for 20MHz and 40MHz
-+	 */
-+	rt2x00dev->calibration_bw20 =
-+	    rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
-+	rt2x00dev->calibration_bw40 =
-+	    rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
-+
-+	/*
-+	 * Set back to initial state
-+	 */
-+	rt2800usb_bbp_write(rt2x00dev, 24, 0);
-+
-+	rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
-+	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
-+	rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
-+
-+	/*
-+	 * set BBP back to BW20
-+	 */
-+	rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
-+	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
-+	rt2800usb_bbp_write(rt2x00dev, 4, bbp);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Device state switch handlers.
-+ */
-+static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
-+				enum dev_state state)
-+{
-+	u32 reg;
-+
-+	rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
-+	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
-+			   (state == STATE_RADIO_RX_ON) ||
-+			   (state == STATE_RADIO_RX_ON_LINK));
-+	rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
-+}
-+
-+static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
-+{
-+	unsigned int i;
-+	u32 reg;
-+
-+	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-+		rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
-+		if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
-+		    !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
-+			return 0;
-+
-+		msleep(1);
-+	}
-+
-+	ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
-+	return -EACCES;
-+}
-+
-+static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
-+{
-+	u32 reg;
-+	u16 word;
-+
-+	/*
-+	 * Initialize all registers.
-+	 */
-+	if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
-+		     rt2800usb_init_registers(rt2x00dev) ||
-+		     rt2800usb_init_bbp(rt2x00dev) ||
-+		     rt2800usb_init_rfcsr(rt2x00dev)))
-+		return -EIO;
-+
-+	rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
-+	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
-+	rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
-+
-+	udelay(50);
-+
-+	rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
-+	rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
-+
-+
-+	rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
-+	rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
-+	/* Don't use bulk in aggregation when working with USB 1.1 */
-+	rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
-+			   (rt2x00dev->rx->usb_maxpacket == 512));
-+	rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
-+	/* FIXME: Calculate this value based on Aggregation defines */
-+	rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
-+	rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
-+	rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
-+	rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
-+	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
-+	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
-+	rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
-+
-+	/*
-+	 * Send signal to firmware during boot time.
-+	 */
-+	rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
-+
-+	/*
-+	 * Initialize LED control
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
-+	rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
-+			      word & 0xff, (word >> 8) & 0xff);
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
-+	rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
-+			      word & 0xff, (word >> 8) & 0xff);
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
-+	rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
-+			      word & 0xff, (word >> 8) & 0xff);
-+
-+	return 0;
-+}
-+
-+static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
-+{
-+	u32 reg;
-+
-+	rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
-+	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
-+	rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
-+
-+	rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
-+	rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
-+	rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
-+
-+	/* Wait for DMA, ignore error */
-+	rt2800usb_wait_wpdma_ready(rt2x00dev);
-+
-+	rt2x00usb_disable_radio(rt2x00dev);
-+}
-+
-+static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
-+			       enum dev_state state)
-+{
-+	rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
-+
-+	if (state == STATE_AWAKE)
-+		rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
-+	else
-+		rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
-+
-+	return 0;
-+}
-+
-+static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
-+				      enum dev_state state)
-+{
-+	int retval = 0;
-+
-+	switch (state) {
-+	case STATE_RADIO_ON:
-+		/*
-+		 * Before the radio can be enabled, the device first has
-+		 * to be woken up. After that it needs a bit of time
-+		 * to be fully awake and the radio can be enabled.
-+		 */
-+		rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
-+		msleep(1);
-+		retval = rt2800usb_enable_radio(rt2x00dev);
-+		break;
-+	case STATE_RADIO_OFF:
-+		/*
-+		 * After the radio has been disablee, the device should
-+		 * be put to sleep for powersaving.
-+		 */
-+		rt2800usb_disable_radio(rt2x00dev);
-+		rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
-+		break;
-+	case STATE_RADIO_RX_ON:
-+	case STATE_RADIO_RX_ON_LINK:
-+	case STATE_RADIO_RX_OFF:
-+	case STATE_RADIO_RX_OFF_LINK:
-+		rt2800usb_toggle_rx(rt2x00dev, state);
-+		break;
-+	case STATE_RADIO_IRQ_ON:
-+	case STATE_RADIO_IRQ_OFF:
-+		/* No support, but no error either */
-+		break;
-+	case STATE_DEEP_SLEEP:
-+	case STATE_SLEEP:
-+	case STATE_STANDBY:
-+	case STATE_AWAKE:
-+		retval = rt2800usb_set_state(rt2x00dev, state);
-+		break;
-+	default:
-+		retval = -ENOTSUPP;
-+		break;
-+	}
-+
-+	if (unlikely(retval))
-+		ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
-+		      state, retval);
-+
-+	return retval;
-+}
-+
-+/*
-+ * TX descriptor initialization
-+ */
-+static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
-+				    struct sk_buff *skb,
-+				    struct txentry_desc *txdesc)
-+{
-+	struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
-+	__le32 *txi = skbdesc->desc;
-+	__le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
-+	u32 word;
-+
-+	/*
-+	 * Initialize TX Info descriptor
-+	 */
-+	rt2x00_desc_read(txwi, 0, &word);
-+	rt2x00_set_field32(&word, TXWI_W0_FRAG,
-+			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
-+	rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
-+	rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
-+	rt2x00_set_field32(&word, TXWI_W0_TS,
-+			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
-+	rt2x00_set_field32(&word, TXWI_W0_AMPDU,
-+			   test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
-+	rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
-+	rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
-+	rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
-+	rt2x00_set_field32(&word, TXWI_W0_BW,
-+			   test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
-+	rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
-+			   test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
-+	rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
-+	rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
-+	rt2x00_desc_write(txwi, 0, word);
-+
-+	rt2x00_desc_read(txwi, 1, &word);
-+	rt2x00_set_field32(&word, TXWI_W1_ACK,
-+			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
-+	rt2x00_set_field32(&word, TXWI_W1_NSEQ,
-+			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
-+	rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
-+	rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
-+			   test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
-+			       txdesc->key_idx : 0xff);
-+	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
-+	rt2x00_set_field32(&word, TXWI_W1_PACKETID,
-+			   skbdesc->entry->entry_idx);
-+	rt2x00_desc_write(txwi, 1, word);
-+
-+	/*
-+	 * Always write 0 to IV/EIV fields, hardware will insert the IV
-+	 * from the IVEIV register when TXINFO_W0_WIV is set to 0.
-+	 * When TXINFO_W0_WIV is set to 1 it will use the IV data
-+	 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
-+	 * crypto entry in the registers should be used to encrypt the frame.
-+	 */
-+	_rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
-+	_rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
-+
-+	/*
-+	 * Initialize TX descriptor
-+	 */
-+	rt2x00_desc_read(txi, 0, &word);
-+	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
-+			   skb->len + TXWI_DESC_SIZE);
-+	rt2x00_set_field32(&word, TXINFO_W0_WIV,
-+			   !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
-+	rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
-+	rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
-+	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
-+	rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
-+			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));
-+	rt2x00_desc_write(txi, 0, word);
-+}
-+
-+/*
-+ * TX data initialization
-+ */
-+static void rt2800usb_write_beacon(struct queue_entry *entry)
-+{
-+	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
-+	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
-+	unsigned int beacon_base;
-+	u32 reg;
-+
-+	/*
-+	 * Add the descriptor in front of the skb.
-+	 */
-+	skb_push(entry->skb, entry->queue->desc_size);
-+	memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
-+	skbdesc->desc = entry->skb->data;
-+
-+	/*
-+	 * Disable beaconing while we are reloading the beacon data,
-+	 * otherwise we might be sending out invalid data.
-+	 */
-+	rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
-+	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
-+	rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
-+
-+	/*
-+	 * Write entire beacon with descriptor to register.
-+	 */
-+	beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
-+	rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
-+					    USB_VENDOR_REQUEST_OUT, beacon_base,
-+					    entry->skb->data, entry->skb->len,
-+					    REGISTER_TIMEOUT32(entry->skb->len));
-+
-+	/*
-+	 * Clean up the beacon skb.
-+	 */
-+	dev_kfree_skb(entry->skb);
-+	entry->skb = NULL;
-+}
-+
-+static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
-+{
-+	int length;
-+
-+	/*
-+	 * The length _must_ include 4 bytes padding,
-+	 * it should always be multiple of 4,
-+	 * but it must _not_ be a multiple of the USB packet size.
-+	 */
-+	length = roundup(entry->skb->len + 4, 4);
-+	length += (4 * !(length % entry->queue->usb_maxpacket));
-+
-+	return length;
-+}
-+
-+static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
-+				    const enum data_queue_qid queue)
-+{
-+	u32 reg;
-+
-+	if (queue != QID_BEACON) {
-+		rt2x00usb_kick_tx_queue(rt2x00dev, queue);
-+		return;
-+	}
-+
-+	rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
-+	if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
-+		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
-+		rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
-+		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
-+		rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
-+	}
-+}
-+
-+/*
-+ * RX control handlers
-+ */
-+static void rt2800usb_fill_rxdone(struct queue_entry *entry,
-+				  struct rxdone_entry_desc *rxdesc)
-+{
-+	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
-+	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
-+	__le32 *rxd = (__le32 *)entry->skb->data;
-+	__le32 *rxwi;
-+	u32 rxd0;
-+	u32 rxwi0;
-+	u32 rxwi1;
-+	u32 rxwi2;
-+	u32 rxwi3;
-+
-+	/*
-+	 * Copy descriptor to the skbdesc->desc buffer, making it safe from
-+	 * moving of frame data in rt2x00usb.
-+	 */
-+	memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
-+	rxd = (__le32 *)skbdesc->desc;
-+	rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
-+
-+	/*
-+	 * It is now safe to read the descriptor on all architectures.
-+	 */
-+	rt2x00_desc_read(rxd, 0, &rxd0);
-+	rt2x00_desc_read(rxwi, 0, &rxwi0);
-+	rt2x00_desc_read(rxwi, 1, &rxwi1);
-+	rt2x00_desc_read(rxwi, 2, &rxwi2);
-+	rt2x00_desc_read(rxwi, 3, &rxwi3);
-+
-+	if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
-+		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
-+
-+	if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
-+		rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
-+		rxdesc->cipher_status =
-+		    rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
-+	}
-+
-+	if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
-+		/*
-+		 * Hardware has stripped IV/EIV data from 802.11 frame during
-+		 * decryption. Unfortunately the descriptor doesn't contain
-+		 * any fields with the EIV/IV data either, so they can't
-+		 * be restored by rt2x00lib.
-+		 */
-+		rxdesc->flags |= RX_FLAG_IV_STRIPPED;
-+
-+		if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
-+			rxdesc->flags |= RX_FLAG_DECRYPTED;
-+		else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
-+			rxdesc->flags |= RX_FLAG_MMIC_ERROR;
-+	}
-+
-+	if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
-+		rxdesc->dev_flags |= RXDONE_MY_BSS;
-+
-+	if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
-+		rxdesc->flags |= RX_FLAG_SHORT_GI;
-+
-+	if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
-+		rxdesc->flags |= RX_FLAG_40MHZ;
-+
-+	/*
-+	 * Detect RX rate, always use MCS as signal type.
-+	 */
-+	rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
-+	rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
-+	rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
-+
-+	/*
-+	 * Mask of 0x8 bit to remove the short preamble flag.
-+	 */
-+	if (rxdesc->rate_mode == RATE_MODE_CCK)
-+		rxdesc->signal &= ~0x8;
-+
-+	rxdesc->rssi =
-+	    (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
-+	     rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
-+
-+	rxdesc->noise =
-+	    (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
-+	     rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
-+
-+	rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
-+
-+	/*
-+	 * Remove RXWI descriptor from start of buffer.
-+	 */
-+	skb_pull(entry->skb, skbdesc->desc_len);
-+	skb_trim(entry->skb, rxdesc->size);
-+}
-+
-+/*
-+ * Device probe functions.
-+ */
-+static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-+{
-+	u16 word;
-+	u8 *mac;
-+	u8 default_lna_gain;
-+
-+	rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
-+
-+	/*
-+	 * Start validation of the data that has been read.
-+	 */
-+	mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
-+	if (!is_valid_ether_addr(mac)) {
-+		DECLARE_MAC_BUF(macbuf);
-+
-+		random_ether_addr(mac);
-+		EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
-+	}
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
-+	if (word == 0xffff) {
-+		rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
-+		rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
-+		rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
-+		rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
-+		EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
-+	} else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
-+		/*
-+		 * There is a max of 2 RX streams for RT2860 series
-+		 */
-+		if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
-+			rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
-+		rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
-+	}
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
-+	if (word == 0xffff) {
-+		rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
-+		rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
-+		rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
-+		EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
-+	}
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
-+	if ((word & 0x00ff) == 0x00ff) {
-+		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
-+		rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
-+				   LED_MODE_TXRX_ACTIVITY);
-+		rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
-+		rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
-+		rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
-+		rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
-+		rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
-+		EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
-+	}
-+
-+	/*
-+	 * During the LNA validation we are going to use
-+	 * lna0 as correct value. Note that EEPROM_LNA
-+	 * is never validated.
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
-+	default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
-+	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
-+		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
-+	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
-+		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
-+	rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
-+	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
-+		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
-+	if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
-+	    rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
-+		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
-+				   default_lna_gain);
-+	rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
-+	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
-+		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
-+	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
-+		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
-+	rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
-+	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
-+		rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
-+	if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
-+	    rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
-+		rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
-+				   default_lna_gain);
-+	rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
-+
-+	return 0;
-+}
-+
-+static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
-+{
-+	u32 reg;
-+	u16 value;
-+	u16 eeprom;
-+
-+	/*
-+	 * Read EEPROM word for configuration.
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-+
-+	/*
-+	 * Identify RF chipset.
-+	 */
-+	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
-+	rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
-+	rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
-+
-+	/*
-+	 * The check for rt2860 is not a typo, some rt2870 hardware
-+	 * identifies itself as rt2860 in the CSR register.
-+	 */
-+	if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
-+	    (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870) &&
-+	    (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x3070)) {
-+		ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
-+		return -ENODEV;
-+	}
-+
-+	if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
-+	    !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
-+	    !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
-+	    !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
-+	    !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
-+	    !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
-+		ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
-+		return -ENODEV;
-+	}
-+
-+	/*
-+	 * Read frequency offset and RF programming sequence.
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
-+	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
-+
-+	/*
-+	 * Read external LNA informations.
-+	 */
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-+
-+	if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
-+		__set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
-+	if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
-+		__set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
-+
-+	/*
-+	 * Detect if this device has an hardware controlled radio.
-+	 */
-+#ifdef CONFIG_RT2X00_LIB_RFKILL
-+	if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
-+		__set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
-+#endif /* CONFIG_RT2X00_LIB_RFKILL */
-+
-+	/*
-+	 * Store led settings, for correct led behaviour.
-+	 */
-+#ifdef CONFIG_RT2X00_LIB_LEDS
-+	rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
-+	rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
-+	rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
-+			   &rt2x00dev->led_mcu_reg);
-+#endif /* CONFIG_RT2X00_LIB_LEDS */
-+
-+	return 0;
-+}
-+
-+/*
-+ * RF value list for rt2870
-+ * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
-+ */
-+static const struct rf_channel rf_vals[] = {
-+	{ 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
-+	{ 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
-+	{ 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
-+	{ 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
-+	{ 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
-+	{ 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
-+	{ 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
-+	{ 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
-+	{ 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
-+	{ 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
-+	{ 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
-+	{ 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
-+	{ 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
-+	{ 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
-+
-+	/* 802.11 UNI / HyperLan 2 */
-+	{ 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
-+	{ 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
-+	{ 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
-+	{ 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
-+	{ 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
-+	{ 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
-+	{ 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
-+	{ 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
-+	{ 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
-+	{ 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
-+	{ 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
-+	{ 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
-+
-+	/* 802.11 HyperLan 2 */
-+	{ 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
-+	{ 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
-+	{ 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
-+	{ 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
-+	{ 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
-+	{ 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
-+	{ 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
-+	{ 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
-+	{ 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
-+	{ 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
-+	{ 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
-+	{ 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
-+	{ 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
-+	{ 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
-+	{ 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
-+	{ 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
-+
-+	/* 802.11 UNII */
-+	{ 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
-+	{ 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
-+	{ 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
-+	{ 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
-+	{ 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
-+	{ 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
-+	{ 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
-+	{ 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
-+	{ 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
-+	{ 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
-+	{ 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
-+
-+	/* 802.11 Japan */
-+	{ 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
-+	{ 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
-+	{ 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
-+	{ 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
-+	{ 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
-+	{ 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
-+	{ 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
-+};
-+
-+/*
-+ * RF value list for rt3070
-+ * Supports: 2.4 GHz
-+ */
-+static const struct rf_channel rf_vals_3070[] = {
-+	{1,  241, 2, 2 },
-+	{2,  241, 2, 7 },
-+	{3,  242, 2, 2 },
-+	{4,  242, 2, 7 },
-+	{5,  243, 2, 2 },
-+	{6,  243, 2, 7 },
-+	{7,  244, 2, 2 },
-+	{8,  244, 2, 7 },
-+	{9,  245, 2, 2 },
-+	{10, 245, 2, 7 },
-+	{11, 246, 2, 2 },
-+	{12, 246, 2, 7 },
-+	{13, 247, 2, 2 },
-+	{14, 248, 2, 4 },
-+};
-+
-+static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-+{
-+	struct hw_mode_spec *spec = &rt2x00dev->spec;
-+	struct channel_info *info;
-+	char *tx_power1;
-+	char *tx_power2;
-+	unsigned int i;
-+	u16 eeprom;
-+
-+	/*
-+	 * Initialize all hw fields.
-+	 */
-+	rt2x00dev->hw->flags =
-+	    IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
-+	    IEEE80211_HW_SIGNAL_DBM |
-+	    IEEE80211_HW_SUPPORTS_PS |
-+	    IEEE80211_HW_PS_NULLFUNC_STACK;
-+	rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
-+
-+	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
-+	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
-+				rt2x00_eeprom_addr(rt2x00dev,
-+						   EEPROM_MAC_ADDR_0));
-+
-+	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-+
-+	/*
-+	 * Initialize HT information.
-+	 */
-+	spec->ht.ht_supported = true;
-+	spec->ht.cap =
-+	    IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
-+	    IEEE80211_HT_CAP_GRN_FLD |
-+	    IEEE80211_HT_CAP_SGI_20 |
-+	    IEEE80211_HT_CAP_SGI_40 |
-+	    IEEE80211_HT_CAP_TX_STBC |
-+	    IEEE80211_HT_CAP_RX_STBC |
-+	    IEEE80211_HT_CAP_PSMP_SUPPORT;
-+	spec->ht.ampdu_factor = 3;
-+	spec->ht.ampdu_density = 4;
-+	spec->ht.mcs.tx_params =
-+	    IEEE80211_HT_MCS_TX_DEFINED |
-+	    IEEE80211_HT_MCS_TX_RX_DIFF |
-+	    ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
-+		IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
-+
-+	switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
-+	case 3:
-+		spec->ht.mcs.rx_mask[2] = 0xff;
-+	case 2:
-+		spec->ht.mcs.rx_mask[1] = 0xff;
-+	case 1:
-+		spec->ht.mcs.rx_mask[0] = 0xff;
-+		spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
-+		break;
-+	}
-+
-+	/*
-+	 * Initialize hw_mode information.
-+	 */
-+	spec->supported_bands = SUPPORT_BAND_2GHZ;
-+	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
-+
-+	if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
-+	    rt2x00_rf(&rt2x00dev->chip, RF2720)) {
-+		spec->num_channels = 14;
-+		spec->channels = rf_vals;
-+	} else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
-+		   rt2x00_rf(&rt2x00dev->chip, RF2750)) {
-+		spec->supported_bands |= SUPPORT_BAND_5GHZ;
-+		spec->num_channels = ARRAY_SIZE(rf_vals);
-+		spec->channels = rf_vals;
-+	} else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
-+		   rt2x00_rf(&rt2x00dev->chip, RF2020)) {
-+		spec->num_channels = ARRAY_SIZE(rf_vals_3070);
-+		spec->channels = rf_vals_3070;
-+	}
-+
-+	/*
-+	 * Create channel information array
-+	 */
-+	info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
-+	if (!info)
-+		return -ENOMEM;
-+
-+	spec->channels_info = info;
-+
-+	tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
-+	tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
-+
-+	for (i = 0; i < 14; i++) {
-+		info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
-+		info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
-+	}
-+
-+	if (spec->num_channels > 14) {
-+		tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
-+		tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
-+
-+		for (i = 14; i < spec->num_channels; i++) {
-+			info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
-+			info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
-+{
-+	int retval;
-+
-+	/*
-+	 * Allocate eeprom data.
-+	 */
-+	retval = rt2800usb_validate_eeprom(rt2x00dev);
-+	if (retval)
-+		return retval;
-+
-+	retval = rt2800usb_init_eeprom(rt2x00dev);
-+	if (retval)
-+		return retval;
-+
-+	/*
-+	 * Initialize hw specifications.
-+	 */
-+	retval = rt2800usb_probe_hw_mode(rt2x00dev);
-+	if (retval)
-+		return retval;
-+
-+	/*
-+	 * This device requires firmware.
-+	 */
-+	__set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
-+	__set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
-+	if (!modparam_nohwcrypt)
-+		__set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
-+
-+	/*
-+	 * Set the rssi offset.
-+	 */
-+	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-+
-+	return 0;
-+}
-+
-+/*
-+ * IEEE80211 stack callback functions.
-+ */
-+static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
-+				   u32 *iv32, u16 *iv16)
-+{
-+	struct rt2x00_dev *rt2x00dev = hw->priv;
-+	struct mac_iveiv_entry iveiv_entry;
-+	u32 offset;
-+
-+	offset = MAC_IVEIV_ENTRY(hw_key_idx);
-+	rt2x00usb_register_multiread(rt2x00dev, offset,
-+				      &iveiv_entry, sizeof(iveiv_entry));
-+
-+	memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
-+	memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
-+}
-+
-+static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
-+{
-+	struct rt2x00_dev *rt2x00dev = hw->priv;
-+	u32 reg;
-+	bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
-+
-+	rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
-+	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
-+	rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
-+	rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
-+	rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
-+	rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
-+	rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
-+	rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
-+	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
-+	rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
-+
-+	return 0;
-+}
-+
-+static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
-+			     const struct ieee80211_tx_queue_params *params)
-+{
-+	struct rt2x00_dev *rt2x00dev = hw->priv;
-+	struct data_queue *queue;
-+	struct rt2x00_field32 field;
-+	int retval;
-+	u32 reg;
-+	u32 offset;
-+
-+	/*
-+	 * First pass the configuration through rt2x00lib, that will
-+	 * update the queue settings and validate the input. After that
-+	 * we are free to update the registers based on the value
-+	 * in the queue parameter.
-+	 */
-+	retval = rt2x00mac_conf_tx(hw, queue_idx, params);
-+	if (retval)
-+		return retval;
-+
-+	/*
-+	 * We only need to perform additional register initialization
-+	 * for WMM queues/
-+	 */
-+	if (queue_idx >= 4)
-+		return 0;
-+
-+	queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
-+
-+	/* Update WMM TXOP register */
-+	offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
-+	field.bit_offset = (queue_idx & 1) * 16;
-+	field.bit_mask = 0xffff << field.bit_offset;
-+
-+	rt2x00usb_register_read(rt2x00dev, offset, &reg);
-+	rt2x00_set_field32(&reg, field, queue->txop);
-+	rt2x00usb_register_write(rt2x00dev, offset, reg);
-+
-+	/* Update WMM registers */
-+	field.bit_offset = queue_idx * 4;
-+	field.bit_mask = 0xf << field.bit_offset;
-+
-+	rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
-+	rt2x00_set_field32(&reg, field, queue->aifs);
-+	rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
-+	rt2x00_set_field32(&reg, field, queue->cw_min);
-+	rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
-+
-+	rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
-+	rt2x00_set_field32(&reg, field, queue->cw_max);
-+	rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
-+
-+	/* Update EDCA registers */
-+	offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
-+
-+	rt2x00usb_register_read(rt2x00dev, offset, &reg);
-+	rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
-+	rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
-+	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
-+	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
-+	rt2x00usb_register_write(rt2x00dev, offset, reg);
-+
-+	return 0;
-+}
-+
-+static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
-+{
-+	struct rt2x00_dev *rt2x00dev = hw->priv;
-+	u64 tsf;
-+	u32 reg;
-+
-+	rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
-+	tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
-+	rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
-+	tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
-+
-+	return tsf;
-+}
-+
-+static const struct ieee80211_ops rt2800usb_mac80211_ops = {
-+	.tx			= rt2x00mac_tx,
-+	.start			= rt2x00mac_start,
-+	.stop			= rt2x00mac_stop,
-+	.add_interface		= rt2x00mac_add_interface,
-+	.remove_interface	= rt2x00mac_remove_interface,
-+	.config			= rt2x00mac_config,
-+	.config_interface	= rt2x00mac_config_interface,
-+	.configure_filter	= rt2x00mac_configure_filter,
-+	.set_key		= rt2x00mac_set_key,
-+	.get_stats		= rt2x00mac_get_stats,
-+	.get_tkip_seq		= rt2800usb_get_tkip_seq,
-+	.set_rts_threshold	= rt2800usb_set_rts_threshold,
-+	.bss_info_changed	= rt2x00mac_bss_info_changed,
-+	.conf_tx		= rt2800usb_conf_tx,
-+	.get_tx_stats		= rt2x00mac_get_tx_stats,
-+	.get_tsf		= rt2800usb_get_tsf,
-+};
-+
-+static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
-+	.probe_hw		= rt2800usb_probe_hw,
-+	.get_firmware_name	= rt2800usb_get_firmware_name,
-+	.check_firmware		= rt2800usb_check_firmware,
-+	.load_firmware		= rt2800usb_load_firmware,
-+	.initialize		= rt2x00usb_initialize,
-+	.uninitialize		= rt2x00usb_uninitialize,
-+	.clear_entry		= rt2x00usb_clear_entry,
-+	.set_device_state	= rt2800usb_set_device_state,
-+	.rfkill_poll		= rt2800usb_rfkill_poll,
-+	.link_stats		= rt2800usb_link_stats,
-+	.reset_tuner		= rt2800usb_reset_tuner,
-+	.link_tuner		= rt2800usb_link_tuner,
-+	.write_tx_desc		= rt2800usb_write_tx_desc,
-+	.write_tx_data		= rt2x00usb_write_tx_data,
-+	.write_beacon		= rt2800usb_write_beacon,
-+	.get_tx_data_len	= rt2800usb_get_tx_data_len,
-+	.kick_tx_queue		= rt2800usb_kick_tx_queue,
-+	.kill_tx_queue		= rt2x00usb_kill_tx_queue,
-+	.fill_rxdone		= rt2800usb_fill_rxdone,
-+	.config_shared_key	= rt2800usb_config_shared_key,
-+	.config_pairwise_key	= rt2800usb_config_pairwise_key,
-+	.config_filter		= rt2800usb_config_filter,
-+	.config_intf		= rt2800usb_config_intf,
-+	.config_erp		= rt2800usb_config_erp,
-+	.config_ant		= rt2800usb_config_ant,
-+	.config			= rt2800usb_config,
-+};
-+
-+static const struct data_queue_desc rt2800usb_queue_rx = {
-+	.entry_num		= RX_ENTRIES,
-+	.data_size		= AGGREGATION_SIZE,
-+	.desc_size		= RXD_DESC_SIZE + RXWI_DESC_SIZE,
-+	.priv_size		= sizeof(struct queue_entry_priv_usb),
-+};
-+
-+static const struct data_queue_desc rt2800usb_queue_tx = {
-+	.entry_num		= TX_ENTRIES,
-+	.data_size		= AGGREGATION_SIZE,
-+	.desc_size		= TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
-+	.priv_size		= sizeof(struct queue_entry_priv_usb),
-+};
-+
-+static const struct data_queue_desc rt2800usb_queue_bcn = {
-+	.entry_num		= 8 * BEACON_ENTRIES,
-+	.data_size		= MGMT_FRAME_SIZE,
-+	.desc_size		= TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
-+	.priv_size		= sizeof(struct queue_entry_priv_usb),
-+};
-+
-+static const struct rt2x00_ops rt2800usb_ops = {
-+	.name		= KBUILD_MODNAME,
-+	.max_sta_intf	= 1,
-+	.max_ap_intf	= 8,
-+	.eeprom_size	= EEPROM_SIZE,
-+	.rf_size	= RF_SIZE,
-+	.tx_queues	= NUM_TX_QUEUES,
-+	.rx		= &rt2800usb_queue_rx,
-+	.tx		= &rt2800usb_queue_tx,
-+	.bcn		= &rt2800usb_queue_bcn,
-+	.lib		= &rt2800usb_rt2x00_ops,
-+	.hw		= &rt2800usb_mac80211_ops,
-+#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-+	.debugfs	= &rt2800usb_rt2x00debug,
-+#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-+};
-+
-+/*
-+ * rt2800usb module information.
-+ */
-+static struct usb_device_id rt2800usb_device_table[] = {
-+	/* Abocom */
-+	{ USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* AirTies */
-+	{ USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Amigo */
-+	{ USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Amit */
-+	{ USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* ASUS */
-+	{ USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* AzureWave */
-+	{ USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Belkin */
-+	{ USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Buffalo */
-+	{ USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Conceptronic */
-+	{ USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Corega */
-+	{ USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* D-Link */
-+	{ USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x2001, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x2001, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Edimax */
-+	{ USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* EnGenius */
-+	{ USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Gemtek */
-+	{ USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Gigabyte */
-+	{ USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Hawking */
-+	{ USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* LevelOne */
-+	{ USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Linksys */
-+	{ USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Logitec */
-+	{ USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Pegatron */
-+	{ USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Philips */
-+	{ USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Planex */
-+	{ USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Qcom */
-+	{ USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Quanta */
-+	{ USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Ralink */
-+	{ USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Samsung */
-+	{ USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Siemens */
-+	{ USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Sitecom */
-+	{ USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* SMC */
-+	{ USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Sparklan */
-+	{ USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* U-Media*/
-+	{ USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* ZCOM */
-+	{ USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Zinwell */
-+	{ USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	/* Zyxel */
-+	{ USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
-+	{ 0, }
-+};
-+
-+MODULE_AUTHOR(DRV_PROJECT);
-+MODULE_VERSION(DRV_VERSION);
-+MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
-+MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
-+MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
-+MODULE_FIRMWARE(FIRMWARE_RT2870);
-+MODULE_LICENSE("GPL");
-+
-+static struct usb_driver rt2800usb_driver = {
-+	.name		= KBUILD_MODNAME,
-+	.id_table	= rt2800usb_device_table,
-+	.probe		= rt2x00usb_probe,
-+	.disconnect	= rt2x00usb_disconnect,
-+	.suspend	= rt2x00usb_suspend,
-+	.resume		= rt2x00usb_resume,
-+};
-+
-+static int __init rt2800usb_init(void)
-+{
-+	return usb_register(&rt2800usb_driver);
-+}
-+
-+static void __exit rt2800usb_exit(void)
-+{
-+	usb_deregister(&rt2800usb_driver);
-+}
-+
-+module_init(rt2800usb_init);
-+module_exit(rt2800usb_exit);
---- /dev/null
-+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
-@@ -0,0 +1,1934 @@
-+/*
-+	Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
-+	<http://rt2x00.serialmonkey.com>
-+
-+	This program is free software; you can redistribute it and/or modify
-+	it under the terms of the GNU General Public License as published by
-+	the Free Software Foundation; either version 2 of the License, or
-+	(at your option) any later version.
-+
-+	This program is distributed in the hope that it will be useful,
-+	but WITHOUT ANY WARRANTY; without even the implied warranty of
-+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+	GNU General Public License for more details.
-+
-+	You should have received a copy of the GNU General Public License
-+	along with this program; if not, write to the
-+	Free Software Foundation, Inc.,
-+	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+/*
-+	Module: rt2800usb
-+	Abstract: Data structures and registers for the rt2800usb module.
-+	Supported chipsets: RT2800U.
-+ */
-+
-+#ifndef RT2800USB_H
-+#define RT2800USB_H
-+
-+/*
-+ * RF chip defines.
-+ *
-+ * RF2820 2.4G 2T3R
-+ * RF2850 2.4G/5G 2T3R
-+ * RF2720 2.4G 1T2R
-+ * RF2750 2.4G/5G 1T2R
-+ * RF3020 2.4G 1T1R
-+ * RF2020 2.4G B/G
-+ */
-+#define RF2820				0x0001
-+#define RF2850				0x0002
-+#define RF2720				0x0003
-+#define RF2750				0x0004
-+#define RF3020				0x0005
-+#define RF2020				0x0006
-+
-+/*
-+ * RT2870 version
-+ */
-+#define RT2860C_VERSION			0x28600100
-+#define RT2860D_VERSION			0x28600101
-+#define RT2880E_VERSION			0x28720200
-+#define RT2883_VERSION			0x28830300
-+#define RT3070_VERSION			0x30700200
-+
-+/*
-+ * Signal information.
-+ * Defaul offset is required for RSSI <-> dBm conversion.
-+ */
-+#define DEFAULT_RSSI_OFFSET		120 /* FIXME */
-+
-+/*
-+ * Register layout information.
-+ */
-+#define CSR_REG_BASE			0x1000
-+#define CSR_REG_SIZE			0x0800
-+#define EEPROM_BASE			0x0000
-+#define EEPROM_SIZE			0x0110
-+#define BBP_BASE			0x0000
-+#define BBP_SIZE			0x0080
-+#define RF_BASE				0x0004
-+#define RF_SIZE				0x0010
-+
-+/*
-+ * Number of TX queues.
-+ */
-+#define NUM_TX_QUEUES			4
-+
-+/*
-+ * USB registers.
-+ */
-+
-+/*
-+ * HOST-MCU shared memory
-+ */
-+#define HOST_CMD_CSR			0x0404
-+#define HOST_CMD_CSR_HOST_COMMAND	FIELD32(0x000000ff)
-+
-+/*
-+ * INT_SOURCE_CSR: Interrupt source register.
-+ * Write one to clear corresponding bit.
-+ * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
-+ */
-+#define INT_SOURCE_CSR			0x0200
-+#define INT_SOURCE_CSR_RXDELAYINT	FIELD32(0x00000001)
-+#define INT_SOURCE_CSR_TXDELAYINT	FIELD32(0x00000002)
-+#define INT_SOURCE_CSR_RX_DONE		FIELD32(0x00000004)
-+#define INT_SOURCE_CSR_AC0_DMA_DONE	FIELD32(0x00000008)
-+#define INT_SOURCE_CSR_AC1_DMA_DONE	FIELD32(0x00000010)
-+#define INT_SOURCE_CSR_AC2_DMA_DONE	FIELD32(0x00000020)
-+#define INT_SOURCE_CSR_AC3_DMA_DONE	FIELD32(0x00000040)
-+#define INT_SOURCE_CSR_HCCA_DMA_DONE	FIELD32(0x00000080)
-+#define INT_SOURCE_CSR_MGMT_DMA_DONE	FIELD32(0x00000100)
-+#define INT_SOURCE_CSR_MCU_COMMAND	FIELD32(0x00000200)
-+#define INT_SOURCE_CSR_RXTX_COHERENT	FIELD32(0x00000400)
-+#define INT_SOURCE_CSR_TBTT		FIELD32(0x00000800)
-+#define INT_SOURCE_CSR_PRE_TBTT		FIELD32(0x00001000)
-+#define INT_SOURCE_CSR_TX_FIFO_STATUS	FIELD32(0x00002000)
-+#define INT_SOURCE_CSR_AUTO_WAKEUP	FIELD32(0x00004000)
-+#define INT_SOURCE_CSR_GPTIMER		FIELD32(0x00008000)
-+#define INT_SOURCE_CSR_RX_COHERENT	FIELD32(0x00010000)
-+#define INT_SOURCE_CSR_TX_COHERENT	FIELD32(0x00020000)
-+
-+/*
-+ * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
-+ */
-+#define INT_MASK_CSR			0x0204
-+#define INT_MASK_CSR_RXDELAYINT		FIELD32(0x00000001)
-+#define INT_MASK_CSR_TXDELAYINT		FIELD32(0x00000002)
-+#define INT_MASK_CSR_RX_DONE		FIELD32(0x00000004)
-+#define INT_MASK_CSR_AC0_DMA_DONE	FIELD32(0x00000008)
-+#define INT_MASK_CSR_AC1_DMA_DONE	FIELD32(0x00000010)
-+#define INT_MASK_CSR_AC2_DMA_DONE	FIELD32(0x00000020)
-+#define INT_MASK_CSR_AC3_DMA_DONE	FIELD32(0x00000040)
-+#define INT_MASK_CSR_HCCA_DMA_DONE	FIELD32(0x00000080)
-+#define INT_MASK_CSR_MGMT_DMA_DONE	FIELD32(0x00000100)
-+#define INT_MASK_CSR_MCU_COMMAND	FIELD32(0x00000200)
-+#define INT_MASK_CSR_RXTX_COHERENT	FIELD32(0x00000400)
-+#define INT_MASK_CSR_TBTT		FIELD32(0x00000800)
-+#define INT_MASK_CSR_PRE_TBTT		FIELD32(0x00001000)
-+#define INT_MASK_CSR_TX_FIFO_STATUS	FIELD32(0x00002000)
-+#define INT_MASK_CSR_AUTO_WAKEUP	FIELD32(0x00004000)
-+#define INT_MASK_CSR_GPTIMER		FIELD32(0x00008000)
-+#define INT_MASK_CSR_RX_COHERENT	FIELD32(0x00010000)
-+#define INT_MASK_CSR_TX_COHERENT	FIELD32(0x00020000)
-+
-+/*
-+ * WPDMA_GLO_CFG
-+ */
-+#define WPDMA_GLO_CFG 			0x0208
-+#define WPDMA_GLO_CFG_ENABLE_TX_DMA	FIELD32(0x00000001)
-+#define WPDMA_GLO_CFG_TX_DMA_BUSY    	FIELD32(0x00000002)
-+#define WPDMA_GLO_CFG_ENABLE_RX_DMA	FIELD32(0x00000004)
-+#define WPDMA_GLO_CFG_RX_DMA_BUSY	FIELD32(0x00000008)
-+#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE	FIELD32(0x00000030)
-+#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE	FIELD32(0x00000040)
-+#define WPDMA_GLO_CFG_BIG_ENDIAN	FIELD32(0x00000080)
-+#define WPDMA_GLO_CFG_RX_HDR_SCATTER	FIELD32(0x0000ff00)
-+#define WPDMA_GLO_CFG_HDR_SEG_LEN	FIELD32(0xffff0000)
-+
-+/*
-+ * WPDMA_RST_IDX
-+ */
-+#define WPDMA_RST_IDX 			0x020c
-+#define WPDMA_RST_IDX_DTX_IDX0		FIELD32(0x00000001)
-+#define WPDMA_RST_IDX_DTX_IDX1		FIELD32(0x00000002)
-+#define WPDMA_RST_IDX_DTX_IDX2		FIELD32(0x00000004)
-+#define WPDMA_RST_IDX_DTX_IDX3		FIELD32(0x00000008)
-+#define WPDMA_RST_IDX_DTX_IDX4		FIELD32(0x00000010)
-+#define WPDMA_RST_IDX_DTX_IDX5		FIELD32(0x00000020)
-+#define WPDMA_RST_IDX_DRX_IDX0		FIELD32(0x00010000)
-+
-+/*
-+ * DELAY_INT_CFG
-+ */
-+#define DELAY_INT_CFG			0x0210
-+#define DELAY_INT_CFG_RXMAX_PTIME	FIELD32(0x000000ff)
-+#define DELAY_INT_CFG_RXMAX_PINT	FIELD32(0x00007f00)
-+#define DELAY_INT_CFG_RXDLY_INT_EN	FIELD32(0x00008000)
-+#define DELAY_INT_CFG_TXMAX_PTIME	FIELD32(0x00ff0000)
-+#define DELAY_INT_CFG_TXMAX_PINT	FIELD32(0x7f000000)
-+#define DELAY_INT_CFG_TXDLY_INT_EN	FIELD32(0x80000000)
-+
-+/*
-+ * WMM_AIFSN_CFG: Aifsn for each EDCA AC
-+ * AIFSN0: AC_BE
-+ * AIFSN1: AC_BK
-+ * AIFSN1: AC_VI
-+ * AIFSN1: AC_VO
-+ */
-+#define WMM_AIFSN_CFG			0x0214
-+#define WMM_AIFSN_CFG_AIFSN0		FIELD32(0x0000000f)
-+#define WMM_AIFSN_CFG_AIFSN1		FIELD32(0x000000f0)
-+#define WMM_AIFSN_CFG_AIFSN2		FIELD32(0x00000f00)
-+#define WMM_AIFSN_CFG_AIFSN3		FIELD32(0x0000f000)
-+
-+/*
-+ * WMM_CWMIN_CSR: CWmin for each EDCA AC
-+ * CWMIN0: AC_BE
-+ * CWMIN1: AC_BK
-+ * CWMIN1: AC_VI
-+ * CWMIN1: AC_VO
-+ */
-+#define WMM_CWMIN_CFG			0x0218
-+#define WMM_CWMIN_CFG_CWMIN0		FIELD32(0x0000000f)
-+#define WMM_CWMIN_CFG_CWMIN1		FIELD32(0x000000f0)
-+#define WMM_CWMIN_CFG_CWMIN2		FIELD32(0x00000f00)
-+#define WMM_CWMIN_CFG_CWMIN3		FIELD32(0x0000f000)
-+
-+/*
-+ * WMM_CWMAX_CSR: CWmax for each EDCA AC
-+ * CWMAX0: AC_BE
-+ * CWMAX1: AC_BK
-+ * CWMAX1: AC_VI
-+ * CWMAX1: AC_VO
-+ */
-+#define WMM_CWMAX_CFG			0x021c
-+#define WMM_CWMAX_CFG_CWMAX0		FIELD32(0x0000000f)
-+#define WMM_CWMAX_CFG_CWMAX1		FIELD32(0x000000f0)
-+#define WMM_CWMAX_CFG_CWMAX2		FIELD32(0x00000f00)
-+#define WMM_CWMAX_CFG_CWMAX3		FIELD32(0x0000f000)
-+
-+/*
-+ * AC_TXOP0: AC_BK/AC_BE TXOP register
-+ * AC0TXOP: AC_BK in unit of 32us
-+ * AC1TXOP: AC_BE in unit of 32us
-+ */
-+#define WMM_TXOP0_CFG			0x0220
-+#define WMM_TXOP0_CFG_AC0TXOP		FIELD32(0x0000ffff)
-+#define WMM_TXOP0_CFG_AC1TXOP		FIELD32(0xffff0000)
-+
-+/*
-+ * AC_TXOP1: AC_VO/AC_VI TXOP register
-+ * AC2TXOP: AC_VI in unit of 32us
-+ * AC3TXOP: AC_VO in unit of 32us
-+ */
-+#define WMM_TXOP1_CFG			0x0224
-+#define WMM_TXOP1_CFG_AC2TXOP		FIELD32(0x0000ffff)
-+#define WMM_TXOP1_CFG_AC3TXOP		FIELD32(0xffff0000)
-+
-+/*
-+ * GPIO_CTRL_CFG:
-+ */
-+#define GPIO_CTRL_CFG			0x0228
-+#define GPIO_CTRL_CFG_BIT0		FIELD32(0x00000001)
-+#define GPIO_CTRL_CFG_BIT1		FIELD32(0x00000002)
-+#define GPIO_CTRL_CFG_BIT2		FIELD32(0x00000004)
-+#define GPIO_CTRL_CFG_BIT3		FIELD32(0x00000008)
-+#define GPIO_CTRL_CFG_BIT4		FIELD32(0x00000010)
-+#define GPIO_CTRL_CFG_BIT5		FIELD32(0x00000020)
-+#define GPIO_CTRL_CFG_BIT6		FIELD32(0x00000040)
-+#define GPIO_CTRL_CFG_BIT7		FIELD32(0x00000080)
-+#define GPIO_CTRL_CFG_BIT8		FIELD32(0x00000100)
-+
-+/*
-+ * MCU_CMD_CFG
-+ */
-+#define MCU_CMD_CFG			0x022c
-+
-+/*
-+ * AC_BK register offsets
-+ */
-+#define TX_BASE_PTR0			0x0230
-+#define TX_MAX_CNT0			0x0234
-+#define TX_CTX_IDX0			0x0238
-+#define TX_DTX_IDX0			0x023c
-+
-+/*
-+ * AC_BE register offsets
-+ */
-+#define TX_BASE_PTR1			0x0240
-+#define TX_MAX_CNT1			0x0244
-+#define TX_CTX_IDX1			0x0248
-+#define TX_DTX_IDX1			0x024c
-+
-+/*
-+ * AC_VI register offsets
-+ */
-+#define TX_BASE_PTR2			0x0250
-+#define TX_MAX_CNT2			0x0254
-+#define TX_CTX_IDX2			0x0258
-+#define TX_DTX_IDX2			0x025c
-+
-+/*
-+ * AC_VO register offsets
-+ */
-+#define TX_BASE_PTR3			0x0260
-+#define TX_MAX_CNT3			0x0264
-+#define TX_CTX_IDX3			0x0268
-+#define TX_DTX_IDX3			0x026c
-+
-+/*
-+ * HCCA register offsets
-+ */
-+#define TX_BASE_PTR4			0x0270
-+#define TX_MAX_CNT4			0x0274
-+#define TX_CTX_IDX4			0x0278
-+#define TX_DTX_IDX4			0x027c
-+
-+/*
-+ * MGMT register offsets
-+ */
-+#define TX_BASE_PTR5			0x0280
-+#define TX_MAX_CNT5			0x0284
-+#define TX_CTX_IDX5			0x0288
-+#define TX_DTX_IDX5			0x028c
-+
-+/*
-+ * RX register offsets
-+ */
-+#define RX_BASE_PTR			0x0290
-+#define RX_MAX_CNT			0x0294
-+#define RX_CRX_IDX			0x0298
-+#define RX_DRX_IDX			0x029c
-+
-+/*
-+ * USB_DMA_CFG
-+ * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
-+ * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
-+ * PHY_CLEAR: phy watch dog enable.
-+ * TX_CLEAR: Clear USB DMA TX path.
-+ * TXOP_HALT: Halt TXOP count down when TX buffer is full.
-+ * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
-+ * RX_BULK_EN: Enable USB DMA Rx.
-+ * TX_BULK_EN: Enable USB DMA Tx.
-+ * EP_OUT_VALID: OUT endpoint data valid.
-+ * RX_BUSY: USB DMA RX FSM busy.
-+ * TX_BUSY: USB DMA TX FSM busy.
-+ */
-+#define USB_DMA_CFG			0x02a0
-+#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT	FIELD32(0x000000ff)
-+#define USB_DMA_CFG_RX_BULK_AGG_LIMIT	FIELD32(0x0000ff00)
-+#define USB_DMA_CFG_PHY_CLEAR		FIELD32(0x00010000)
-+#define USB_DMA_CFG_TX_CLEAR		FIELD32(0x00080000)
-+#define USB_DMA_CFG_TXOP_HALT		FIELD32(0x00100000)
-+#define USB_DMA_CFG_RX_BULK_AGG_EN	FIELD32(0x00200000)
-+#define USB_DMA_CFG_RX_BULK_EN		FIELD32(0x00400000)
-+#define USB_DMA_CFG_TX_BULK_EN		FIELD32(0x00800000)
-+#define USB_DMA_CFG_EP_OUT_VALID	FIELD32(0x3f000000)
-+#define USB_DMA_CFG_RX_BUSY		FIELD32(0x40000000)
-+#define USB_DMA_CFG_TX_BUSY		FIELD32(0x80000000)
-+
-+/*
-+ * USB_CYC_CFG
-+ */
-+#define USB_CYC_CFG			0x02a4
-+#define USB_CYC_CFG_CLOCK_CYCLE		FIELD32(0x000000ff)
-+
-+/*
-+ * PBF_SYS_CTRL
-+ * HOST_RAM_WRITE: enable Host program ram write selection
-+ */
-+#define PBF_SYS_CTRL			0x0400
-+#define PBF_SYS_CTRL_READY		FIELD32(0x00000080)
-+#define PBF_SYS_CTRL_HOST_RAM_WRITE	FIELD32(0x00010000)
-+
-+/*
-+ * PBF registers
-+ * Most are for debug. Driver doesn't touch PBF register.
-+ */
-+#define PBF_CFG				0x0408
-+#define PBF_MAX_PCNT			0x040c
-+#define PBF_CTRL			0x0410
-+#define PBF_INT_STA			0x0414
-+#define PBF_INT_ENA			0x0418
-+
-+/*
-+ * BCN_OFFSET0:
-+ */
-+#define BCN_OFFSET0			0x042c
-+#define BCN_OFFSET0_BCN0		FIELD32(0x000000ff)
-+#define BCN_OFFSET0_BCN1		FIELD32(0x0000ff00)
-+#define BCN_OFFSET0_BCN2		FIELD32(0x00ff0000)
-+#define BCN_OFFSET0_BCN3		FIELD32(0xff000000)
-+
-+/*
-+ * BCN_OFFSET1:
-+ */
-+#define BCN_OFFSET1			0x0430
-+#define BCN_OFFSET1_BCN4		FIELD32(0x000000ff)
-+#define BCN_OFFSET1_BCN5		FIELD32(0x0000ff00)
-+#define BCN_OFFSET1_BCN6		FIELD32(0x00ff0000)
-+#define BCN_OFFSET1_BCN7		FIELD32(0xff000000)
-+
-+/*
-+ * PBF registers
-+ * Most are for debug. Driver doesn't touch PBF register.
-+ */
-+#define TXRXQ_PCNT			0x0438
-+#define PBF_DBG				0x043c
-+
-+/*
-+ * RF registers
-+ */
-+#define	RF_CSR_CFG			0x0500
-+#define RF_CSR_CFG_DATA			FIELD32(0x000000ff)
-+#define RF_CSR_CFG_REGNUM		FIELD32(0x00001f00)
-+#define RF_CSR_CFG_WRITE		FIELD32(0x00010000)
-+#define RF_CSR_CFG_BUSY			FIELD32(0x00020000)
-+
-+/*
-+ * MAC Control/Status Registers(CSR).
-+ * Some values are set in TU, whereas 1 TU == 1024 us.
-+ */
-+
-+/*
-+ * MAC_CSR0: ASIC revision number.
-+ * ASIC_REV: 0
-+ * ASIC_VER: 2870
-+ */
-+#define MAC_CSR0			0x1000
-+#define MAC_CSR0_ASIC_REV		FIELD32(0x0000ffff)
-+#define MAC_CSR0_ASIC_VER		FIELD32(0xffff0000)
-+
-+/*
-+ * MAC_SYS_CTRL:
-+ */
-+#define MAC_SYS_CTRL			0x1004
-+#define MAC_SYS_CTRL_RESET_CSR		FIELD32(0x00000001)
-+#define MAC_SYS_CTRL_RESET_BBP		FIELD32(0x00000002)
-+#define MAC_SYS_CTRL_ENABLE_TX		FIELD32(0x00000004)
-+#define MAC_SYS_CTRL_ENABLE_RX		FIELD32(0x00000008)
-+#define MAC_SYS_CTRL_CONTINUOUS_TX	FIELD32(0x00000010)
-+#define MAC_SYS_CTRL_LOOPBACK		FIELD32(0x00000020)
-+#define MAC_SYS_CTRL_WLAN_HALT		FIELD32(0x00000040)
-+#define MAC_SYS_CTRL_RX_TIMESTAMP	FIELD32(0x00000080)
-+
-+/*
-+ * MAC_ADDR_DW0: STA MAC register 0
-+ */
-+#define MAC_ADDR_DW0			0x1008
-+#define MAC_ADDR_DW0_BYTE0		FIELD32(0x000000ff)
-+#define MAC_ADDR_DW0_BYTE1		FIELD32(0x0000ff00)
-+#define MAC_ADDR_DW0_BYTE2		FIELD32(0x00ff0000)
-+#define MAC_ADDR_DW0_BYTE3		FIELD32(0xff000000)
-+
-+/*
-+ * MAC_ADDR_DW1: STA MAC register 1
-+ * UNICAST_TO_ME_MASK:
-+ * Used to mask off bits from byte 5 of the MAC address
-+ * to determine the UNICAST_TO_ME bit for RX frames.
-+ * The full mask is complemented by BSS_ID_MASK:
-+ *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
-+ */
-+#define MAC_ADDR_DW1			0x100c
-+#define MAC_ADDR_DW1_BYTE4		FIELD32(0x000000ff)
-+#define MAC_ADDR_DW1_BYTE5		FIELD32(0x0000ff00)
-+#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK	FIELD32(0x00ff0000)
-+
-+/*
-+ * MAC_BSSID_DW0: BSSID register 0
-+ */
-+#define MAC_BSSID_DW0			0x1010
-+#define MAC_BSSID_DW0_BYTE0		FIELD32(0x000000ff)
-+#define MAC_BSSID_DW0_BYTE1		FIELD32(0x0000ff00)
-+#define MAC_BSSID_DW0_BYTE2		FIELD32(0x00ff0000)
-+#define MAC_BSSID_DW0_BYTE3		FIELD32(0xff000000)
-+
-+/*
-+ * MAC_BSSID_DW1: BSSID register 1
-+ * BSS_ID_MASK:
-+ *     0: 1-BSSID mode (BSS index = 0)
-+ *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
-+ *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
-+ *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
-+ * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
-+ * BSSID. This will make sure that those bits will be ignored
-+ * when determining the MY_BSS of RX frames.
-+ */
-+#define MAC_BSSID_DW1			0x1014
-+#define MAC_BSSID_DW1_BYTE4		FIELD32(0x000000ff)
-+#define MAC_BSSID_DW1_BYTE5		FIELD32(0x0000ff00)
-+#define MAC_BSSID_DW1_BSS_ID_MASK	FIELD32(0x00030000)
-+#define MAC_BSSID_DW1_BSS_BCN_NUM	FIELD32(0x001c0000)
-+
-+/*
-+ * MAX_LEN_CFG: Maximum frame length register.
-+ * MAX_MPDU: rt2860b max 16k bytes
-+ * MAX_PSDU: Maximum PSDU length
-+ *	(power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
-+ */
-+#define MAX_LEN_CFG			0x1018
-+#define MAX_LEN_CFG_MAX_MPDU		FIELD32(0x00000fff)
-+#define MAX_LEN_CFG_MAX_PSDU		FIELD32(0x00003000)
-+#define MAX_LEN_CFG_MIN_PSDU		FIELD32(0x0000c000)
-+#define MAX_LEN_CFG_MIN_MPDU		FIELD32(0x000f0000)
-+
-+/*
-+ * BBP_CSR_CFG: BBP serial control register
-+ * VALUE: Register value to program into BBP
-+ * REG_NUM: Selected BBP register
-+ * READ_CONTROL: 0 write BBP, 1 read BBP
-+ * BUSY: ASIC is busy executing BBP commands
-+ * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
-+ * BBP_RW_MODE: 0 serial, 1 paralell
-+ */
-+#define BBP_CSR_CFG			0x101c
-+#define BBP_CSR_CFG_VALUE		FIELD32(0x000000ff)
-+#define BBP_CSR_CFG_REGNUM		FIELD32(0x0000ff00)
-+#define BBP_CSR_CFG_READ_CONTROL	FIELD32(0x00010000)
-+#define BBP_CSR_CFG_BUSY		FIELD32(0x00020000)
-+#define BBP_CSR_CFG_BBP_PAR_DUR		FIELD32(0x00040000)
-+#define BBP_CSR_CFG_BBP_RW_MODE		FIELD32(0x00080000)
-+
-+/*
-+ * RF_CSR_CFG0: RF control register
-+ * REGID_AND_VALUE: Register value to program into RF
-+ * BITWIDTH: Selected RF register
-+ * STANDBYMODE: 0 high when standby, 1 low when standby
-+ * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
-+ * BUSY: ASIC is busy executing RF commands
-+ */
-+#define RF_CSR_CFG0			0x1020
-+#define RF_CSR_CFG0_REGID_AND_VALUE	FIELD32(0x00ffffff)
-+#define RF_CSR_CFG0_BITWIDTH		FIELD32(0x1f000000)
-+#define RF_CSR_CFG0_REG_VALUE_BW	FIELD32(0x1fffffff)
-+#define RF_CSR_CFG0_STANDBYMODE		FIELD32(0x20000000)
-+#define RF_CSR_CFG0_SEL			FIELD32(0x40000000)
-+#define RF_CSR_CFG0_BUSY		FIELD32(0x80000000)
-+
-+/*
-+ * RF_CSR_CFG1: RF control register
-+ * REGID_AND_VALUE: Register value to program into RF
-+ * RFGAP: Gap between BB_CONTROL_RF and RF_LE
-+ *        0: 3 system clock cycle (37.5usec)
-+ *        1: 5 system clock cycle (62.5usec)
-+ */
-+#define RF_CSR_CFG1			0x1024
-+#define RF_CSR_CFG1_REGID_AND_VALUE	FIELD32(0x00ffffff)
-+#define RF_CSR_CFG1_RFGAP		FIELD32(0x1f000000)
-+
-+/*
-+ * RF_CSR_CFG2: RF control register
-+ * VALUE: Register value to program into RF
-+ * RFGAP: Gap between BB_CONTROL_RF and RF_LE
-+ *        0: 3 system clock cycle (37.5usec)
-+ *        1: 5 system clock cycle (62.5usec)
-+ */
-+#define RF_CSR_CFG2			0x1028
-+#define RF_CSR_CFG2_VALUE		FIELD32(0x00ffffff)
-+
-+/*
-+ * LED_CFG: LED control
-+ * color LED's:
-+ *   0: off
-+ *   1: blinking upon TX2
-+ *   2: periodic slow blinking
-+ *   3: always on
-+ * LED polarity:
-+ *   0: active low
-+ *   1: active high
-+ */
-+#define LED_CFG				0x102c
-+#define LED_CFG_ON_PERIOD		FIELD32(0x000000ff)
-+#define LED_CFG_OFF_PERIOD		FIELD32(0x0000ff00)
-+#define LED_CFG_SLOW_BLINK_PERIOD	FIELD32(0x003f0000)
-+#define LED_CFG_R_LED_MODE		FIELD32(0x03000000)
-+#define LED_CFG_G_LED_MODE		FIELD32(0x0c000000)
-+#define LED_CFG_Y_LED_MODE		FIELD32(0x30000000)
-+#define LED_CFG_LED_POLAR		FIELD32(0x40000000)
-+
-+/*
-+ * XIFS_TIME_CFG: MAC timing
-+ * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
-+ * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
-+ * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
-+ *	when MAC doesn't reference BBP signal BBRXEND
-+ * EIFS: unit 1us
-+ * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
-+ *
-+ */
-+#define XIFS_TIME_CFG			0x1100
-+#define XIFS_TIME_CFG_CCKM_SIFS_TIME	FIELD32(0x000000ff)
-+#define XIFS_TIME_CFG_OFDM_SIFS_TIME	FIELD32(0x0000ff00)
-+#define XIFS_TIME_CFG_OFDM_XIFS_TIME	FIELD32(0x000f0000)
-+#define XIFS_TIME_CFG_EIFS		FIELD32(0x1ff00000)
-+#define XIFS_TIME_CFG_BB_RXEND_ENABLE	FIELD32(0x20000000)
-+
-+/*
-+ * BKOFF_SLOT_CFG:
-+ */
-+#define BKOFF_SLOT_CFG			0x1104
-+#define BKOFF_SLOT_CFG_SLOT_TIME	FIELD32(0x000000ff)
-+#define BKOFF_SLOT_CFG_CC_DELAY_TIME	FIELD32(0x0000ff00)
-+
-+/*
-+ * NAV_TIME_CFG:
-+ */
-+#define NAV_TIME_CFG			0x1108
-+#define NAV_TIME_CFG_SIFS		FIELD32(0x000000ff)
-+#define NAV_TIME_CFG_SLOT_TIME		FIELD32(0x0000ff00)
-+#define NAV_TIME_CFG_EIFS		FIELD32(0x01ff0000)
-+#define NAV_TIME_ZERO_SIFS		FIELD32(0x02000000)
-+
-+/*
-+ * CH_TIME_CFG: count as channel busy
-+ */
-+#define CH_TIME_CFG     	        0x110c
-+
-+/*
-+ * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
-+ */
-+#define PBF_LIFE_TIMER     	        0x1110
-+
-+/*
-+ * BCN_TIME_CFG:
-+ * BEACON_INTERVAL: in unit of 1/16 TU
-+ * TSF_TICKING: Enable TSF auto counting
-+ * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
-+ * BEACON_GEN: Enable beacon generator
-+ */
-+#define BCN_TIME_CFG			0x1114
-+#define BCN_TIME_CFG_BEACON_INTERVAL	FIELD32(0x0000ffff)
-+#define BCN_TIME_CFG_TSF_TICKING	FIELD32(0x00010000)
-+#define BCN_TIME_CFG_TSF_SYNC		FIELD32(0x00060000)
-+#define BCN_TIME_CFG_TBTT_ENABLE	FIELD32(0x00080000)
-+#define BCN_TIME_CFG_BEACON_GEN		FIELD32(0x00100000)
-+#define BCN_TIME_CFG_TX_TIME_COMPENSATE	FIELD32(0xf0000000)
-+
-+/*
-+ * TBTT_SYNC_CFG:
-+ */
-+#define TBTT_SYNC_CFG			0x1118
-+
-+/*
-+ * TSF_TIMER_DW0: Local lsb TSF timer, read-only
-+ */
-+#define TSF_TIMER_DW0			0x111c
-+#define TSF_TIMER_DW0_LOW_WORD		FIELD32(0xffffffff)
-+
-+/*
-+ * TSF_TIMER_DW1: Local msb TSF timer, read-only
-+ */
-+#define TSF_TIMER_DW1			0x1120
-+#define TSF_TIMER_DW1_HIGH_WORD		FIELD32(0xffffffff)
-+
-+/*
-+ * TBTT_TIMER: TImer remains till next TBTT, read-only
-+ */
-+#define TBTT_TIMER			0x1124
-+
-+/*
-+ * INT_TIMER_CFG:
-+ */
-+#define INT_TIMER_CFG			0x1128
-+
-+/*
-+ * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
-+ */
-+#define INT_TIMER_EN			0x112c
-+
-+/*
-+ * CH_IDLE_STA: channel idle time
-+ */
-+#define CH_IDLE_STA			0x1130
-+
-+/*
-+ * CH_BUSY_STA: channel busy time
-+ */
-+#define CH_BUSY_STA			0x1134
-+
-+/*
-+ * MAC_STATUS_CFG:
-+ * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
-+ *	if 1 or higher one of the 2 registers is busy.
-+ */
-+#define MAC_STATUS_CFG			0x1200
-+#define MAC_STATUS_CFG_BBP_RF_BUSY	FIELD32(0x00000003)
-+
-+/*
-+ * PWR_PIN_CFG:
-+ */
-+#define PWR_PIN_CFG			0x1204
-+
-+/*
-+ * AUTOWAKEUP_CFG: Manual power control / status register
-+ * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
-+ * AUTOWAKE: 0:sleep, 1:awake
-+ */
-+#define AUTOWAKEUP_CFG			0x1208
-+#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME	FIELD32(0x000000ff)
-+#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE	FIELD32(0x00007f00)
-+#define AUTOWAKEUP_CFG_AUTOWAKE		FIELD32(0x00008000)
-+
-+/*
-+ * EDCA_AC0_CFG:
-+ */
-+#define EDCA_AC0_CFG			0x1300
-+#define EDCA_AC0_CFG_TX_OP		FIELD32(0x000000ff)
-+#define EDCA_AC0_CFG_AIFSN		FIELD32(0x00000f00)
-+#define EDCA_AC0_CFG_CWMIN		FIELD32(0x0000f000)
-+#define EDCA_AC0_CFG_CWMAX		FIELD32(0x000f0000)
-+
-+/*
-+ * EDCA_AC1_CFG:
-+ */
-+#define EDCA_AC1_CFG			0x1304
-+#define EDCA_AC1_CFG_TX_OP		FIELD32(0x000000ff)
-+#define EDCA_AC1_CFG_AIFSN		FIELD32(0x00000f00)
-+#define EDCA_AC1_CFG_CWMIN		FIELD32(0x0000f000)
-+#define EDCA_AC1_CFG_CWMAX		FIELD32(0x000f0000)
-+
-+/*
-+ * EDCA_AC2_CFG:
-+ */
-+#define EDCA_AC2_CFG			0x1308
-+#define EDCA_AC2_CFG_TX_OP		FIELD32(0x000000ff)
-+#define EDCA_AC2_CFG_AIFSN		FIELD32(0x00000f00)
-+#define EDCA_AC2_CFG_CWMIN		FIELD32(0x0000f000)
-+#define EDCA_AC2_CFG_CWMAX		FIELD32(0x000f0000)
-+
-+/*
-+ * EDCA_AC3_CFG:
-+ */
-+#define EDCA_AC3_CFG			0x130c
-+#define EDCA_AC3_CFG_TX_OP		FIELD32(0x000000ff)
-+#define EDCA_AC3_CFG_AIFSN		FIELD32(0x00000f00)
-+#define EDCA_AC3_CFG_CWMIN		FIELD32(0x0000f000)
-+#define EDCA_AC3_CFG_CWMAX		FIELD32(0x000f0000)
-+
-+/*
-+ * EDCA_TID_AC_MAP:
-+ */
-+#define EDCA_TID_AC_MAP			0x1310
-+
-+/*
-+ * TX_PWR_CFG_0:
-+ */
-+#define TX_PWR_CFG_0			0x1314
-+#define TX_PWR_CFG_0_1MBS		FIELD32(0x0000000f)
-+#define TX_PWR_CFG_0_2MBS		FIELD32(0x000000f0)
-+#define TX_PWR_CFG_0_55MBS		FIELD32(0x00000f00)
-+#define TX_PWR_CFG_0_11MBS		FIELD32(0x0000f000)
-+#define TX_PWR_CFG_0_6MBS		FIELD32(0x000f0000)
-+#define TX_PWR_CFG_0_9MBS		FIELD32(0x00f00000)
-+#define TX_PWR_CFG_0_12MBS		FIELD32(0x0f000000)
-+#define TX_PWR_CFG_0_18MBS		FIELD32(0xf0000000)
-+
-+/*
-+ * TX_PWR_CFG_1:
-+ */
-+#define TX_PWR_CFG_1			0x1318
-+#define TX_PWR_CFG_1_24MBS		FIELD32(0x0000000f)
-+#define TX_PWR_CFG_1_36MBS		FIELD32(0x000000f0)
-+#define TX_PWR_CFG_1_48MBS		FIELD32(0x00000f00)
-+#define TX_PWR_CFG_1_54MBS		FIELD32(0x0000f000)
-+#define TX_PWR_CFG_1_MCS0		FIELD32(0x000f0000)
-+#define TX_PWR_CFG_1_MCS1		FIELD32(0x00f00000)
-+#define TX_PWR_CFG_1_MCS2		FIELD32(0x0f000000)
-+#define TX_PWR_CFG_1_MCS3		FIELD32(0xf0000000)
-+
-+/*
-+ * TX_PWR_CFG_2:
-+ */
-+#define TX_PWR_CFG_2			0x131c
-+#define TX_PWR_CFG_2_MCS4		FIELD32(0x0000000f)
-+#define TX_PWR_CFG_2_MCS5		FIELD32(0x000000f0)
-+#define TX_PWR_CFG_2_MCS6		FIELD32(0x00000f00)
-+#define TX_PWR_CFG_2_MCS7		FIELD32(0x0000f000)
-+#define TX_PWR_CFG_2_MCS8		FIELD32(0x000f0000)
-+#define TX_PWR_CFG_2_MCS9		FIELD32(0x00f00000)
-+#define TX_PWR_CFG_2_MCS10		FIELD32(0x0f000000)
-+#define TX_PWR_CFG_2_MCS11		FIELD32(0xf0000000)
-+
-+/*
-+ * TX_PWR_CFG_3:
-+ */
-+#define TX_PWR_CFG_3			0x1320
-+#define TX_PWR_CFG_3_MCS12		FIELD32(0x0000000f)
-+#define TX_PWR_CFG_3_MCS13		FIELD32(0x000000f0)
-+#define TX_PWR_CFG_3_MCS14		FIELD32(0x00000f00)
-+#define TX_PWR_CFG_3_MCS15		FIELD32(0x0000f000)
-+#define TX_PWR_CFG_3_UKNOWN1		FIELD32(0x000f0000)
-+#define TX_PWR_CFG_3_UKNOWN2		FIELD32(0x00f00000)
-+#define TX_PWR_CFG_3_UKNOWN3		FIELD32(0x0f000000)
-+#define TX_PWR_CFG_3_UKNOWN4		FIELD32(0xf0000000)
-+
-+/*
-+ * TX_PWR_CFG_4:
-+ */
-+#define TX_PWR_CFG_4			0x1324
-+#define TX_PWR_CFG_4_UKNOWN5		FIELD32(0x0000000f)
-+#define TX_PWR_CFG_4_UKNOWN6		FIELD32(0x000000f0)
-+#define TX_PWR_CFG_4_UKNOWN7		FIELD32(0x00000f00)
-+#define TX_PWR_CFG_4_UKNOWN8		FIELD32(0x0000f000)
-+
-+/*
-+ * TX_PIN_CFG:
-+ */
-+#define TX_PIN_CFG			0x1328
-+#define TX_PIN_CFG_PA_PE_A0_EN		FIELD32(0x00000001)
-+#define TX_PIN_CFG_PA_PE_G0_EN		FIELD32(0x00000002)
-+#define TX_PIN_CFG_PA_PE_A1_EN		FIELD32(0x00000004)
-+#define TX_PIN_CFG_PA_PE_G1_EN		FIELD32(0x00000008)
-+#define TX_PIN_CFG_PA_PE_A0_POL		FIELD32(0x00000010)
-+#define TX_PIN_CFG_PA_PE_G0_POL		FIELD32(0x00000020)
-+#define TX_PIN_CFG_PA_PE_A1_POL		FIELD32(0x00000040)
-+#define TX_PIN_CFG_PA_PE_G1_POL		FIELD32(0x00000080)
-+#define TX_PIN_CFG_LNA_PE_A0_EN		FIELD32(0x00000100)
-+#define TX_PIN_CFG_LNA_PE_G0_EN		FIELD32(0x00000200)
-+#define TX_PIN_CFG_LNA_PE_A1_EN		FIELD32(0x00000400)
-+#define TX_PIN_CFG_LNA_PE_G1_EN		FIELD32(0x00000800)
-+#define TX_PIN_CFG_LNA_PE_A0_POL	FIELD32(0x00001000)
-+#define TX_PIN_CFG_LNA_PE_G0_POL	FIELD32(0x00002000)
-+#define TX_PIN_CFG_LNA_PE_A1_POL	FIELD32(0x00004000)
-+#define TX_PIN_CFG_LNA_PE_G1_POL	FIELD32(0x00008000)
-+#define TX_PIN_CFG_RFTR_EN		FIELD32(0x00010000)
-+#define TX_PIN_CFG_RFTR_POL		FIELD32(0x00020000)
-+#define TX_PIN_CFG_TRSW_EN		FIELD32(0x00040000)
-+#define TX_PIN_CFG_TRSW_POL		FIELD32(0x00080000)
-+
-+/*
-+ * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
-+ */
-+#define TX_BAND_CFG			0x132c
-+#define TX_BAND_CFG_HT40_PLUS		FIELD32(0x00000001)
-+#define TX_BAND_CFG_A			FIELD32(0x00000002)
-+#define TX_BAND_CFG_BG			FIELD32(0x00000004)
-+
-+/*
-+ * TX_SW_CFG0:
-+ */
-+#define TX_SW_CFG0			0x1330
-+
-+/*
-+ * TX_SW_CFG1:
-+ */
-+#define TX_SW_CFG1			0x1334
-+
-+/*
-+ * TX_SW_CFG2:
-+ */
-+#define TX_SW_CFG2			0x1338
-+
-+/*
-+ * TXOP_THRES_CFG:
-+ */
-+#define TXOP_THRES_CFG			0x133c
-+
-+/*
-+ * TXOP_CTRL_CFG:
-+ */
-+#define TXOP_CTRL_CFG			0x1340
-+
-+/*
-+ * TX_RTS_CFG:
-+ * RTS_THRES: unit:byte
-+ * RTS_FBK_EN: enable rts rate fallback
-+ */
-+#define TX_RTS_CFG			0x1344
-+#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT	FIELD32(0x000000ff)
-+#define TX_RTS_CFG_RTS_THRES		FIELD32(0x00ffff00)
-+#define TX_RTS_CFG_RTS_FBK_EN		FIELD32(0x01000000)
-+
-+/*
-+ * TX_TIMEOUT_CFG:
-+ * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
-+ * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
-+ * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
-+ *                it is recommended that:
-+ *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
-+ */
-+#define TX_TIMEOUT_CFG			0x1348
-+#define TX_TIMEOUT_CFG_MPDU_LIFETIME	FIELD32(0x000000f0)
-+#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT	FIELD32(0x0000ff00)
-+#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT	FIELD32(0x00ff0000)
-+
-+/*
-+ * TX_RTY_CFG:
-+ * SHORT_RTY_LIMIT: short retry limit
-+ * LONG_RTY_LIMIT: long retry limit
-+ * LONG_RTY_THRE: Long retry threshoold
-+ * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
-+ *                   0:expired by retry limit, 1: expired by mpdu life timer
-+ * AGG_RTY_MODE: Aggregate MPDU retry mode
-+ *               0:expired by retry limit, 1: expired by mpdu life timer
-+ * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
-+ */
-+#define TX_RTY_CFG			0x134c
-+#define TX_RTY_CFG_SHORT_RTY_LIMIT	FIELD32(0x000000ff)
-+#define TX_RTY_CFG_LONG_RTY_LIMIT	FIELD32(0x0000ff00)
-+#define TX_RTY_CFG_LONG_RTY_THRE	FIELD32(0x0fff0000)
-+#define TX_RTY_CFG_NON_AGG_RTY_MODE	FIELD32(0x10000000)
-+#define TX_RTY_CFG_AGG_RTY_MODE		FIELD32(0x20000000)
-+#define TX_RTY_CFG_TX_AUTO_FB_ENABLE	FIELD32(0x40000000)
-+
-+/*
-+ * TX_LINK_CFG:
-+ * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
-+ * MFB_ENABLE: TX apply remote MFB 1:enable
-+ * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
-+ *                     0: not apply remote remote unsolicit (MFS=7)
-+ * TX_MRQ_EN: MCS request TX enable
-+ * TX_RDG_EN: RDG TX enable
-+ * TX_CF_ACK_EN: Piggyback CF-ACK enable
-+ * REMOTE_MFB: remote MCS feedback
-+ * REMOTE_MFS: remote MCS feedback sequence number
-+ */
-+#define TX_LINK_CFG			0x1350
-+#define TX_LINK_CFG_REMOTE_MFB_LIFETIME	FIELD32(0x000000ff)
-+#define TX_LINK_CFG_MFB_ENABLE		FIELD32(0x00000100)
-+#define TX_LINK_CFG_REMOTE_UMFS_ENABLE	FIELD32(0x00000200)
-+#define TX_LINK_CFG_TX_MRQ_EN		FIELD32(0x00000400)
-+#define TX_LINK_CFG_TX_RDG_EN		FIELD32(0x00000800)
-+#define TX_LINK_CFG_TX_CF_ACK_EN	FIELD32(0x00001000)
-+#define TX_LINK_CFG_REMOTE_MFB		FIELD32(0x00ff0000)
-+#define TX_LINK_CFG_REMOTE_MFS		FIELD32(0xff000000)
-+
-+/*
-+ * HT_FBK_CFG0:
-+ */
-+#define HT_FBK_CFG0			0x1354
-+#define HT_FBK_CFG0_HTMCS0FBK		FIELD32(0x0000000f)
-+#define HT_FBK_CFG0_HTMCS1FBK		FIELD32(0x000000f0)
-+#define HT_FBK_CFG0_HTMCS2FBK		FIELD32(0x00000f00)
-+#define HT_FBK_CFG0_HTMCS3FBK		FIELD32(0x0000f000)
-+#define HT_FBK_CFG0_HTMCS4FBK		FIELD32(0x000f0000)
-+#define HT_FBK_CFG0_HTMCS5FBK		FIELD32(0x00f00000)
-+#define HT_FBK_CFG0_HTMCS6FBK		FIELD32(0x0f000000)
-+#define HT_FBK_CFG0_HTMCS7FBK		FIELD32(0xf0000000)
-+
-+/*
-+ * HT_FBK_CFG1:
-+ */
-+#define HT_FBK_CFG1			0x1358
-+#define HT_FBK_CFG1_HTMCS8FBK		FIELD32(0x0000000f)
-+#define HT_FBK_CFG1_HTMCS9FBK		FIELD32(0x000000f0)
-+#define HT_FBK_CFG1_HTMCS10FBK		FIELD32(0x00000f00)
-+#define HT_FBK_CFG1_HTMCS11FBK		FIELD32(0x0000f000)
-+#define HT_FBK_CFG1_HTMCS12FBK		FIELD32(0x000f0000)
-+#define HT_FBK_CFG1_HTMCS13FBK		FIELD32(0x00f00000)
-+#define HT_FBK_CFG1_HTMCS14FBK		FIELD32(0x0f000000)
-+#define HT_FBK_CFG1_HTMCS15FBK		FIELD32(0xf0000000)
-+
-+/*
-+ * LG_FBK_CFG0:
-+ */
-+#define LG_FBK_CFG0			0x135c
-+#define LG_FBK_CFG0_OFDMMCS0FBK		FIELD32(0x0000000f)
-+#define LG_FBK_CFG0_OFDMMCS1FBK		FIELD32(0x000000f0)
-+#define LG_FBK_CFG0_OFDMMCS2FBK		FIELD32(0x00000f00)
-+#define LG_FBK_CFG0_OFDMMCS3FBK		FIELD32(0x0000f000)
-+#define LG_FBK_CFG0_OFDMMCS4FBK		FIELD32(0x000f0000)
-+#define LG_FBK_CFG0_OFDMMCS5FBK		FIELD32(0x00f00000)
-+#define LG_FBK_CFG0_OFDMMCS6FBK		FIELD32(0x0f000000)
-+#define LG_FBK_CFG0_OFDMMCS7FBK		FIELD32(0xf0000000)
-+
-+/*
-+ * LG_FBK_CFG1:
-+ */
-+#define LG_FBK_CFG1			0x1360
-+#define LG_FBK_CFG0_CCKMCS0FBK		FIELD32(0x0000000f)
-+#define LG_FBK_CFG0_CCKMCS1FBK		FIELD32(0x000000f0)
-+#define LG_FBK_CFG0_CCKMCS2FBK		FIELD32(0x00000f00)
-+#define LG_FBK_CFG0_CCKMCS3FBK		FIELD32(0x0000f000)
-+
-+/*
-+ * CCK_PROT_CFG: CCK Protection
-+ * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
-+ * PROTECT_CTRL: Protection control frame type for CCK TX
-+ *               0:none, 1:RTS/CTS, 2:CTS-to-self
-+ * PROTECT_NAV: TXOP protection type for CCK TX
-+ *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
-+ * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
-+ * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
-+ * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
-+ * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
-+ * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
-+ * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
-+ * RTS_TH_EN: RTS threshold enable on CCK TX
-+ */
-+#define CCK_PROT_CFG			0x1364
-+#define CCK_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)
-+#define CCK_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)
-+#define CCK_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)
-+#define CCK_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)
-+#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)
-+#define CCK_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
-+#define CCK_PROT_CFG_TX_OP_ALLOW_MM40	FIELD32(0x00800000)
-+#define CCK_PROT_CFG_TX_OP_ALLOW_GF20	FIELD32(0x01000000)
-+#define CCK_PROT_CFG_TX_OP_ALLOW_GF40	FIELD32(0x02000000)
-+#define CCK_PROT_CFG_RTS_TH_EN		FIELD32(0x04000000)
-+
-+/*
-+ * OFDM_PROT_CFG: OFDM Protection
-+ */
-+#define OFDM_PROT_CFG			0x1368
-+#define OFDM_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)
-+#define OFDM_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)
-+#define OFDM_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40	FIELD32(0x00800000)
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20	FIELD32(0x01000000)
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40	FIELD32(0x02000000)
-+#define OFDM_PROT_CFG_RTS_TH_EN		FIELD32(0x04000000)
-+
-+/*
-+ * MM20_PROT_CFG: MM20 Protection
-+ */
-+#define MM20_PROT_CFG			0x136c
-+#define MM20_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)
-+#define MM20_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)
-+#define MM20_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)
-+#define MM20_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)
-+#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)
-+#define MM20_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
-+#define MM20_PROT_CFG_TX_OP_ALLOW_MM40	FIELD32(0x00800000)
-+#define MM20_PROT_CFG_TX_OP_ALLOW_GF20	FIELD32(0x01000000)
-+#define MM20_PROT_CFG_TX_OP_ALLOW_GF40	FIELD32(0x02000000)
-+#define MM20_PROT_CFG_RTS_TH_EN		FIELD32(0x04000000)
-+
-+/*
-+ * MM40_PROT_CFG: MM40 Protection
-+ */
-+#define MM40_PROT_CFG			0x1370
-+#define MM40_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)
-+#define MM40_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)
-+#define MM40_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)
-+#define MM40_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)
-+#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)
-+#define MM40_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
-+#define MM40_PROT_CFG_TX_OP_ALLOW_MM40	FIELD32(0x00800000)
-+#define MM40_PROT_CFG_TX_OP_ALLOW_GF20	FIELD32(0x01000000)
-+#define MM40_PROT_CFG_TX_OP_ALLOW_GF40	FIELD32(0x02000000)
-+#define MM40_PROT_CFG_RTS_TH_EN		FIELD32(0x04000000)
-+
-+/*
-+ * GF20_PROT_CFG: GF20 Protection
-+ */
-+#define GF20_PROT_CFG			0x1374
-+#define GF20_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)
-+#define GF20_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)
-+#define GF20_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)
-+#define GF20_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)
-+#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)
-+#define GF20_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
-+#define GF20_PROT_CFG_TX_OP_ALLOW_MM40	FIELD32(0x00800000)
-+#define GF20_PROT_CFG_TX_OP_ALLOW_GF20	FIELD32(0x01000000)
-+#define GF20_PROT_CFG_TX_OP_ALLOW_GF40	FIELD32(0x02000000)
-+#define GF20_PROT_CFG_RTS_TH_EN		FIELD32(0x04000000)
-+
-+/*
-+ * GF40_PROT_CFG: GF40 Protection
-+ */
-+#define GF40_PROT_CFG			0x1378
-+#define GF40_PROT_CFG_PROTECT_RATE	FIELD32(0x0000ffff)
-+#define GF40_PROT_CFG_PROTECT_CTRL	FIELD32(0x00030000)
-+#define GF40_PROT_CFG_PROTECT_NAV	FIELD32(0x000c0000)
-+#define GF40_PROT_CFG_TX_OP_ALLOW_CCK	FIELD32(0x00100000)
-+#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM	FIELD32(0x00200000)
-+#define GF40_PROT_CFG_TX_OP_ALLOW_MM20	FIELD32(0x00400000)
-+#define GF40_PROT_CFG_TX_OP_ALLOW_MM40	FIELD32(0x00800000)
-+#define GF40_PROT_CFG_TX_OP_ALLOW_GF20	FIELD32(0x01000000)
-+#define GF40_PROT_CFG_TX_OP_ALLOW_GF40	FIELD32(0x02000000)
-+#define GF40_PROT_CFG_RTS_TH_EN		FIELD32(0x04000000)
-+
-+/*
-+ * EXP_CTS_TIME:
-+ */
-+#define EXP_CTS_TIME			0x137c
-+
-+/*
-+ * EXP_ACK_TIME:
-+ */
-+#define EXP_ACK_TIME			0x1380
-+
-+/*
-+ * RX_FILTER_CFG: RX configuration register.
-+ */
-+#define RX_FILTER_CFG			0x1400
-+#define RX_FILTER_CFG_DROP_CRC_ERROR	FIELD32(0x00000001)
-+#define RX_FILTER_CFG_DROP_PHY_ERROR	FIELD32(0x00000002)
-+#define RX_FILTER_CFG_DROP_NOT_TO_ME	FIELD32(0x00000004)
-+#define RX_FILTER_CFG_DROP_NOT_MY_BSSD	FIELD32(0x00000008)
-+#define RX_FILTER_CFG_DROP_VER_ERROR	FIELD32(0x00000010)
-+#define RX_FILTER_CFG_DROP_MULTICAST	FIELD32(0x00000020)
-+#define RX_FILTER_CFG_DROP_BROADCAST	FIELD32(0x00000040)
-+#define RX_FILTER_CFG_DROP_DUPLICATE	FIELD32(0x00000080)
-+#define RX_FILTER_CFG_DROP_CF_END_ACK	FIELD32(0x00000100)
-+#define RX_FILTER_CFG_DROP_CF_END	FIELD32(0x00000200)
-+#define RX_FILTER_CFG_DROP_ACK		FIELD32(0x00000400)
-+#define RX_FILTER_CFG_DROP_CTS		FIELD32(0x00000800)
-+#define RX_FILTER_CFG_DROP_RTS		FIELD32(0x00001000)
-+#define RX_FILTER_CFG_DROP_PSPOLL	FIELD32(0x00002000)
-+#define RX_FILTER_CFG_DROP_BA		FIELD32(0x00004000)
-+#define RX_FILTER_CFG_DROP_BAR		FIELD32(0x00008000)
-+#define RX_FILTER_CFG_DROP_CNTL		FIELD32(0x00010000)
-+
-+/*
-+ * AUTO_RSP_CFG:
-+ * AUTORESPONDER: 0: disable, 1: enable
-+ * BAC_ACK_POLICY: 0:long, 1:short preamble
-+ * CTS_40_MMODE: Response CTS 40MHz duplicate mode
-+ * CTS_40_MREF: Response CTS 40MHz duplicate mode
-+ * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
-+ * DUAL_CTS_EN: Power bit value in control frame
-+ * ACK_CTS_PSM_BIT:Power bit value in control frame
-+ */
-+#define AUTO_RSP_CFG			0x1404
-+#define AUTO_RSP_CFG_AUTORESPONDER	FIELD32(0x00000001)
-+#define AUTO_RSP_CFG_BAC_ACK_POLICY	FIELD32(0x00000002)
-+#define AUTO_RSP_CFG_CTS_40_MMODE	FIELD32(0x00000004)
-+#define AUTO_RSP_CFG_CTS_40_MREF	FIELD32(0x00000008)
-+#define AUTO_RSP_CFG_AR_PREAMBLE	FIELD32(0x00000010)
-+#define AUTO_RSP_CFG_DUAL_CTS_EN	FIELD32(0x00000040)
-+#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT	FIELD32(0x00000080)
-+
-+/*
-+ * LEGACY_BASIC_RATE:
-+ */
-+#define LEGACY_BASIC_RATE		0x1408
-+
-+/*
-+ * HT_BASIC_RATE:
-+ */
-+#define HT_BASIC_RATE			0x140c
-+
-+/*
-+ * HT_CTRL_CFG:
-+ */
-+#define HT_CTRL_CFG			0x1410
-+
-+/*
-+ * SIFS_COST_CFG:
-+ */
-+#define SIFS_COST_CFG			0x1414
-+
-+/*
-+ * RX_PARSER_CFG:
-+ * Set NAV for all received frames
-+ */
-+#define RX_PARSER_CFG			0x1418
-+
-+/*
-+ * TX_SEC_CNT0:
-+ */
-+#define TX_SEC_CNT0			0x1500
-+
-+/*
-+ * RX_SEC_CNT0:
-+ */
-+#define RX_SEC_CNT0			0x1504
-+
-+/*
-+ * CCMP_FC_MUTE:
-+ */
-+#define CCMP_FC_MUTE			0x1508
-+
-+/*
-+ * TXOP_HLDR_ADDR0:
-+ */
-+#define TXOP_HLDR_ADDR0			0x1600
-+
-+/*
-+ * TXOP_HLDR_ADDR1:
-+ */
-+#define TXOP_HLDR_ADDR1			0x1604
-+
-+/*
-+ * TXOP_HLDR_ET:
-+ */
-+#define TXOP_HLDR_ET			0x1608
-+
-+/*
-+ * QOS_CFPOLL_RA_DW0:
-+ */
-+#define QOS_CFPOLL_RA_DW0		0x160c
-+
-+/*
-+ * QOS_CFPOLL_RA_DW1:
-+ */
-+#define QOS_CFPOLL_RA_DW1		0x1610
-+
-+/*
-+ * QOS_CFPOLL_QC:
-+ */
-+#define QOS_CFPOLL_QC			0x1614
-+
-+/*
-+ * RX_STA_CNT0: RX PLCP error count & RX CRC error count
-+ */
-+#define RX_STA_CNT0			0x1700
-+#define RX_STA_CNT0_CRC_ERR		FIELD32(0x0000ffff)
-+#define RX_STA_CNT0_PHY_ERR		FIELD32(0xffff0000)
-+
-+/*
-+ * RX_STA_CNT1: RX False CCA count & RX LONG frame count
-+ */
-+#define RX_STA_CNT1			0x1704
-+#define RX_STA_CNT1_FALSE_CCA		FIELD32(0x0000ffff)
-+#define RX_STA_CNT1_PLCP_ERR		FIELD32(0xffff0000)
-+
-+/*
-+ * RX_STA_CNT2:
-+ */
-+#define RX_STA_CNT2			0x1708
-+#define RX_STA_CNT2_RX_DUPLI_COUNT	FIELD32(0x0000ffff)
-+#define RX_STA_CNT2_RX_FIFO_OVERFLOW	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_STA_CNT0: TX Beacon count
-+ */
-+#define TX_STA_CNT0			0x170c
-+#define TX_STA_CNT0_TX_FAIL_COUNT	FIELD32(0x0000ffff)
-+#define TX_STA_CNT0_TX_BEACON_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_STA_CNT1: TX tx count
-+ */
-+#define TX_STA_CNT1			0x1710
-+#define TX_STA_CNT1_TX_SUCCESS		FIELD32(0x0000ffff)
-+#define TX_STA_CNT1_TX_RETRANSMIT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_STA_CNT2: TX tx count
-+ */
-+#define TX_STA_CNT2			0x1714
-+#define TX_STA_CNT2_TX_ZERO_LEN_COUNT	FIELD32(0x0000ffff)
-+#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_STA_FIFO: TX Result for specific PID status fifo register
-+ */
-+#define TX_STA_FIFO			0x1718
-+#define TX_STA_FIFO_VALID		FIELD32(0x00000001)
-+#define TX_STA_FIFO_PID_TYPE		FIELD32(0x0000001e)
-+#define TX_STA_FIFO_TX_SUCCESS		FIELD32(0x00000020)
-+#define TX_STA_FIFO_TX_AGGRE		FIELD32(0x00000040)
-+#define TX_STA_FIFO_TX_ACK_REQUIRED	FIELD32(0x00000080)
-+#define TX_STA_FIFO_WCID		FIELD32(0x0000ff00)
-+#define TX_STA_FIFO_SUCCESS_RATE	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT: Debug counter
-+ */
-+#define TX_AGG_CNT			0x171c
-+#define TX_AGG_CNT_NON_AGG_TX_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT_AGG_TX_COUNT		FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT0:
-+ */
-+#define TX_AGG_CNT0			0x1720
-+#define TX_AGG_CNT0_AGG_SIZE_1_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT0_AGG_SIZE_2_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT1:
-+ */
-+#define TX_AGG_CNT1			0x1724
-+#define TX_AGG_CNT1_AGG_SIZE_3_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT1_AGG_SIZE_4_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT2:
-+ */
-+#define TX_AGG_CNT2			0x1728
-+#define TX_AGG_CNT2_AGG_SIZE_5_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT2_AGG_SIZE_6_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT3:
-+ */
-+#define TX_AGG_CNT3			0x172c
-+#define TX_AGG_CNT3_AGG_SIZE_7_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT3_AGG_SIZE_8_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT4:
-+ */
-+#define TX_AGG_CNT4			0x1730
-+#define TX_AGG_CNT4_AGG_SIZE_9_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT4_AGG_SIZE_10_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT5:
-+ */
-+#define TX_AGG_CNT5			0x1734
-+#define TX_AGG_CNT5_AGG_SIZE_11_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT5_AGG_SIZE_12_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT6:
-+ */
-+#define TX_AGG_CNT6			0x1738
-+#define TX_AGG_CNT6_AGG_SIZE_13_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT6_AGG_SIZE_14_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * TX_AGG_CNT7:
-+ */
-+#define TX_AGG_CNT7			0x173c
-+#define TX_AGG_CNT7_AGG_SIZE_15_COUNT	FIELD32(0x0000ffff)
-+#define TX_AGG_CNT7_AGG_SIZE_16_COUNT	FIELD32(0xffff0000)
-+
-+/*
-+ * MPDU_DENSITY_CNT:
-+ * TX_ZERO_DEL: TX zero length delimiter count
-+ * RX_ZERO_DEL: RX zero length delimiter count
-+ */
-+#define MPDU_DENSITY_CNT		0x1740
-+#define MPDU_DENSITY_CNT_TX_ZERO_DEL	FIELD32(0x0000ffff)
-+#define MPDU_DENSITY_CNT_RX_ZERO_DEL	FIELD32(0xffff0000)
-+
-+/*
-+ * Security key table memory.
-+ * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
-+ * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
-+ * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
-+ * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
-+ * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
-+ * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
-+ */
-+#define MAC_WCID_BASE			0x1800
-+#define PAIRWISE_KEY_TABLE_BASE		0x4000
-+#define MAC_IVEIV_TABLE_BASE		0x6000
-+#define MAC_WCID_ATTRIBUTE_BASE		0x6800
-+#define SHARED_KEY_TABLE_BASE		0x6c00
-+#define SHARED_KEY_MODE_BASE		0x7000
-+
-+#define MAC_WCID_ENTRY(__idx) \
-+	( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
-+#define PAIRWISE_KEY_ENTRY(__idx) \
-+	( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
-+#define MAC_IVEIV_ENTRY(__idx) \
-+	( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
-+#define MAC_WCID_ATTR_ENTRY(__idx) \
-+	( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
-+#define SHARED_KEY_ENTRY(__idx) \
-+	( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
-+#define SHARED_KEY_MODE_ENTRY(__idx) \
-+	( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
-+
-+struct mac_wcid_entry {
-+	u8 mac[6];
-+	u8 reserved[2];
-+} __attribute__ ((packed));
-+
-+struct hw_key_entry {
-+	u8 key[16];
-+	u8 tx_mic[8];
-+	u8 rx_mic[8];
-+} __attribute__ ((packed));
-+
-+struct mac_iveiv_entry {
-+	u8 iv[8];
-+} __attribute__ ((packed));
-+
-+/*
-+ * MAC_WCID_ATTRIBUTE:
-+ */
-+#define MAC_WCID_ATTRIBUTE_KEYTAB	FIELD32(0x00000001)
-+#define MAC_WCID_ATTRIBUTE_CIPHER	FIELD32(0x0000000e)
-+#define MAC_WCID_ATTRIBUTE_BSS_IDX	FIELD32(0x00000070)
-+#define MAC_WCID_ATTRIBUTE_RX_WIUDF	FIELD32(0x00000380)
-+
-+/*
-+ * SHARED_KEY_MODE:
-+ */
-+#define SHARED_KEY_MODE_BSS0_KEY0	FIELD32(0x00000007)
-+#define SHARED_KEY_MODE_BSS0_KEY1	FIELD32(0x00000070)
-+#define SHARED_KEY_MODE_BSS0_KEY2	FIELD32(0x00000700)
-+#define SHARED_KEY_MODE_BSS0_KEY3	FIELD32(0x00007000)
-+#define SHARED_KEY_MODE_BSS1_KEY0	FIELD32(0x00070000)
-+#define SHARED_KEY_MODE_BSS1_KEY1	FIELD32(0x00700000)
-+#define SHARED_KEY_MODE_BSS1_KEY2	FIELD32(0x07000000)
-+#define SHARED_KEY_MODE_BSS1_KEY3	FIELD32(0x70000000)
-+
-+/*
-+ * HOST-MCU communication
-+ */
-+
-+/*
-+ * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
-+ */
-+#define H2M_MAILBOX_CSR			0x7010
-+#define H2M_MAILBOX_CSR_ARG0		FIELD32(0x000000ff)
-+#define H2M_MAILBOX_CSR_ARG1		FIELD32(0x0000ff00)
-+#define H2M_MAILBOX_CSR_CMD_TOKEN	FIELD32(0x00ff0000)
-+#define H2M_MAILBOX_CSR_OWNER		FIELD32(0xff000000)
-+
-+/*
-+ * H2M_MAILBOX_CID:
-+ */
-+#define H2M_MAILBOX_CID			0x7014
-+
-+/*
-+ * H2M_MAILBOX_STATUS:
-+ */
-+#define H2M_MAILBOX_STATUS		0x701c
-+
-+/*
-+ * H2M_INT_SRC:
-+ */
-+#define H2M_INT_SRC			0x7024
-+
-+/*
-+ * H2M_BBP_AGENT:
-+ */
-+#define H2M_BBP_AGENT			0x7028
-+
-+/*
-+ * MCU_LEDCS: LED control for MCU Mailbox.
-+ */
-+#define MCU_LEDCS_LED_MODE		FIELD8(0x1f)
-+#define MCU_LEDCS_POLARITY		FIELD8(0x01)
-+
-+/*
-+ * HW_CS_CTS_BASE:
-+ * Carrier-sense CTS frame base address.
-+ * It's where mac stores carrier-sense frame for carrier-sense function.
-+ */
-+#define HW_CS_CTS_BASE			0x7700
-+
-+/*
-+ * HW_DFS_CTS_BASE:
-+ * FS CTS frame base address. It's where mac stores CTS frame for DFS.
-+ */
-+#define HW_DFS_CTS_BASE			0x7780
-+
-+/*
-+ * TXRX control registers - base address 0x3000
-+ */
-+
-+/*
-+ * TXRX_CSR1:
-+ * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
-+ */
-+#define TXRX_CSR1			0x77d0
-+
-+/*
-+ * HW_DEBUG_SETTING_BASE:
-+ * since NULL frame won't be that long (256 byte)
-+ * We steal 16 tail bytes to save debugging settings
-+ */
-+#define HW_DEBUG_SETTING_BASE		0x77f0
-+#define HW_DEBUG_SETTING_BASE2		0x7770
-+
-+/*
-+ * HW_BEACON_BASE
-+ * In order to support maximum 8 MBSS and its maximum length
-+ * is 512 bytes for each beacon
-+ * Three section discontinue memory segments will be used.
-+ * 1. The original region for BCN 0~3
-+ * 2. Extract memory from FCE table for BCN 4~5
-+ * 3. Extract memory from Pair-wise key table for BCN 6~7
-+ *    It occupied those memory of wcid 238~253 for BCN 6
-+ *    and wcid 222~237 for BCN 7
-+ *
-+ * IMPORTANT NOTE: Not sure why legacy driver does this,
-+ * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
-+ */
-+#define HW_BEACON_BASE0			0x7800
-+#define HW_BEACON_BASE1			0x7a00
-+#define HW_BEACON_BASE2			0x7c00
-+#define HW_BEACON_BASE3			0x7e00
-+#define HW_BEACON_BASE4			0x7200
-+#define HW_BEACON_BASE5			0x7400
-+#define HW_BEACON_BASE6			0x5dc0
-+#define HW_BEACON_BASE7			0x5bc0
-+
-+#define HW_BEACON_OFFSET(__index) \
-+	( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
-+	  (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
-+	  (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
-+
-+/*
-+ * 8051 firmware image.
-+ */
-+#define FIRMWARE_RT2870			"rt2870.bin"
-+#define FIRMWARE_IMAGE_BASE		0x3000
-+
-+/*
-+ * BBP registers.
-+ * The wordsize of the BBP is 8 bits.
-+ */
-+
-+/*
-+ * BBP 1: TX Antenna
-+ */
-+#define BBP1_TX_POWER			FIELD8(0x07)
-+#define BBP1_TX_ANTENNA			FIELD8(0x18)
-+
-+/*
-+ * BBP 3: RX Antenna
-+ */
-+#define BBP3_RX_ANTENNA			FIELD8(0x18)
-+#define BBP3_HT40_PLUS			FIELD8(0x20)
-+
-+/*
-+ * BBP 4: Bandwidth
-+ */
-+#define BBP4_TX_BF			FIELD8(0x01)
-+#define BBP4_BANDWIDTH			FIELD8(0x18)
-+
-+/*
-+ * RFCSR registers
-+ * The wordsize of the RFCSR is 8 bits.
-+ */
-+
-+/*
-+ * RFCSR 6:
-+ */
-+#define RFCSR6_R			FIELD8(0x03)
-+
-+/*
-+ * RFCSR 7:
-+ */
-+#define RFCSR7_RF_TUNING		FIELD8(0x01)
-+
-+/*
-+ * RFCSR 12:
-+ */
-+#define RFCSR12_TX_POWER		FIELD8(0x1f)
-+
-+/*
-+ * RFCSR 22:
-+ */
-+#define RFCSR22_BASEBAND_LOOPBACK	FIELD8(0x01)
-+
-+/*
-+ * RFCSR 23:
-+ */
-+#define RFCSR23_FREQ_OFFSET		FIELD8(0x7f)
-+
-+/*
-+ * RFCSR 30:
-+ */
-+#define RFCSR30_RF_CALIBRATION		FIELD8(0x80)
-+
-+/*
-+ * RF registers
-+ */
-+
-+/*
-+ * RF 2
-+ */
-+#define RF2_ANTENNA_RX2			FIELD32(0x00000040)
-+#define RF2_ANTENNA_TX1			FIELD32(0x00004000)
-+#define RF2_ANTENNA_RX1			FIELD32(0x00020000)
-+
-+/*
-+ * RF 3
-+ */
-+#define RF3_TXPOWER_G			FIELD32(0x00003e00)
-+#define RF3_TXPOWER_A_7DBM_BOOST	FIELD32(0x00000200)
-+#define RF3_TXPOWER_A			FIELD32(0x00003c00)
-+
-+/*
-+ * RF 4
-+ */
-+#define RF4_TXPOWER_G			FIELD32(0x000007c0)
-+#define RF4_TXPOWER_A_7DBM_BOOST	FIELD32(0x00000040)
-+#define RF4_TXPOWER_A			FIELD32(0x00000780)
-+#define RF4_FREQ_OFFSET			FIELD32(0x001f8000)
-+#define RF4_HT40			FIELD32(0x00200000)
-+
-+/*
-+ * EEPROM content.
-+ * The wordsize of the EEPROM is 16 bits.
-+ */
-+
-+/*
-+ * EEPROM Version
-+ */
-+#define EEPROM_VERSION			0x0001
-+#define EEPROM_VERSION_FAE		FIELD16(0x00ff)
-+#define EEPROM_VERSION_VERSION		FIELD16(0xff00)
-+
-+/*
-+ * HW MAC address.
-+ */
-+#define EEPROM_MAC_ADDR_0		0x0002
-+#define EEPROM_MAC_ADDR_BYTE0		FIELD16(0x00ff)
-+#define EEPROM_MAC_ADDR_BYTE1		FIELD16(0xff00)
-+#define EEPROM_MAC_ADDR_1		0x0003
-+#define EEPROM_MAC_ADDR_BYTE2		FIELD16(0x00ff)
-+#define EEPROM_MAC_ADDR_BYTE3		FIELD16(0xff00)
-+#define EEPROM_MAC_ADDR_2		0x0004
-+#define EEPROM_MAC_ADDR_BYTE4		FIELD16(0x00ff)
-+#define EEPROM_MAC_ADDR_BYTE5		FIELD16(0xff00)
-+
-+/*
-+ * EEPROM ANTENNA config
-+ * RXPATH: 1: 1R, 2: 2R, 3: 3R
-+ * TXPATH: 1: 1T, 2: 2T
-+ */
-+#define	EEPROM_ANTENNA			0x001a
-+#define EEPROM_ANTENNA_RXPATH		FIELD16(0x000f)
-+#define EEPROM_ANTENNA_TXPATH		FIELD16(0x00f0)
-+#define EEPROM_ANTENNA_RF_TYPE		FIELD16(0x0f00)
-+
-+/*
-+ * EEPROM NIC config
-+ * CARDBUS_ACCEL: 0 - enable, 1 - disable
-+ */
-+#define	EEPROM_NIC			0x001b
-+#define EEPROM_NIC_HW_RADIO		FIELD16(0x0001)
-+#define EEPROM_NIC_DYNAMIC_TX_AGC	FIELD16(0x0002)
-+#define EEPROM_NIC_EXTERNAL_LNA_BG	FIELD16(0x0004)
-+#define EEPROM_NIC_EXTERNAL_LNA_A	FIELD16(0x0008)
-+#define EEPROM_NIC_CARDBUS_ACCEL	FIELD16(0x0010)
-+#define EEPROM_NIC_BW40M_SB_BG		FIELD16(0x0020)
-+#define EEPROM_NIC_BW40M_SB_A		FIELD16(0x0040)
-+#define EEPROM_NIC_WPS_PBC		FIELD16(0x0080)
-+#define EEPROM_NIC_BW40M_BG		FIELD16(0x0100)
-+#define EEPROM_NIC_BW40M_A		FIELD16(0x0200)
-+
-+/*
-+ * EEPROM frequency
-+ */
-+#define	EEPROM_FREQ			0x001d
-+#define EEPROM_FREQ_OFFSET		FIELD16(0x00ff)
-+#define EEPROM_FREQ_LED_MODE		FIELD16(0x7f00)
-+#define EEPROM_FREQ_LED_POLARITY	FIELD16(0x1000)
-+
-+/*
-+ * EEPROM LED
-+ * POLARITY_RDY_G: Polarity RDY_G setting.
-+ * POLARITY_RDY_A: Polarity RDY_A setting.
-+ * POLARITY_ACT: Polarity ACT setting.
-+ * POLARITY_GPIO_0: Polarity GPIO0 setting.
-+ * POLARITY_GPIO_1: Polarity GPIO1 setting.
-+ * POLARITY_GPIO_2: Polarity GPIO2 setting.
-+ * POLARITY_GPIO_3: Polarity GPIO3 setting.
-+ * POLARITY_GPIO_4: Polarity GPIO4 setting.
-+ * LED_MODE: Led mode.
-+ */
-+#define EEPROM_LED1			0x001e
-+#define EEPROM_LED2			0x001f
-+#define EEPROM_LED3			0x0020
-+#define EEPROM_LED_POLARITY_RDY_BG	FIELD16(0x0001)
-+#define EEPROM_LED_POLARITY_RDY_A	FIELD16(0x0002)
-+#define EEPROM_LED_POLARITY_ACT		FIELD16(0x0004)
-+#define EEPROM_LED_POLARITY_GPIO_0	FIELD16(0x0008)
-+#define EEPROM_LED_POLARITY_GPIO_1	FIELD16(0x0010)
-+#define EEPROM_LED_POLARITY_GPIO_2	FIELD16(0x0020)
-+#define EEPROM_LED_POLARITY_GPIO_3	FIELD16(0x0040)
-+#define EEPROM_LED_POLARITY_GPIO_4	FIELD16(0x0080)
-+#define EEPROM_LED_LED_MODE		FIELD16(0x1f00)
-+
-+/*
-+ * EEPROM LNA
-+ */
-+#define EEPROM_LNA			0x0022
-+#define EEPROM_LNA_BG			FIELD16(0x00ff)
-+#define EEPROM_LNA_A0			FIELD16(0xff00)
-+
-+/*
-+ * EEPROM RSSI BG offset
-+ */
-+#define EEPROM_RSSI_BG			0x0023
-+#define EEPROM_RSSI_BG_OFFSET0		FIELD16(0x00ff)
-+#define EEPROM_RSSI_BG_OFFSET1		FIELD16(0xff00)
-+
-+/*
-+ * EEPROM RSSI BG2 offset
-+ */
-+#define EEPROM_RSSI_BG2			0x0024
-+#define EEPROM_RSSI_BG2_OFFSET2		FIELD16(0x00ff)
-+#define EEPROM_RSSI_BG2_LNA_A1		FIELD16(0xff00)
-+
-+/*
-+ * EEPROM RSSI A offset
-+ */
-+#define EEPROM_RSSI_A			0x0025
-+#define EEPROM_RSSI_A_OFFSET0		FIELD16(0x00ff)
-+#define EEPROM_RSSI_A_OFFSET1		FIELD16(0xff00)
-+
-+/*
-+ * EEPROM RSSI A2 offset
-+ */
-+#define EEPROM_RSSI_A2			0x0026
-+#define EEPROM_RSSI_A2_OFFSET2		FIELD16(0x00ff)
-+#define EEPROM_RSSI_A2_LNA_A2		FIELD16(0xff00)
-+
-+/*
-+ * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
-+ *	This is delta in 40MHZ.
-+ * VALUE: Tx Power dalta value (MAX=4)
-+ * TYPE: 1: Plus the delta value, 0: minus the delta value
-+ * TXPOWER: Enable:
-+ */
-+#define EEPROM_TXPOWER_DELTA		0x0028
-+#define EEPROM_TXPOWER_DELTA_VALUE	FIELD16(0x003f)
-+#define EEPROM_TXPOWER_DELTA_TYPE	FIELD16(0x0040)
-+#define EEPROM_TXPOWER_DELTA_TXPOWER	FIELD16(0x0080)
-+
-+/*
-+ * EEPROM TXPOWER 802.11BG
-+ */
-+#define	EEPROM_TXPOWER_BG1		0x0029
-+#define	EEPROM_TXPOWER_BG2		0x0030
-+#define EEPROM_TXPOWER_BG_SIZE		7
-+#define EEPROM_TXPOWER_BG_1		FIELD16(0x00ff)
-+#define EEPROM_TXPOWER_BG_2		FIELD16(0xff00)
-+
-+/*
-+ * EEPROM TXPOWER 802.11A
-+ */
-+#define EEPROM_TXPOWER_A1		0x003c
-+#define EEPROM_TXPOWER_A2		0x0053
-+#define EEPROM_TXPOWER_A_SIZE		6
-+#define EEPROM_TXPOWER_A_1		FIELD16(0x00ff)
-+#define EEPROM_TXPOWER_A_2		FIELD16(0xff00)
-+
-+/*
-+ * EEPROM TXpower byrate: 20MHZ power
-+ */
-+#define EEPROM_TXPOWER_BYRATE		0x006f
-+
-+/*
-+ * EEPROM BBP.
-+ */
-+#define	EEPROM_BBP_START		0x0078
-+#define EEPROM_BBP_SIZE			16
-+#define EEPROM_BBP_VALUE		FIELD16(0x00ff)
-+#define EEPROM_BBP_REG_ID		FIELD16(0xff00)
-+
-+/*
-+ * MCU mailbox commands.
-+ */
-+#define MCU_SLEEP			0x30
-+#define MCU_WAKEUP			0x31
-+#define MCU_RADIO_OFF			0x35
-+#define MCU_LED				0x50
-+#define MCU_LED_STRENGTH		0x51
-+#define MCU_LED_1			0x52
-+#define MCU_LED_2			0x53
-+#define MCU_LED_3			0x54
-+#define MCU_RADAR			0x60
-+#define MCU_BOOT_SIGNAL			0x72
-+#define MCU_BBP_SIGNAL			0x80
-+
-+/*
-+ * DMA descriptor defines.
-+ */
-+#define TXD_DESC_SIZE			( 4 * sizeof(__le32) )
-+#define TXINFO_DESC_SIZE		( 1 * sizeof(__le32) )
-+#define TXWI_DESC_SIZE			( 4 * sizeof(__le32) )
-+#define RXD_DESC_SIZE			( 1 * sizeof(__le32) )
-+#define RXWI_DESC_SIZE			( 4 * sizeof(__le32) )
-+
-+/*
-+ * TX descriptor format for TX, PRIO and Beacon Ring.
-+ */
-+
-+/*
-+ * Word0
-+ */
-+#define TXD_W0_SD_PTR0			FIELD32(0xffffffff)
-+
-+/*
-+ * Word1
-+ */
-+#define TXD_W1_SD_LEN1			FIELD32(0x00003fff)
-+#define TXD_W1_LAST_SEC1		FIELD32(0x00004000)
-+#define TXD_W1_BURST			FIELD32(0x00008000)
-+#define TXD_W1_SD_LEN0			FIELD32(0x3fff0000)
-+#define TXD_W1_LAST_SEC0		FIELD32(0x40000000)
-+#define TXD_W1_DMA_DONE			FIELD32(0x80000000)
-+
-+/*
-+ * Word2
-+ */
-+#define TXD_W2_SD_PTR1			FIELD32(0xffffffff)
-+
-+/*
-+ * Word3
-+ * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
-+ * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
-+ *       0:MGMT, 1:HCCA 2:EDCA
-+ */
-+#define TXD_W3_WIV			FIELD32(0x01000000)
-+#define TXD_W3_QSEL			FIELD32(0x06000000)
-+#define TXD_W3_TCO			FIELD32(0x20000000)
-+#define TXD_W3_UCO			FIELD32(0x40000000)
-+#define TXD_W3_ICO			FIELD32(0x80000000)
-+
-+/*
-+ * TX Info structure
-+ */
-+
-+/*
-+ * Word0
-+ * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
-+ * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
-+ *       0:MGMT, 1:HCCA 2:EDCA
-+ * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
-+ * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
-+ *               Force USB DMA transmit frame from current selected endpoint
-+ */
-+#define TXINFO_W0_USB_DMA_TX_PKT_LEN	FIELD32(0x0000ffff)
-+#define TXINFO_W0_WIV			FIELD32(0x01000000)
-+#define TXINFO_W0_QSEL			FIELD32(0x06000000)
-+#define TXINFO_W0_SW_USE_LAST_ROUND	FIELD32(0x08000000)
-+#define TXINFO_W0_USB_DMA_NEXT_VALID	FIELD32(0x40000000)
-+#define TXINFO_W0_USB_DMA_TX_BURST	FIELD32(0x80000000)
-+
-+/*
-+ * TX WI structure
-+ */
-+
-+/*
-+ * Word0
-+ * FRAG: 1 To inform TKIP engine this is a fragment.
-+ * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
-+ * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
-+ * BW: Channel bandwidth 20MHz or 40 MHz
-+ * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
-+ */
-+#define TXWI_W0_FRAG			FIELD32(0x00000001)
-+#define TXWI_W0_MIMO_PS			FIELD32(0x00000002)
-+#define TXWI_W0_CF_ACK			FIELD32(0x00000004)
-+#define TXWI_W0_TS			FIELD32(0x00000008)
-+#define TXWI_W0_AMPDU			FIELD32(0x00000010)
-+#define TXWI_W0_MPDU_DENSITY		FIELD32(0x000000e0)
-+#define TXWI_W0_TX_OP			FIELD32(0x00000300)
-+#define TXWI_W0_MCS			FIELD32(0x007f0000)
-+#define TXWI_W0_BW			FIELD32(0x00800000)
-+#define TXWI_W0_SHORT_GI		FIELD32(0x01000000)
-+#define TXWI_W0_STBC			FIELD32(0x06000000)
-+#define TXWI_W0_IFS			FIELD32(0x08000000)
-+#define TXWI_W0_PHYMODE			FIELD32(0xc0000000)
-+
-+/*
-+ * Word1
-+ */
-+#define TXWI_W1_ACK			FIELD32(0x00000001)
-+#define TXWI_W1_NSEQ			FIELD32(0x00000002)
-+#define TXWI_W1_BW_WIN_SIZE		FIELD32(0x000000fc)
-+#define TXWI_W1_WIRELESS_CLI_ID		FIELD32(0x0000ff00)
-+#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT	FIELD32(0x0fff0000)
-+#define TXWI_W1_PACKETID		FIELD32(0xf0000000)
-+
-+/*
-+ * Word2
-+ */
-+#define TXWI_W2_IV			FIELD32(0xffffffff)
-+
-+/*
-+ * Word3
-+ */
-+#define TXWI_W3_EIV			FIELD32(0xffffffff)
-+
-+/*
-+ * RX descriptor format for RX Ring.
-+ */
-+
-+/*
-+ * Word0
-+ * UNICAST_TO_ME: This RX frame is unicast to me.
-+ * MULTICAST: This is a multicast frame.
-+ * BROADCAST: This is a broadcast frame.
-+ * MY_BSS: this frame belongs to the same BSSID.
-+ * CRC_ERROR: CRC error.
-+ * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
-+ * AMSDU: rx with 802.3 header, not 802.11 header.
-+ */
-+
-+#define RXD_W0_BA			FIELD32(0x00000001)
-+#define RXD_W0_DATA			FIELD32(0x00000002)
-+#define RXD_W0_NULLDATA			FIELD32(0x00000004)
-+#define RXD_W0_FRAG			FIELD32(0x00000008)
-+#define RXD_W0_UNICAST_TO_ME		FIELD32(0x00000010)
-+#define RXD_W0_MULTICAST		FIELD32(0x00000020)
-+#define RXD_W0_BROADCAST		FIELD32(0x00000040)
-+#define RXD_W0_MY_BSS			FIELD32(0x00000080)
-+#define RXD_W0_CRC_ERROR		FIELD32(0x00000100)
-+#define RXD_W0_CIPHER_ERROR		FIELD32(0x00000600)
-+#define RXD_W0_AMSDU			FIELD32(0x00000800)
-+#define RXD_W0_HTC			FIELD32(0x00001000)
-+#define RXD_W0_RSSI			FIELD32(0x00002000)
-+#define RXD_W0_L2PAD			FIELD32(0x00004000)
-+#define RXD_W0_AMPDU			FIELD32(0x00008000)
-+#define RXD_W0_DECRYPTED		FIELD32(0x00010000)
-+#define RXD_W0_PLCP_RSSI		FIELD32(0x00020000)
-+#define RXD_W0_CIPHER_ALG		FIELD32(0x00040000)
-+#define RXD_W0_LAST_AMSDU		FIELD32(0x00080000)
-+#define RXD_W0_PLCP_SIGNAL		FIELD32(0xfff00000)
-+
-+/*
-+ * RX WI structure
-+ */
-+
-+/*
-+ * Word0
-+ */
-+#define RXWI_W0_WIRELESS_CLI_ID		FIELD32(0x000000ff)
-+#define RXWI_W0_KEY_INDEX		FIELD32(0x00000300)
-+#define RXWI_W0_BSSID			FIELD32(0x00001c00)
-+#define RXWI_W0_UDF			FIELD32(0x0000e000)
-+#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT	FIELD32(0x0fff0000)
-+#define RXWI_W0_TID			FIELD32(0xf0000000)
-+
-+/*
-+ * Word1
-+ */
-+#define RXWI_W1_FRAG			FIELD32(0x0000000f)
-+#define RXWI_W1_SEQUENCE		FIELD32(0x0000fff0)
-+#define RXWI_W1_MCS			FIELD32(0x007f0000)
-+#define RXWI_W1_BW			FIELD32(0x00800000)
-+#define RXWI_W1_SHORT_GI		FIELD32(0x01000000)
-+#define RXWI_W1_STBC			FIELD32(0x06000000)
-+#define RXWI_W1_PHYMODE			FIELD32(0xc0000000)
-+
-+/*
-+ * Word2
-+ */
-+#define RXWI_W2_RSSI0			FIELD32(0x000000ff)
-+#define RXWI_W2_RSSI1			FIELD32(0x0000ff00)
-+#define RXWI_W2_RSSI2			FIELD32(0x00ff0000)
-+
-+/*
-+ * Word3
-+ */
-+#define RXWI_W3_SNR0			FIELD32(0x000000ff)
-+#define RXWI_W3_SNR1			FIELD32(0x0000ff00)
-+
-+/*
-+ * Macro's for converting txpower from EEPROM to mac80211 value
-+ * and from mac80211 value to register value.
-+ */
-+#define MIN_G_TXPOWER	0
-+#define MIN_A_TXPOWER	-7
-+#define MAX_G_TXPOWER	31
-+#define MAX_A_TXPOWER	15
-+#define DEFAULT_TXPOWER	5
-+
-+#define TXPOWER_G_FROM_DEV(__txpower) \
-+	((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
-+
-+#define TXPOWER_G_TO_DEV(__txpower) \
-+	clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
-+
-+#define TXPOWER_A_FROM_DEV(__txpower) \
-+	((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
-+
-+#define TXPOWER_A_TO_DEV(__txpower) \
-+	clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
-+
-+#endif /* RT2800USB_H */
---- a/drivers/net/wireless/rt2x00/rt2x00.h
-+++ b/drivers/net/wireless/rt2x00/rt2x00.h
-@@ -144,6 +144,7 @@ struct rt2x00_chip {
- #define RT2890D		0x0781	/* 2.4GHz, 5GHz PCIe */
- #define RT2880		0x2880	/* WSOC */
- #define RT3052		0x3052	/* WSOC */
-+#define RT2870		0x1600
- 
- 	u16 rf;
- 	u32 rev;
diff --git a/package/mac80211/patches/401-ath9k-dont-register-leds-on-ar9100.patch b/package/mac80211/patches/401-ath9k-dont-register-leds-on-ar9100.patch
index 4fe0e46cc..c5895a361 100644
--- a/package/mac80211/patches/401-ath9k-dont-register-leds-on-ar9100.patch
+++ b/package/mac80211/patches/401-ath9k-dont-register-leds-on-ar9100.patch
@@ -1,6 +1,6 @@
---- a/drivers/net/wireless/ath9k/main.c
-+++ b/drivers/net/wireless/ath9k/main.c
-@@ -1031,6 +1031,9 @@ static void ath_unregister_led(struct at
+--- a/drivers/net/wireless/ath/ath9k/main.c
++++ b/drivers/net/wireless/ath/ath9k/main.c
+@@ -1020,6 +1020,9 @@ static void ath_unregister_led(struct at
  
  static void ath_deinit_leds(struct ath_softc *sc)
  {
@@ -10,7 +10,7 @@
  	cancel_delayed_work_sync(&sc->ath_led_blink_work);
  	ath_unregister_led(&sc->assoc_led);
  	sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
-@@ -1045,6 +1048,9 @@ static void ath_init_leds(struct ath_sof
+@@ -1034,6 +1037,9 @@ static void ath_init_leds(struct ath_sof
  	char *trigger;
  	int ret;
  
diff --git a/package/mac80211/patches/402-ath9k-enable-debug.patch b/package/mac80211/patches/402-ath9k-enable-debug.patch
index 24234eb22..c4a4936cc 100644
--- a/package/mac80211/patches/402-ath9k-enable-debug.patch
+++ b/package/mac80211/patches/402-ath9k-enable-debug.patch
@@ -1,6 +1,6 @@
 --- a/config.mk
 +++ b/config.mk
-@@ -125,7 +125,7 @@ ifneq ($(CONFIG_PCI),)
+@@ -124,7 +124,7 @@ ifneq ($(CONFIG_PCI),)
  CONFIG_ATH5K=m
  # CONFIG_ATH5K_DEBUG=y
  CONFIG_ATH9K=m
diff --git a/package/mac80211/patches/403-ath9k-fix-invalid-mac-address-handling.patch b/package/mac80211/patches/403-ath9k-fix-invalid-mac-address-handling.patch
index 69d32103b..e740c90ab 100644
--- a/package/mac80211/patches/403-ath9k-fix-invalid-mac-address-handling.patch
+++ b/package/mac80211/patches/403-ath9k-fix-invalid-mac-address-handling.patch
@@ -1,11 +1,11 @@
---- a/drivers/net/wireless/ath9k/hw.c
-+++ b/drivers/net/wireless/ath9k/hw.c
-@@ -513,11 +513,18 @@ static int ath9k_hw_init_macaddr(struct 
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -534,8 +534,18 @@ static int ath9k_hw_init_macaddr(struct 
  		ah->macaddr[2 * i] = eeval >> 8;
  		ah->macaddr[2 * i + 1] = eeval & 0xff;
  	}
--	if (sum == 0 || sum == 0xffff * 3) {
-+
+-	if (sum == 0 || sum == 0xffff * 3)
+-		return -EADDRNOTAVAIL;
 +	if (!is_valid_ether_addr(ah->macaddr)) {
 +		DECLARE_MAC_BUF(macbuf);
 +
@@ -14,12 +14,10 @@
 +			print_mac(macbuf, ah->macaddr));
 +
 +		random_ether_addr(ah->macaddr);
- 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
--			"mac address read failed: %pM\n",
--			ah->macaddr);
--		return -EADDRNOTAVAIL;
++		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 +			"random mac address will be used: %s\n",
 +			print_mac(macbuf, ah->macaddr));
- 	}
++	}
  
  	return 0;
+ }
diff --git a/package/mac80211/patches/404-ath9k-uninline-ath9k_io-read-write-32-routines.patch b/package/mac80211/patches/404-ath9k-uninline-ath9k_io-read-write-32-routines.patch
deleted file mode 100644
index d461cb17e..000000000
--- a/package/mac80211/patches/404-ath9k-uninline-ath9k_io-read-write-32-routines.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From dd51972ba5d11df434faf9171fe02c0cc48d35c1 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Wed, 29 Apr 2009 08:52:16 +0200
-Subject: [PATCH] ath9k: uninline ath9k_io{read,write}32 routines
-
-The spin_lock handling uses lots of instructions on some archs.
-With this patch the size of the ath9k module will be significantly
-smaller.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
-Example results on different platforms:
-
-xscale:     468344 -> 293022 (62.6%)
-mips32:     549847 -> 389421 (70.8%)
-mips32r2:   510520 -> 394020 (77.2%)
-ppc40x:     365153 -> 296928 (81.3%)
-
- drivers/net/wireless/ath9k/ath9k.h |   33 +------------------------------
- drivers/net/wireless/ath9k/hw.c    |   32 +++++++++++++++++++++++++++++++
- 2 files changed, 34 insertions(+), 31 deletions(-)
-
---- a/drivers/net/wireless/ath9k/ath9k.h
-+++ b/drivers/net/wireless/ath9k/ath9k.h
-@@ -721,36 +721,7 @@ void ath9k_wiphy_pause_all_forced(struct
- bool ath9k_wiphy_scanning(struct ath_softc *sc);
- void ath9k_wiphy_work(struct work_struct *work);
- 
--/*
-- * Read and write, they both share the same lock. We do this to serialize
-- * reads and writes on Atheros 802.11n PCI devices only. This is required
-- * as the FIFO on these devices can only accept sanely 2 requests. After
-- * that the device goes bananas. Serializing the reads/writes prevents this
-- * from happening.
-- */
--
--static inline void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
--{
--	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
--		unsigned long flags;
--		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
--		iowrite32(val, ah->ah_sc->mem + reg_offset);
--		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
--	} else
--		iowrite32(val, ah->ah_sc->mem + reg_offset);
--}
--
--static inline unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
--{
--	u32 val;
--	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
--		unsigned long flags;
--		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
--		val = ioread32(ah->ah_sc->mem + reg_offset);
--		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
--	} else
--		val = ioread32(ah->ah_sc->mem + reg_offset);
--	return val;
--}
-+void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val);
-+unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset);
- 
- #endif /* ATH9K_H */
---- a/drivers/net/wireless/ath9k/hw.c
-+++ b/drivers/net/wireless/ath9k/hw.c
-@@ -84,6 +84,38 @@ static u32 ath9k_hw_mac_to_clks(struct a
- 		return ath9k_hw_mac_clks(ah, usecs);
- }
- 
-+/*
-+ * Read and write, they both share the same lock. We do this to serialize
-+ * reads and writes on Atheros 802.11n PCI devices only. This is required
-+ * as the FIFO on these devices can only accept sanely 2 requests. After
-+ * that the device goes bananas. Serializing the reads/writes prevents this
-+ * from happening.
-+ */
-+
-+void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
-+{
-+	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
-+		unsigned long flags;
-+		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
-+		iowrite32(val, ah->ah_sc->mem + reg_offset);
-+		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
-+	} else
-+		iowrite32(val, ah->ah_sc->mem + reg_offset);
-+}
-+
-+unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
-+{
-+	u32 val;
-+	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
-+		unsigned long flags;
-+		spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
-+		val = ioread32(ah->ah_sc->mem + reg_offset);
-+		spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
-+	} else
-+		val = ioread32(ah->ah_sc->mem + reg_offset);
-+	return val;
-+}
-+
- bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
- {
- 	int i;
diff --git a/package/mac80211/patches/510-b43-poison-rx-buffers.patch b/package/mac80211/patches/510-b43-poison-rx-buffers.patch
deleted file mode 100644
index c1c6d79bd..000000000
--- a/package/mac80211/patches/510-b43-poison-rx-buffers.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-This patch adds poisoning and sanity checking to the RX DMA buffers.
-This is used for protection against buggy hardware/firmware that raises
-RX interrupts without doing an actual DMA transfer.
-
-This mechanism protects against rare "bad packets" (due to uninitialized skb data)
-and rare kernel crashes due to uninitialized RX headers.
-
-The poison is selected to not match on valid frames and to be cheap for checking.
-
-The poison check mechanism _might_ trigger incorrectly, if we are voluntarily
-receiving frames with bad PLCP headers. However, this is nonfatal, because the
-chance of such a match is basically zero and in case it happens it just results
-in dropping the packet.
-Bad-PLCP RX defaults to off, and you should leave it off unless you want to listen
-to the latest news broadcasted by your microwave oven.
-
-This patch also moves the initialization of the RX-header "length" field in front of
-the mapping of the DMA buffer. The CPU should not touch the buffer after we mapped it.
-
-Cc: stable@kernel.org
-Reported-by: Francesco Gringoli <francesco.gringoli@ing.unibs.it>
-Signed-off-by: Michael Buesch <mb@bu3sch.de>
-
----
-
---- a/drivers/net/wireless/b43/dma.c
-+++ b/drivers/net/wireless/b43/dma.c
-@@ -555,11 +555,32 @@ address_error:
- 	return 1;
- }
- 
-+static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
-+{
-+	unsigned char *f = skb->data + ring->frameoffset;
-+
-+	return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
-+}
-+
-+static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
-+{
-+	struct b43_rxhdr_fw4 *rxhdr;
-+	unsigned char *frame;
-+
-+	/* This poisons the RX buffer to detect DMA failures. */
-+
-+	rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
-+	rxhdr->frame_len = 0;
-+
-+	B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
-+	frame = skb->data + ring->frameoffset;
-+	memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
-+}
-+
- static int setup_rx_descbuffer(struct b43_dmaring *ring,
- 			       struct b43_dmadesc_generic *desc,
- 			       struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
- {
--	struct b43_rxhdr_fw4 *rxhdr;
- 	dma_addr_t dmaaddr;
- 	struct sk_buff *skb;
- 
-@@ -568,6 +589,7 @@ static int setup_rx_descbuffer(struct b4
- 	skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
- 	if (unlikely(!skb))
- 		return -ENOMEM;
-+	b43_poison_rx_buffer(ring, skb);
- 	dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
- 	if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
- 		/* ugh. try to realloc in zone_dma */
-@@ -578,6 +600,7 @@ static int setup_rx_descbuffer(struct b4
- 		skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
- 		if (unlikely(!skb))
- 			return -ENOMEM;
-+		b43_poison_rx_buffer(ring, skb);
- 		dmaaddr = map_descbuffer(ring, skb->data,
- 					 ring->rx_buffersize, 0);
- 		if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
-@@ -592,9 +615,6 @@ static int setup_rx_descbuffer(struct b4
- 	ring->ops->fill_descriptor(ring, desc, dmaaddr,
- 				   ring->rx_buffersize, 0, 0, 0);
- 
--	rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
--	rxhdr->frame_len = 0;
--
- 	return 0;
- }
- 
-@@ -1489,6 +1509,15 @@ static void dma_rx(struct b43_dmaring *r
- 			goto drop;
- 		}
- 	}
-+	if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
-+		/* Something went wrong with the DMA.
-+		 * The device did not touch the buffer and did not overwrite the poison. */
-+		b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
-+		/* recycle the descriptor buffer. */
-+		sync_descbuffer_for_device(ring, meta->dmaaddr,
-+					   ring->rx_buffersize);
-+		goto drop;
-+	}
- 	if (unlikely(len > ring->rx_buffersize)) {
- 		/* The data did not fit into one descriptor buffer
- 		 * and is split over multiple buffers.
diff --git a/package/mac80211/patches/511-b43-refresh-rx-poison-on-buffer-recycling.patch b/package/mac80211/patches/511-b43-refresh-rx-poison-on-buffer-recycling.patch
deleted file mode 100644
index dfe79208c..000000000
--- a/package/mac80211/patches/511-b43-refresh-rx-poison-on-buffer-recycling.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-The RX buffer poison needs to be refreshed, if we recycle an RX buffer,
-because it might be (partially) overwritten by some DMA operations.
-
-Cc: stable@kernel.org
-Cc: Francesco Gringoli <francesco.gringoli@ing.unibs.it>
-Signed-off-by: Michael Buesch <mb@bu3sch.de>
-
----
-
---- a/drivers/net/wireless/b43/dma.c
-+++ b/drivers/net/wireless/b43/dma.c
-@@ -1503,20 +1503,16 @@ static void dma_rx(struct b43_dmaring *r
- 			len = le16_to_cpu(rxhdr->frame_len);
- 		} while (len == 0 && i++ < 5);
- 		if (unlikely(len == 0)) {
--			/* recycle the descriptor buffer. */
--			sync_descbuffer_for_device(ring, meta->dmaaddr,
--						   ring->rx_buffersize);
--			goto drop;
-+			dmaaddr = meta->dmaaddr;
-+			goto drop_recycle_buffer;
- 		}
- 	}
- 	if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
- 		/* Something went wrong with the DMA.
- 		 * The device did not touch the buffer and did not overwrite the poison. */
- 		b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
--		/* recycle the descriptor buffer. */
--		sync_descbuffer_for_device(ring, meta->dmaaddr,
--					   ring->rx_buffersize);
--		goto drop;
-+		dmaaddr = meta->dmaaddr;
-+		goto drop_recycle_buffer;
- 	}
- 	if (unlikely(len > ring->rx_buffersize)) {
- 		/* The data did not fit into one descriptor buffer
-@@ -1530,6 +1526,7 @@ static void dma_rx(struct b43_dmaring *r
- 		while (1) {
- 			desc = ops->idx2desc(ring, *slot, &meta);
- 			/* recycle the descriptor buffer. */
-+			b43_poison_rx_buffer(ring, meta->skb);
- 			sync_descbuffer_for_device(ring, meta->dmaaddr,
- 						   ring->rx_buffersize);
- 			*slot = next_slot(ring, *slot);
-@@ -1548,8 +1545,7 @@ static void dma_rx(struct b43_dmaring *r
- 	err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
- 	if (unlikely(err)) {
- 		b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
--		sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
--		goto drop;
-+		goto drop_recycle_buffer;
- 	}
- 
- 	unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
-@@ -1559,6 +1555,11 @@ static void dma_rx(struct b43_dmaring *r
- 	b43_rx(ring->dev, skb, rxhdr);
- drop:
- 	return;
-+
-+drop_recycle_buffer:
-+	/* Poison and recycle the RX buffer. */
-+	b43_poison_rx_buffer(ring, skb);
-+	sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
- }
- 
- void b43_dma_rx(struct b43_dmaring *ring)
diff --git a/package/mac80211/patches/520-b43-autodepend-on-hwrandom.patch b/package/mac80211/patches/520-b43-autodepend-on-hwrandom.patch
deleted file mode 100644
index 0eef6bfdb..000000000
--- a/package/mac80211/patches/520-b43-autodepend-on-hwrandom.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-This patch is submitted upstream and can be removed when it hits compat-wireless.
-
---mb
-
-
-
---- a/drivers/net/wireless/b43/b43.h
-+++ b/drivers/net/wireless/b43/b43.h
-@@ -625,9 +625,11 @@ struct b43_wl {
- 	/* Stats about the wireless interface */
- 	struct ieee80211_low_level_stats ieee_stats;
- 
-+#ifdef CONFIG_B43_HWRNG
- 	struct hwrng rng;
--	u8 rng_initialized;
-+	bool rng_initialized;
- 	char rng_name[30 + 1];
-+#endif /* CONFIG_B43_HWRNG */
- 
- 	/* The RF-kill button */
- 	struct b43_rfkill rfkill;
---- a/drivers/net/wireless/b43/main.c
-+++ b/drivers/net/wireless/b43/main.c
-@@ -2980,6 +2980,7 @@ static void b43_security_init(struct b43
- 	b43_clear_keys(dev);
- }
- 
-+#ifdef CONFIG_B43_HWRNG
- static int b43_rng_read(struct hwrng *rng, u32 *data)
- {
- 	struct b43_wl *wl = (struct b43_wl *)rng->priv;
-@@ -2995,17 +2996,21 @@ static int b43_rng_read(struct hwrng *rn
- 
- 	return (sizeof(u16));
- }
-+#endif /* CONFIG_B43_HWRNG */
- 
- static void b43_rng_exit(struct b43_wl *wl)
- {
-+#ifdef CONFIG_B43_HWRNG
- 	if (wl->rng_initialized)
- 		hwrng_unregister(&wl->rng);
-+#endif /* CONFIG_B43_HWRNG */
- }
- 
- static int b43_rng_init(struct b43_wl *wl)
- {
--	int err;
-+	int err = 0;
- 
-+#ifdef CONFIG_B43_HWRNG
- 	snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
- 		 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
- 	wl->rng.name = wl->rng_name;
-@@ -3018,6 +3023,7 @@ static int b43_rng_init(struct b43_wl *w
- 		b43err(wl, "Failed to register the random "
- 		       "number generator (%d)\n", err);
- 	}
-+#endif /* CONFIG_B43_HWRNG */
- 
- 	return err;
- }
---- a/config.mk
-+++ b/config.mk
-@@ -148,6 +148,7 @@ CONFIG_ATH9K_DEBUG=y
- # CONFIG_B43_PIO=y
- # CONFIG_B43_LEDS=y
- # CONFIG_B43_RFKILL=y
-+# CONFIG_B43_HWRNG=y
- # CONFIG_B43_DEBUG=y
- # CONFIG_B43_FORCE_PIO=y
- 
diff --git a/package/mac80211/patches/530-b43-optimize-hotpath-mmio.patch b/package/mac80211/patches/530-b43-optimize-hotpath-mmio.patch
deleted file mode 100644
index 9ea12f3b4..000000000
--- a/package/mac80211/patches/530-b43-optimize-hotpath-mmio.patch
+++ /dev/null
@@ -1,173 +0,0 @@
---- a/drivers/net/wireless/b43/b43.h
-+++ b/drivers/net/wireless/b43/b43.h
-@@ -778,8 +778,8 @@ struct b43_wldev {
- 	/* Reason code of the last interrupt. */
- 	u32 irq_reason;
- 	u32 dma_reason[6];
--	/* saved irq enable/disable state bitfield. */
--	u32 irq_savedstate;
-+	/* The currently active generic-interrupt mask. */
-+	u32 irq_mask;
- 	/* Link Quality calculation context. */
- 	struct b43_noise_calculation noisecalc;
- 	/* if > 0 MAC is suspended. if == 0 MAC is enabled. */
---- a/drivers/net/wireless/b43/main.c
-+++ b/drivers/net/wireless/b43/main.c
-@@ -673,32 +673,6 @@ static void b43_short_slot_timing_disabl
- 	b43_set_slot_time(dev, 20);
- }
- 
--/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
-- * Returns the _previously_ enabled IRQ mask.
-- */
--static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
--{
--	u32 old_mask;
--
--	old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
--	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
--
--	return old_mask;
--}
--
--/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
-- * Returns the _previously_ enabled IRQ mask.
-- */
--static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
--{
--	u32 old_mask;
--
--	old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
--	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
--
--	return old_mask;
--}
--
- /* Synchronize IRQ top- and bottom-half.
-  * IRQs must be masked before calling this.
-  * This must not be called with the irq_lock held.
-@@ -1593,7 +1567,7 @@ static void handle_irq_beacon(struct b43
- 	/* This is the bottom half of the asynchronous beacon update. */
- 
- 	/* Ignore interrupt in the future. */
--	dev->irq_savedstate &= ~B43_IRQ_BEACON;
-+	dev->irq_mask &= ~B43_IRQ_BEACON;
- 
- 	cmd = b43_read32(dev, B43_MMIO_MACCMD);
- 	beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
-@@ -1602,7 +1576,7 @@ static void handle_irq_beacon(struct b43
- 	/* Schedule interrupt manually, if busy. */
- 	if (beacon0_valid && beacon1_valid) {
- 		b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
--		dev->irq_savedstate |= B43_IRQ_BEACON;
-+		dev->irq_mask |= B43_IRQ_BEACON;
- 		return;
- 	}
- 
-@@ -1641,11 +1615,9 @@ static void b43_beacon_update_trigger_wo
- 	if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
- 		spin_lock_irq(&wl->irq_lock);
- 		/* update beacon right away or defer to irq */
--		dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
- 		handle_irq_beacon(dev);
- 		/* The handler might have updated the IRQ mask. */
--		b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
--			    dev->irq_savedstate);
-+		b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
- 		mmiowb();
- 		spin_unlock_irq(&wl->irq_lock);
- 	}
-@@ -1879,7 +1851,7 @@ static void b43_interrupt_tasklet(struct
- 	if (reason & B43_IRQ_TX_OK)
- 		handle_irq_transmit_status(dev);
- 
--	b43_interrupt_enable(dev, dev->irq_savedstate);
-+	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
- 	mmiowb();
- 	spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
- }
-@@ -1893,7 +1865,9 @@ static void b43_interrupt_ack(struct b43
- 	b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
- 	b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
- 	b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
-+/* Unused ring
- 	b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
-+*/
- }
- 
- /* Interrupt handler top-half */
-@@ -1903,18 +1877,19 @@ static irqreturn_t b43_interrupt_handler
- 	struct b43_wldev *dev = dev_id;
- 	u32 reason;
- 
--	if (!dev)
--		return IRQ_NONE;
-+	B43_WARN_ON(!dev);
- 
- 	spin_lock(&dev->wl->irq_lock);
- 
--	if (b43_status(dev) < B43_STAT_STARTED)
-+	if (unlikely(b43_status(dev) < B43_STAT_STARTED)) {
-+		/* This can only happen on shared IRQ lines. */
- 		goto out;
-+	}
- 	reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
- 	if (reason == 0xffffffff)	/* shared IRQ */
- 		goto out;
- 	ret = IRQ_HANDLED;
--	reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
-+	reason &= dev->irq_mask;
- 	if (!reason)
- 		goto out;
- 
-@@ -1928,16 +1903,18 @@ static irqreturn_t b43_interrupt_handler
- 	    & 0x0001DC00;
- 	dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
- 	    & 0x0000DC00;
-+/* Unused ring
- 	dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
- 	    & 0x0000DC00;
-+*/
- 
- 	b43_interrupt_ack(dev, reason);
- 	/* disable all IRQs. They are enabled again in the bottom half. */
--	dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
-+	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
- 	/* save the reason code and call our bottom half. */
- 	dev->irq_reason = reason;
- 	tasklet_schedule(&dev->isr_tasklet);
--      out:
-+out:
- 	mmiowb();
- 	spin_unlock(&dev->wl->irq_lock);
- 
-@@ -3799,7 +3776,7 @@ static void b43_wireless_core_stop(struc
- 	 * setting the status to INITIALIZED, as the interrupt handler
- 	 * won't care about IRQs then. */
- 	spin_lock_irqsave(&wl->irq_lock, flags);
--	dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
-+	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
- 	b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);	/* flush */
- 	spin_unlock_irqrestore(&wl->irq_lock, flags);
- 	b43_synchronize_irq(dev);
-@@ -3840,7 +3817,7 @@ static int b43_wireless_core_start(struc
- 
- 	/* Start data flow (TX/RX). */
- 	b43_mac_enable(dev);
--	b43_interrupt_enable(dev, dev->irq_savedstate);
-+	b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
- 
- 	/* Start maintainance work */
- 	b43_periodic_tasks_setup(dev);
-@@ -3998,9 +3975,9 @@ static void setup_struct_wldev_for_init(
- 	/* IRQ related flags */
- 	dev->irq_reason = 0;
- 	memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
--	dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
-+	dev->irq_mask = B43_IRQ_MASKTEMPLATE;
- 	if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
--		dev->irq_savedstate &= ~B43_IRQ_PHY_TXERR;
-+		dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
- 
- 	dev->mac_suspended = 1;
- 
diff --git a/package/mac80211/patches/540-b43-Add-fw-capabilities.patch b/package/mac80211/patches/540-b43-Add-fw-capabilities.patch
new file mode 100644
index 000000000..c2320c697
--- /dev/null
+++ b/package/mac80211/patches/540-b43-Add-fw-capabilities.patch
@@ -0,0 +1,198 @@
+Completely untested patch to implement firmware capabilities
+and automagic QoS-disabling.
+
+
+--- a/drivers/net/wireless/b43/b43.h
++++ b/drivers/net/wireless/b43/b43.h
+@@ -163,6 +163,7 @@ enum {
+ #define B43_SHM_SH_WLCOREREV		0x0016	/* 802.11 core revision */
+ #define B43_SHM_SH_PCTLWDPOS		0x0008
+ #define B43_SHM_SH_RXPADOFF		0x0034	/* RX Padding data offset (PIO only) */
++#define B43_SHM_SH_FWCAPA		0x0042	/* Firmware capabilities (Opensource firmware only) */
+ #define B43_SHM_SH_PHYVER		0x0050	/* PHY version */
+ #define B43_SHM_SH_PHYTYPE		0x0052	/* PHY type */
+ #define B43_SHM_SH_ANTSWAP		0x005C	/* Antenna swap threshold */
+@@ -297,6 +298,10 @@ enum {
+ #define B43_HF_MLADVW		0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
+ #define B43_HF_PR45960W		0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
+ 
++/* Firmware capabilities field in SHM (Opensource firmware only) */
++#define B43_FWCAPA_HWCRYPTO	0x0001
++#define B43_FWCAPA_QOS		0x0002
++
+ /* MacFilter offsets. */
+ #define B43_MACFILTER_SELF		0x0000
+ #define B43_MACFILTER_BSSID		0x0003
+@@ -596,6 +601,13 @@ struct b43_wl {
+ 	/* Pointer to the ieee80211 hardware data structure */
+ 	struct ieee80211_hw *hw;
+ 
++	/* The number of queues that were registered with the mac80211 subsystem
++	 * initially. This is a backup copy of hw->queues in case hw->queues has
++	 * to be dynamically lowered at runtime (Firmware does not support QoS).
++	 * hw->queues has to be restored to the original value before unregistering
++	 * from the mac80211 subsystem. */
++	u16 mac80211_initially_registered_queues;
++
+ 	struct mutex mutex;
+ 	spinlock_t irq_lock;
+ 	/* R/W lock for data transmission.
+@@ -752,6 +764,8 @@ struct b43_wldev {
+ 	bool dfq_valid;		/* Directed frame queue valid (IBSS PS mode, ATIM) */
+ 	bool radio_hw_enable;	/* saved state of radio hardware enabled state */
+ 	bool suspend_in_progress;	/* TRUE, if we are in a suspend/resume cycle */
++	bool qos_enabled;		/* TRUE, if QoS is used. */
++	bool hwcrypto_enabled;		/* TRUE, if HW crypto acceleration is enabled. */
+ 
+ 	/* PHY/Radio device. */
+ 	struct b43_phy phy;
+--- a/drivers/net/wireless/b43/dma.c
++++ b/drivers/net/wireless/b43/dma.c
+@@ -1285,7 +1285,7 @@ static struct b43_dmaring *select_ring_b
+ {
+ 	struct b43_dmaring *ring;
+ 
+-	if (b43_modparam_qos) {
++	if (dev->qos_enabled) {
+ 		/* 0 = highest priority */
+ 		switch (queue_prio) {
+ 		default:
+--- a/drivers/net/wireless/b43/main.c
++++ b/drivers/net/wireless/b43/main.c
+@@ -80,8 +80,8 @@ static int modparam_nohwcrypt;
+ module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
+ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
+ 
+-int b43_modparam_qos = 1;
+-module_param_named(qos, b43_modparam_qos, int, 0444);
++static int modparam_qos = 1;
++module_param_named(qos, modparam_qos, int, 0444);
+ MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
+ 
+ static int modparam_btcoex = 1;
+@@ -538,6 +538,13 @@ void b43_hf_write(struct b43_wldev *dev,
+ 	b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
+ }
+ 
++/* Read the firmware capabilities bitmask (Opensource firmware only) */
++static u16 b43_fwcapa_read(struct b43_wldev *dev)
++{
++	B43_WARN_ON(!dev->fw.opensource);
++	return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
++}
++
+ void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
+ {
+ 	u32 low, high;
+@@ -2307,12 +2314,34 @@ static int b43_upload_microcode(struct b
+ 	dev->fw.patch = fwpatch;
+ 	dev->fw.opensource = (fwdate == 0xFFFF);
+ 
++	/* Default to use-all-queues. */
++	dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
++	dev->qos_enabled = !!modparam_qos;
++	/* Default to firmware/hardware crypto acceleration. */
++	dev->hwcrypto_enabled = 1;
++
+ 	if (dev->fw.opensource) {
++		u16 fwcapa;
++
+ 		/* Patchlevel info is encoded in the "time" field. */
+ 		dev->fw.patch = fwtime;
+-		b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
+-			dev->fw.rev, dev->fw.patch,
+-			dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
++		b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
++			dev->fw.rev, dev->fw.patch);
++
++		fwcapa = b43_fwcapa_read(dev);
++		if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
++			b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
++			/* Disable hardware crypto and fall back to software crypto. */
++			dev->hwcrypto_enabled = 0;
++		}
++		if (!(fwcapa & B43_FWCAPA_QOS)) {
++			b43info(dev->wl, "QoS not supported by firmware\n");
++			/* Disable QoS. Tweak hw->queues to 1. It will be restored before
++			 * ieee80211_unregister to make sure the networking core can
++			 * properly free possible resources. */
++			dev->wl->hw->queues = 1;
++			dev->qos_enabled = 0;
++		}
+ 	} else {
+ 		b43info(dev->wl, "Loading firmware version %u.%u "
+ 			"(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
+@@ -3629,7 +3658,7 @@ static int b43_op_set_key(struct ieee802
+ 	if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
+ 		goto out_unlock;
+ 
+-	if (dev->fw.pcm_request_failed) {
++	if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
+ 		/* We don't have firmware for the crypto engine.
+ 		 * Must use software-crypto. */
+ 		err = -EOPNOTSUPP;
+@@ -4737,6 +4766,7 @@ static int b43_wireless_init(struct ssb_
+ 		b43err(NULL, "Could not allocate ieee80211 device\n");
+ 		goto out;
+ 	}
++	wl = hw_to_b43_wl(hw);
+ 
+ 	/* fill hw info */
+ 	hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
+@@ -4750,7 +4780,8 @@ static int b43_wireless_init(struct ssb_
+ 		BIT(NL80211_IFTYPE_WDS) |
+ 		BIT(NL80211_IFTYPE_ADHOC);
+ 
+-	hw->queues = b43_modparam_qos ? 4 : 1;
++	hw->queues = modparam_qos ? 4 : 1;
++	wl->mac80211_initially_registered_queues = hw->queues;
+ 	hw->max_rates = 2;
+ 	SET_IEEE80211_DEV(hw, dev->dev);
+ 	if (is_valid_ether_addr(sprom->et1mac))
+@@ -4758,9 +4789,7 @@ static int b43_wireless_init(struct ssb_
+ 	else
+ 		SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
+ 
+-	/* Get and initialize struct b43_wl */
+-	wl = hw_to_b43_wl(hw);
+-	memset(wl, 0, sizeof(*wl));
++	/* Initialize struct b43_wl */
+ 	wl->hw = hw;
+ 	spin_lock_init(&wl->irq_lock);
+ 	rwlock_init(&wl->tx_lock);
+@@ -4826,8 +4855,13 @@ static void b43_remove(struct ssb_device
+ 	cancel_work_sync(&wldev->restart_work);
+ 
+ 	B43_WARN_ON(!wl);
+-	if (wl->current_dev == wldev)
++	if (wl->current_dev == wldev) {
++		/* Restore the queues count before unregistering, because firmware detect
++		 * might have modified it. Restoring is important, so the networking
++		 * stack can properly free resources. */
++		wl->hw->queues = wl->mac80211_initially_registered_queues;
+ 		ieee80211_unregister_hw(wl->hw);
++	}
+ 
+ 	b43_one_core_detach(dev);
+ 
+--- a/drivers/net/wireless/b43/main.h
++++ b/drivers/net/wireless/b43/main.h
+@@ -39,7 +39,6 @@
+ #define PAD_BYTES(nr_bytes)		P4D_BYTES( __LINE__ , (nr_bytes))
+ 
+ 
+-extern int b43_modparam_qos;
+ extern int b43_modparam_verbose;
+ 
+ /* Logmessage verbosity levels. Update the b43_modparam_verbose helptext, if
+--- a/drivers/net/wireless/b43/pio.c
++++ b/drivers/net/wireless/b43/pio.c
+@@ -313,7 +313,7 @@ static struct b43_pio_txqueue *select_qu
+ {
+ 	struct b43_pio_txqueue *q;
+ 
+-	if (b43_modparam_qos) {
++	if (dev->qos_enabled) {
+ 		/* 0 = highest priority */
+ 		switch (queue_prio) {
+ 		default:
diff --git a/package/mac80211/patches/600-p54usb_without_pm_support.patch b/package/mac80211/patches/600-p54usb_without_pm_support.patch
new file mode 100644
index 000000000..9fa8915c4
--- /dev/null
+++ b/package/mac80211/patches/600-p54usb_without_pm_support.patch
@@ -0,0 +1,16 @@
+Fixes compile error when CONFIG_PM=n is set
+
+--- a/drivers/net/wireless/p54/p54usb.c
++++ b/drivers/net/wireless/p54/p54usb.c
+@@ -919,9 +919,11 @@ static int __devinit p54u_probe(struct u
+ 	priv->common.open = p54u_open;
+ 	priv->common.stop = p54u_stop;
+ 	if (recognized_pipes < P54U_PIPE_NUMBER) {
++#ifdef CONFIG_PM
+ 		/* ISL3887 needs a full reset on resume */
+ 		udev->reset_resume = 1;
+ 		err = p54u_device_reset(dev);
++#endif
+ 
+ 		priv->hw_type = P54U_3887;
+ 		dev->extra_tx_headroom += sizeof(struct lm87_tx_hdr);
author	hauke <hauke@3c298f89-4303-0410-b956-a3cf2f4a3e73>	2009-05-01 13:43:12 +0000
committer	hauke <hauke@3c298f89-4303-0410-b956-a3cf2f4a3e73>	2009-05-01 13:43:12 +0000
commit	80be62eefc21797174acf9bfc9c98a2110b0f856 (patch)
tree	d6243c804c302dcd159ddf3745d614ceb300b6f4 /package
parent	21dcc33bffe7fff29fe97f91c05ec76de920e545 (diff)