[uboot-lantiq]

* rework the arcadyan sku support
* adds a few new boards and switches


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25273 3c298f89-4303-0410-b956-a3cf2f4a3e73

7 files changed, 0 insertions, 1231 deletions

diff --git a/package/uboot-lantiq/files/board/arcadyan/arv4518/Makefile b/package/uboot-lantiq/files/board/arcadyan/arv4518/Makefile
deleted file mode 100644
index 61f383b8d..000000000
--- a/package/uboot-lantiq/files/board/arcadyan/arv4518/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-#COBJS	:= $(BOARD).o
-COBJS-y	+= arv4518.o
-
-SOBJS	= lowlevel_init.o pmuenable.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/package/uboot-lantiq/files/board/arcadyan/arv4518/arv4518.c b/package/uboot-lantiq/files/board/arcadyan/arv4518/arv4518.c
deleted file mode 100644
index c015dd701..000000000
--- a/package/uboot-lantiq/files/board/arcadyan/arv4518/arv4518.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Thomas Langer, Ralph Hempel
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <asm/addrspace.h>
-#include <asm/danube.h>
-#include <asm/reboot.h>
-#include <asm/io.h>
-#if defined(CONFIG_CMD_HTTPD)
-#include <httpd.h>
-#endif
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-
-extern ulong ifx_get_ddr_hz(void);
-extern ulong ifx_get_cpuclk(void);
-
-/* IDs and registers of known external switches */
-#define ID_RTL8306	0x5988
-#define CONFIG_EXTRA_SWITCH 1
-void _machine_restart(void)
-{
-	*DANUBE_RCU_RST_REQ |=1<<30;
-}
-
-#ifdef CONFIG_SYS_RAMBOOT
-phys_size_t initdram(int board_type)
-{
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
-}
-#elif defined(CONFIG_USE_DDR_RAM)
-phys_size_t initdram(int board_type)
-{
-	return (CONFIG_SYS_MAX_RAM);
-}
-#else
-
-static ulong max_sdram_size(void)     /* per Chip Select */
-{
-	/* The only supported SDRAM data width is 16bit.
-	 */
-#define CFG_DW	4
-
-	/* The only supported number of SDRAM banks is 4.
-	 */
-#define CFG_NB	4
-
-	ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
-	int   cols   = cfgpb0 & 0xF;
-	int   rows   = (cfgpb0 & 0xF0) >> 4;
-	ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
-
-	return size;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'.
- */
-
-static long int dram_size(long int *base, long int maxsize)
-{
-	volatile long int *addr;
-	ulong cnt, val;
-	ulong save[32];			/* to make test non-destructive */
-	unsigned char i = 0;
-
-	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		save[i++] = *addr;
-		*addr = ~cnt;
-	}
-
-	/* write 0 to base address */
-	addr = base;
-	save[i] = *addr;
-	*addr = 0;
-
-	/* check at base address */
-	if ((val = *addr) != 0) {
-		*addr = save[i];
-		return (0);
-	}
-
-	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
-		addr = base + cnt;		/* pointer arith! */
-
-		val = *addr;
-		*addr = save[--i];
-
-		if (val != (~cnt)) {
-			return (cnt * sizeof (long));
-		}
-	}
-	return (maxsize);
-}
-
-phys_size_t initdram(int board_type)
-{
-	int   rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
-	ulong size, max_size       = 0;
-	ulong our_address;
-
-	/* load t9 into our_address */
-	asm volatile ("move %0, $25" : "=r" (our_address) :);
-
-	/* Can't probe for RAM size unless we are running from Flash.
-	 * find out whether running from DRAM or Flash.
-	 */
-	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
-	{
-		return max_sdram_size();
-	}
-
-	for (cols = 0x8; cols <= 0xC; cols++)
-	{
-		for (rows = 0xB; rows <= 0xD; rows++)
-		{
-			*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
-			                          (rows << 4) | cols;
-			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-			                          max_sdram_size());
-
-			if (size > max_size)
-			{
-				best_val = *DANUBE_SDRAM_MC_CFGPB0;
-				max_size = size;
-			}
-		}
-	}
-
-	*DANUBE_SDRAM_MC_CFGPB0 = best_val;
-	return max_size;
-}
-#endif
-
-int checkboard (void)
-{
-	unsigned long chipid = *DANUBE_MPS_CHIPID;
-	int part_num;
-
-	puts ("Board: ");
-
-	part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
-	switch (part_num)
-	{
-	case 0x129:
-	case 0x12D:
-	case 0x12b: 
-		puts("Danube/Twinpass/Vinax-VE ");
-		break;
-	default:
-		printf ("unknown, chip part number 0x%03X ", part_num);
-		break;
-	}
-	printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
-
-	printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
-	printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
-
-	return 0;
-}
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-int board_early_init_f(void)
-{
-#ifdef CONFIG_EBU_ADDSEL0
-	(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
-#endif
-#ifdef CONFIG_EBU_ADDSEL1
-	(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
-#endif
-#ifdef CONFIG_EBU_ADDSEL2
-	(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
-#endif
-#ifdef CONFIG_EBU_ADDSEL3
-	(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
-#endif
-#ifdef CONFIG_EBU_BUSCON0
-	(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
-#endif
-#ifdef CONFIG_EBU_BUSCON1
-	(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
-#endif
-#ifdef CONFIG_EBU_BUSCON2
-	(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
-#endif
-#ifdef CONFIG_EBU_BUSCON3
-	(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
-#endif
-
-	return 0;
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-
-#ifdef CONFIG_EXTRA_SWITCH
-static int external_switch_init(void)
-{
-	unsigned short chipid;
-	static char * const name = "lq_cpe_eth";
-
-	/* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
-	udelay(100000);
-
-	puts("\nsearching for rtl8306 switch ... ");
-	if (miiphy_read(name, 4, 30, &chipid) == 0) {
-		puts("s1\n");
-		if (chipid == ID_RTL8306) {
-			puts("found");
-			/* set led mode */
-			miiphy_write(name, 0, 19, 0xffff);
-			/* magic */
-			miiphy_write(name, 4, 22, 0x877f);
-			puts("\n");
-			return 0;
-		}
-		puts("failed\n");
-	}
-	puts("\nno known switch found ... \n");
-
-	return 0;
-}
-#endif /* CONFIG_EXTRA_SWITCH */
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_IFX_ETOP)
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-               eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
-
-	*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
-	*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
-
-	if (lq_eth_initialize(bis))
-		return -1;
-
-	*DANUBE_RCU_RST_REQ |=1;
-	udelay(200000);
-	*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
-	udelay(1000);
-
-#ifdef CONFIG_EXTRA_SWITCH
-	if (external_switch_init()<0)
-		return -1;
-#endif /* CONFIG_EXTRA_SWITCH */
-#endif /* CONFIG_IFX_ETOP */
-
-	return 0;
-}
-
-#if defined(CONFIG_CMD_HTTPD)
-int do_http_upgrade(const unsigned char *data, const ulong size)
-{
-	char buf[128];
-
-	if(getenv ("ram_addr") == NULL)
-		return -1;
-	if(getenv ("kernel_addr") == NULL)
-		return -1;
-	/* check the image */
-	if(run_command("imi ${ram_addr}", 0) < 0) {
-		return -1;
-	}
-	/* write the image to the flash */
-	puts("http ugrade ...\n");
-	sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
-	return run_command(buf, 0);
-}
-
-int do_http_progress(const int state)
-{
-	/* toggle LED's here */
-	switch(state) {
-		case HTTP_PROGRESS_START:
-		puts("http start\n");
-		break;
-		case HTTP_PROGRESS_TIMEOUT:
-		puts(".");
-		break;
-		case HTTP_PROGRESS_UPLOAD_READY:
-		puts("http upload ready\n");
-		break;
-		case HTTP_PROGRESS_UGRADE_READY:
-		puts("http ugrade ready\n");
-		break;
-		case HTTP_PROGRESS_UGRADE_FAILED:
-		puts("http ugrade failed\n");
-		break;
-	}
-	return 0;
-}
-
-unsigned long do_http_tmp_address(void)
-{
-	char *s = getenv ("ram_addr");
-	if (s) {
-		ulong tmp = simple_strtoul (s, NULL, 16);
-		return tmp;
-	}
-	return 0 /*0x80a00000*/;
-}
-
-#endif
diff --git a/package/uboot-lantiq/files/board/arcadyan/arv4518/config.mk b/package/uboot-lantiq/files/board/arcadyan/arv4518/config.mk
deleted file mode 100644
index c0e5d8244..000000000
--- a/package/uboot-lantiq/files/board/arcadyan/arv4518/config.mk
+++ /dev/null
@@ -1,60 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Danube board with MIPS 24Kc CPU core
-#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifdef CONFIG_LZMA_BOOTSTRAP
-
-ifdef BUILD_BOOTSTRAP
-
-$(info BUILD_BOOTSTRAP )
-#TEXT_BASE = 0xB0000000
-TEXT_BASE = 0x80010000
-
-else # BUILD_BOOTSTRAP
-
-ifndef TEXT_BASE
-$(info redefine TEXT_BASE = 0x80040000 )
-TEXT_BASE = 0x80040000
-endif
-
-endif # BUILD_BOOTSTRAP
-
-else
-
-ifdef BUILD_BOOTSTRAP
-$(error BUILD_BOOTSTRAP but not enabled in config)
-endif
-
-ifndef TEXT_BASE
-## Standard: boot from ebu
-$(info redefine TEXT_BASE = 0xB0000000 )
-TEXT_BASE = 0xB0000000
-## For testing: boot from RAM
-# TEXT_BASE = 0x80100000
-endif
-
-endif # CONFIG_LZMA_BOOTSTRAP
diff --git a/package/uboot-lantiq/files/board/arcadyan/arv4518/ddr_settings.h b/package/uboot-lantiq/files/board/arcadyan/arv4518/ddr_settings.h
deleted file mode 100644
index 4df6f1170..000000000
--- a/package/uboot-lantiq/files/board/arcadyan/arv4518/ddr_settings.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x605
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x70a
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xc02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x130  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xd
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA03  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1b00
-#define MC_DC22_VALUE	0x1b1b
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x59   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x510
-#define MC_DC29_VALUE	0x4e20
-#define MC_DC30_VALUE	0x8235
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x500
-#define MC_DC46_VALUE	0x0
diff --git a/package/uboot-lantiq/files/board/arcadyan/arv4518/lowlevel_init.S b/package/uboot-lantiq/files/board/arcadyan/arv4518/lowlevel_init.S
deleted file mode 100644
index c4570d015..000000000
--- a/package/uboot-lantiq/files/board/arcadyan/arv4518/lowlevel_init.S
+++ /dev/null
@@ -1,622 +0,0 @@
-/*
- *  Memory sub-system initialization code for Danube board.
- *  Andre Messerschmidt
- *  Copyright (c) 2005	Infineon Technologies AG
- *
- *  Based on Inca-IP code
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/* History:
-      peng liu May 25, 2006, for PLL setting after reset, 05252006
- */
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#if 0
-
-#if defined(CONFIG_USE_DDR_RAM)
-
-#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
-#include "ddr_settings_r111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
-#include "ddr_settings_r166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
-#include "ddr_settings_e111.h"
-#define DDR111
-#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
-#include "ddr_settings_e166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
-#include "ddr_settings_PROMOSDDR400.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
-#include "ddr_settings_Samsung_166.h"
-#define DDR166
-#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
-#include "ddr_settings_psc_166.h"
-#define DDR166
-#else
-#warning "missing definition for ddr_settings.h, use default!"
-#include "ddr_settings.h"
-#endif
-#endif /* CONFIG_USE_DDR_RAM */
-
-#else
-
-#include "ddr_settings.h"
-#define DDR166
-
-#endif
-
-#if defined(CONFIG_USE_DDR_RAM) &&  !defined(MC_DC0_VALUE)
-#error "missing include of ddr_settings.h"
-#endif
-
-#define EBU_MODUL_BASE		0xBE105300
-#define EBU_CLC(value)		0x0000(value)
-#define EBU_CON(value)		0x0010(value)
-#define EBU_ADDSEL0(value)	0x0020(value)
-#define EBU_ADDSEL1(value)	0x0024(value)
-#define EBU_ADDSEL2(value)	0x0028(value)
-#define EBU_ADDSEL3(value)	0x002C(value)
-#define EBU_BUSCON0(value)	0x0060(value)
-#define EBU_BUSCON1(value)	0x0064(value)
-#define EBU_BUSCON2(value)	0x0068(value)
-#define EBU_BUSCON3(value)	0x006C(value)
-
-#define MC_MODUL_BASE		0xBF800000
-#define MC_ERRCAUSE(value)	0x0010(value)
-#define MC_ERRADDR(value)	0x0020(value)
-#define MC_CON(value)		0x0060(value)
-
-#define MC_SRAM_ENABLE		0x00000004
-#define MC_SDRAM_ENABLE		0x00000002
-#define MC_DDRRAM_ENABLE	0x00000001
-
-#define MC_SDR_MODUL_BASE	0xBF800200
-#define MC_IOGP(value)		0x0000(value)
-#define MC_CTRLENA(value)	0x0010(value)
-#define MC_MRSCODE(value)	0x0020(value)
-#define MC_CFGDW(value)		0x0030(value)
-#define MC_CFGPB0(value)	0x0040(value)
-#define MC_LATENCY(value)	0x0080(value)
-#define MC_TREFRESH(value)	0x0090(value)
-#define MC_SELFRFSH(value)	0x00A0(value)
-
-#define MC_DDR_MODUL_BASE	0xBF801000
-#define MC_DC00(value)		0x0000(value)
-#define MC_DC01(value)		0x0010(value)
-#define MC_DC02(value)		0x0020(value)
-#define MC_DC03(value)		0x0030(value)
-#define MC_DC04(value)		0x0040(value)
-#define MC_DC05(value)		0x0050(value)
-#define MC_DC06(value)		0x0060(value)
-#define MC_DC07(value)		0x0070(value)
-#define MC_DC08(value)		0x0080(value)
-#define MC_DC09(value)		0x0090(value)
-#define MC_DC10(value)		0x00A0(value)
-#define MC_DC11(value)		0x00B0(value)
-#define MC_DC12(value)		0x00C0(value)
-#define MC_DC13(value)		0x00D0(value)
-#define MC_DC14(value)		0x00E0(value)
-#define MC_DC15(value)		0x00F0(value)
-#define MC_DC16(value)		0x0100(value)
-#define MC_DC17(value)		0x0110(value)
-#define MC_DC18(value)		0x0120(value)
-#define MC_DC19(value)		0x0130(value)
-#define MC_DC20(value)		0x0140(value)
-#define MC_DC21(value)		0x0150(value)
-#define MC_DC22(value)		0x0160(value)
-#define MC_DC23(value)		0x0170(value)
-#define MC_DC24(value)		0x0180(value)
-#define MC_DC25(value)		0x0190(value)
-#define MC_DC26(value)		0x01A0(value)
-#define MC_DC27(value)		0x01B0(value)
-#define MC_DC28(value)		0x01C0(value)
-#define MC_DC29(value)		0x01D0(value)
-#define MC_DC30(value)		0x01E0(value)
-#define MC_DC31(value)		0x01F0(value)
-#define MC_DC32(value)		0x0200(value)
-#define MC_DC33(value)		0x0210(value)
-#define MC_DC34(value)		0x0220(value)
-#define MC_DC35(value)		0x0230(value)
-#define MC_DC36(value)		0x0240(value)
-#define MC_DC37(value)		0x0250(value)
-#define MC_DC38(value)		0x0260(value)
-#define MC_DC39(value)		0x0270(value)
-#define MC_DC40(value)		0x0280(value)
-#define MC_DC41(value)		0x0290(value)
-#define MC_DC42(value)		0x02A0(value)
-#define MC_DC43(value)		0x02B0(value)
-#define MC_DC44(value)		0x02C0(value)
-#define MC_DC45(value)		0x02D0(value)
-#define MC_DC46(value)		0x02E0(value)
-
-#define RCU_OFFSET  0xBF203000
-#define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
-#define RCU_STS          (RCU_OFFSET + 0x0014)
-
-#define CGU_OFFSET  0xBF103000
-#define  PLL0_CFG     (CGU_OFFSET + 0x0004)
-#define  PLL1_CFG     (CGU_OFFSET + 0x0008)
-#define  PLL2_CFG     (CGU_OFFSET + 0x000C)
-#define  CGU_SYS      (CGU_OFFSET + 0x0010)
-#define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
-#define  IF_CLK       (CGU_OFFSET + 0x0018)
-#define  CGU_SMD      (CGU_OFFSET + 0x0020)
-#define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
-#define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
-#define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
-#define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
-#define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
-#define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
-#define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
-
-//05252006
-#define  pll0_35MHz_CONFIG 0x9D861059
-#define  pll1_35MHz_CONFIG 0x1A260CD9
-#define  pll2_35MHz_CONFIG 0x8000f1e5
-#define  pll0_36MHz_CONFIG 0x1000125D
-#define  pll1_36MHz_CONFIG 0x1B1E0C99
-#define  pll2_36MHz_CONFIG 0x8002f2a1
-//05252006
-
-//06063001-joelin disable the PCI CFRAME mask -start
-/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
-But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
-
-The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
-The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
-*/
-#define PCI_CR_PR_OFFSET  0xBE105400
-#define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
-#define PCI_CONFIG_SPACE  0xB7000000
-#define CS_CFM		(PCI_CONFIG_SPACE + 0x6C)
-//06063001-joelin disable the PCI CFRAME mask -end
-	.set	noreorder
-
-
-/*
- * void ebu_init(void)
- */
-	.globl	ebu_init
-	.ent	ebu_init
-ebu_init:
-
-#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
-	defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
-	defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
-	defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
-
-	li	t1, EBU_MODUL_BASE
-#if defined(CONFIG_EBU_ADDSEL0)
-	li	t2, CONFIG_EBU_ADDSEL0
-	sw	t2, EBU_ADDSEL0(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL1)
-	li	t2, CONFIG_EBU_ADDSEL1
-	sw	t2, EBU_ADDSEL1(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL2)
-	li	t2, CONFIG_EBU_ADDSEL2
-	sw	t2, EBU_ADDSEL2(t1)
-#endif
-#if defined(CONFIG_EBU_ADDSEL3)
-	li	t2, CONFIG_EBU_ADDSEL3
-	sw	t2, EBU_ADDSEL3(t1)
-#endif
-
-#if defined(CONFIG_EBU_BUSCON0)
-	li	t2, CONFIG_EBU_BUSCON0
-	sw	t2, EBU_BUSCON0(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON1)
-	li	t2, CONFIG_EBU_BUSCON1
-	sw	t2, EBU_BUSCON1(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON2)
-	li	t2, CONFIG_EBU_BUSCON2
-	sw	t2, EBU_BUSCON2(t1)
-#endif
-#if defined(CONFIG_EBU_BUSCON3)
-	li	t2, CONFIG_EBU_BUSCON3
-	sw	t2, EBU_BUSCON3(t1)
-#endif
-
-#endif
-
-	j	ra
-	nop
-
-	.end	ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-	.globl	cgu_init
-	.ent	cgu_init
-cgu_init:
-	li  t2, CGU_SYS
-	lw  t2,0(t2)
-	beq t2,a0,freq_up2date
-	nop
-
-	li  t2, RCU_STS
-	lw  t2, 0(t2)
-	and t2,0x00020000
-	beq t2,0x00020000,boot_36MHZ
-	nop
-//05252006
-	li  t1, PLL0_CFG
-	li  t2, pll0_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_35MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-	b   wait_reset
-	nop
-boot_36MHZ:
-	li  t1, PLL0_CFG
-	li  t2, pll0_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL1_CFG
-	li  t2, pll1_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, PLL2_CFG
-	li  t2, pll2_36MHz_CONFIG
-	sw	t2,0(t1)
-	li  t1, CGU_SYS
-	sw	a0,0(t1)
-	li  t1, RCU_RST_REQ
-	li  t2, 0x40000008
-	sw	t2,0(t1)
-//05252006
-
-wait_reset:
-	b   wait_reset
-	nop
-freq_up2date:
-	j ra
-	nop
-
-	.end	cgu_init
-
-#ifndef CONFIG_USE_DDR_RAM
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	sdram_init
-	.ent	sdram_init
-sdram_init:
-
-	/* SDRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable SDRAM module in memory controller */
-	li	t3, MC_SDRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_SDR_MODUL_BASE
-
-	/* disable the controller */
-	li	t2, 0
-	sw	t2, MC_CTRLENA(t1)
-
-	li	t2, 0x822
-	sw	t2, MC_IOGP(t1)
-
-	li	t2, 0x2
-	sw	t2, MC_CFGDW(t1)
-
-	/* Set CAS Latency */
-	li	t2, 0x00000020
-	sw	t2, MC_MRSCODE(t1)
-
-	/* Set CS0 to SDRAM parameters */
-	li	t2, 0x000014d8
-	sw	t2, MC_CFGPB0(t1)
-
-	/* Set SDRAM latency parameters */
-	li  	t2, 0x00036325;   /* BC PC100 */
-	sw	t2, MC_LATENCY(t1)
-
-	/* Set SDRAM refresh rate */
-	li	t2, 0x00000C30
-	sw	t2, MC_TREFRESH(t1)
-
-	/* Clear Power-down registers */
-	sw	zero, MC_SELFRFSH(t1)
-
-	/* Finally enable the controller */
-	li	t2, 1
-	sw	t2, MC_CTRLENA(t1)
-
-	j	ra
-	nop
-
-	.end	sdram_init
-
-#endif /* !CONFIG_USE_DDR_RAM */
-
-#ifdef CONFIG_USE_DDR_RAM
-/*
- * void ddrram_init(long)
- *
- * a0 has the clock value
- */
-	.globl	ddrram_init
-	.ent	ddrram_init
-ddrram_init:
-
-	/* DDR-DRAM Initialization
-	 */
-	li	t1, MC_MODUL_BASE
-
-	/* Clear Error log registers */
-	sw	zero, MC_ERRCAUSE(t1)
-	sw	zero, MC_ERRADDR(t1)
-
-	/* Enable DDR module in memory controller */
-	li	t3, MC_DDRRAM_ENABLE
-	lw	t2, MC_CON(t1)
-	or	t3, t2, t3
-	sw	t3, MC_CON(t1)
-
-	li	t1, MC_DDR_MODUL_BASE
-
-	/* Write configuration to DDR controller registers */
-	li	t2, MC_DC0_VALUE
-	sw	t2, MC_DC00(t1)
-
-	li	t2, MC_DC1_VALUE
-	sw	t2, MC_DC01(t1)
-
-	li	t2, MC_DC2_VALUE
-	sw	t2, MC_DC02(t1)
-
-	li	t2, MC_DC3_VALUE
-	sw	t2, MC_DC03(t1)
-
-	li	t2, MC_DC4_VALUE
-	sw	t2, MC_DC04(t1)
-
-	li	t2, MC_DC5_VALUE
-	sw	t2, MC_DC05(t1)
-
-	li	t2, MC_DC6_VALUE
-	sw	t2, MC_DC06(t1)
-
-	li	t2, MC_DC7_VALUE
-	sw	t2, MC_DC07(t1)
-
-	li	t2, MC_DC8_VALUE
-	sw	t2, MC_DC08(t1)
-
-	li	t2, MC_DC9_VALUE
-	sw	t2, MC_DC09(t1)
-
-	li	t2, MC_DC10_VALUE
-	sw	t2, MC_DC10(t1)
-
-	li	t2, MC_DC11_VALUE
-	sw	t2, MC_DC11(t1)
-
-	li	t2, MC_DC12_VALUE
-	sw	t2, MC_DC12(t1)
-
-	li	t2, MC_DC13_VALUE
-	sw	t2, MC_DC13(t1)
-
-	li	t2, MC_DC14_VALUE
-	sw	t2, MC_DC14(t1)
-
-	li	t2, MC_DC15_VALUE
-	sw	t2, MC_DC15(t1)
-
-	li	t2, MC_DC16_VALUE
-	sw	t2, MC_DC16(t1)
-
-	li	t2, MC_DC17_VALUE
-	sw	t2, MC_DC17(t1)
-
-	li	t2, MC_DC18_VALUE
-	sw	t2, MC_DC18(t1)
-
-	li	t2, MC_DC19_VALUE
-	sw	t2, MC_DC19(t1)
-
-	li	t2, MC_DC20_VALUE
-	sw	t2, MC_DC20(t1)
-
-	li	t2, MC_DC21_VALUE
-	sw	t2, MC_DC21(t1)
-
-	li	t2, MC_DC22_VALUE
-	sw	t2, MC_DC22(t1)
-
-	li	t2, MC_DC23_VALUE
-	sw	t2, MC_DC23(t1)
-
-	li	t2, MC_DC24_VALUE
-	sw	t2, MC_DC24(t1)
-
-	li	t2, MC_DC25_VALUE
-	sw	t2, MC_DC25(t1)
-
-	li	t2, MC_DC26_VALUE
-	sw	t2, MC_DC26(t1)
-
-	li	t2, MC_DC27_VALUE
-	sw	t2, MC_DC27(t1)
-
-	li	t2, MC_DC28_VALUE
-	sw	t2, MC_DC28(t1)
-
-	li	t2, MC_DC29_VALUE
-	sw	t2, MC_DC29(t1)
-
-	li	t2, MC_DC30_VALUE
-	sw	t2, MC_DC30(t1)
-
-	li	t2, MC_DC31_VALUE
-	sw	t2, MC_DC31(t1)
-
-	li	t2, MC_DC32_VALUE
-	sw	t2, MC_DC32(t1)
-
-	li	t2, MC_DC33_VALUE
-	sw	t2, MC_DC33(t1)
-
-	li	t2, MC_DC34_VALUE
-	sw	t2, MC_DC34(t1)
-
-	li	t2, MC_DC35_VALUE
-	sw	t2, MC_DC35(t1)
-
-	li	t2, MC_DC36_VALUE
-	sw	t2, MC_DC36(t1)
-
-	li	t2, MC_DC37_VALUE
-	sw	t2, MC_DC37(t1)
-
-	li	t2, MC_DC38_VALUE
-	sw	t2, MC_DC38(t1)
-
-	li	t2, MC_DC39_VALUE
-	sw	t2, MC_DC39(t1)
-
-	li	t2, MC_DC40_VALUE
-	sw	t2, MC_DC40(t1)
-
-	li	t2, MC_DC41_VALUE
-	sw	t2, MC_DC41(t1)
-
-	li	t2, MC_DC42_VALUE
-	sw	t2, MC_DC42(t1)
-
-	li	t2, MC_DC43_VALUE
-	sw	t2, MC_DC43(t1)
-
-	li	t2, MC_DC44_VALUE
-	sw	t2, MC_DC44(t1)
-
-	li	t2, MC_DC45_VALUE
-	sw	t2, MC_DC45(t1)
-
-	li	t2, MC_DC46_VALUE
-	sw	t2, MC_DC46(t1)
-
-	li	t2, 0x00000100
-	sw	t2, MC_DC03(t1)
-
-	j	ra
-	nop
-
-	.end	ddrram_init
-#endif /* CONFIG_USE_DDR_RAM */
-
-	.globl	lowlevel_init
-	.ent	lowlevel_init
-lowlevel_init:
-	/* EBU, CGU and SDRAM/DDR-RAM Initialization.
-	 */
-	move	t0, ra
-	/* We rely on the fact that non of the following ..._init() functions
-	 * modify t0
-	 */
-#if defined(CONFIG_SYS_EBU_BOOT)
-#if defined(DDR166)
-	/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
-	li  a0,0xe8
-#elif defined(DDR133)
-	/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
-	li  a0,0xe9
-#else /* defined(DDR111) */
-	/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
-	li  a0,0xea
-#endif
-	bal	cgu_init
-	nop
-#endif /* CONFIG_SYS_EBU_BOOT */
-
-	bal	ebu_init
-	nop
-
-//06063001-joelin disable the PCI CFRAME mask-start
-#ifdef DISABLE_CFRAME
-	li  t1, PCI_CR_PCI	//mw bf103034 80000000
-	li  t2, 0x80000000
-	sw	t2,0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x103
-	sw  t2,0(t1)
-
-	li  t1, CS_CFM			//mw b700006c 0
-	li  t2, 0x00
-	sw  t2, 0(t1)
-
-	li  t1, PCI_CR_PCI_MOD_REG	//mw be105430 103
-	li  t2, 0x1000103
-	sw  t2, 0(t1)
-#endif
-//06063001-joelin disable the PCI CFRAME mask-end
-
-#ifdef CONFIG_SYS_EBU_BOOT
-#ifndef CONFIG_SYS_RAMBOOT
-#ifdef CONFIG_USE_DDR_RAM
-	bal	ddrram_init
-	nop
-#else
-	bal	sdram_init
-	nop
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-#endif /* CONFIG_SYS_EBU_BOOT */
-
-	move	ra, t0
-	j	ra
-	nop
-
-	.end	lowlevel_init
diff --git a/package/uboot-lantiq/files/board/arcadyan/arv4518/pmuenable.S b/package/uboot-lantiq/files/board/arcadyan/arv4518/pmuenable.S
deleted file mode 100644
index e0d7971d8..000000000
--- a/package/uboot-lantiq/files/board/arcadyan/arv4518/pmuenable.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  Power Management unit initialization code for AMAZON development board.
- *
- *  Copyright (c) 2003	Ou Ke, Infineon.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#define PMU_PWDCR 		0xBF10201C
-#define PMU_SR			0xBF102020
-
-	.globl	pmuenable
-
-pmuenable:
-	li      t0, PMU_PWDCR
-	li      t1, 0x2		/* enable everything */
-	sw      t1, 0(t0)
-#if 0
-1:
-	li	t0, PMU_SR
-	lw      t2, 0(t0)
-	bne     t1, t2, 1b
-	nop
-#endif
-	j	ra
-	nop
-
-
diff --git a/package/uboot-lantiq/files/board/arcadyan/arv4518/u-boot.lds b/package/uboot-lantiq/files/board/arcadyan/arv4518/u-boot.lds
deleted file mode 100644
index 9a6cd1b8a..000000000
--- a/package/uboot-lantiq/files/board/arcadyan/arv4518/u-boot.lds
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text       :
-	{
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data  : { *(.data) }
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-	  __got_start = .;
-	  *(.got)
-	  __got_end = .;
-	}
-
-	.sdata  : { *(.sdata) }
-
-	.u_boot_cmd : {
-	  __u_boot_cmd_start = .;
-	  *(.u_boot_cmd)
-	  __u_boot_cmd_end = .;
-	}
-
-	uboot_end_data = .;
-	num_got_entries = (__got_end - __got_start) >> 2;
-
-	. = ALIGN(4);
-	.sbss (NOLOAD)  : { *(.sbss) }
-	.bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
-	uboot_end = .;
-}