drop uboot-ifxmips, use uboot-lantiq instead

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25294 3c298f89-4303-0410-b956-a3cf2f4a3e73

6 files changed, 0 insertions, 507 deletions

diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/Makefile b/package/uboot-ifxmips/files/cpu/mips/danube/Makefile
deleted file mode 100644
index 6f7b5dc68..000000000
--- a/package/uboot-ifxmips/files/cpu/mips/danube/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-#########################################################################
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-COBJS	= ifx_asc.o ifx_clock.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c
deleted file mode 100644
index 52c6cb271..000000000
--- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*****************************************************************************
- * DANUBE BootROM
- * Copyright (c) 2005, Infineon Technologies AG, All rights reserved
- * IFAP DC COM SD
- *****************************************************************************/
-
-#include <config.h>
-//#include <lib.h>
-#include <asm/danube.h>
-#include <asm/addrspace.h>
-#include <asm/ifx_asc.h>
-
-
-#define ASC_FIFO_PRESENT
-#define SET_BIT(reg, mask)                  reg |= (mask)
-#define CLEAR_BIT(reg, mask)                reg &= (~mask)
-#define CLEAR_BITS(reg, mask)               CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask)                 SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val)   {reg &= (~mask); reg |= (val << off);}
-
-
-typedef unsigned char u8;
-typedef unsigned short u16;
-typedef unsigned long u32;
-typedef signed   long s32;
-typedef unsigned int uint;
-typedef unsigned long ulong;
-typedef volatile unsigned short vuint;
-
-
-
-void serial_setbrg (void);
-
-/*TODO: undefine this !!!*/
-#undef DEBUG_ASC_RAW
-#ifdef DEBUG_ASC_RAW
-#define DEBUG_ASC_RAW_RX_BUF		0xA0800000
-#define DEBUG_ASC_RAW_TX_BUF		0xA0900000
-#endif
-
-static volatile DanubeAsc_t *pAsc = (DanubeAsc_t *)DANUBE_ASC1;
-
-typedef struct{
-  u16 fdv; /* 0~511 fractional divider value*/
-  u16 reload; /* 13 bit reload value*/
-} ifx_asc_baud_reg_t;
-
-#ifdef ON_VENUS
-/*9600 @1.25M rel 00.08*/
-//#define FDV 503
-//#define RELOAD 7
-/*9600 @0.625M rel final00.01 & rtl_freeze*/
-#define FDV 503
-#define RELOAD 3
-/* first index is DDR_SEL, second index is FPI_SEL */
-#endif
-static ifx_asc_baud_reg_t g_danube_asc_baud[4][2] = 
-{
-#ifdef ON_VENUS
-     {{503,3},{503,3}},   /* 1152000 @ 166.67M and half*/
-      {{503,3},{503,3}},   /* 1152000 @ 133.3M  and half*/
-      {{503,3},{503,3}},   /* 1152000 @ 111.11M and half*/
-      {{503.3},{503,3}}    /* 1152000 @ 83.33M  and half*/
-#else
-/*  TAPEOUT table */
-     {{436,76},{419,36}},   /* 1152000 @ 166.67M and half*/
-      {{453,63},{453,31}},   /* 1152000 @ 133.3M  and half*/
-      {{501,58},{510,29}},   /* 1152000 @ 111.11M and half*/
-      {{419.36},{453,19}}    /* 1152000 @ 83.33M  and half*/
-#endif
-};
-/******************************************************************************
-*
-* asc_init - initialize a Danube ASC channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-int serial_init (void)
-{
-
-	/* and we have to set CLC register*/
-	CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
-	SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
-
-	/* initialy we are in async mode */
-	pAsc->asc_con = ASCCON_M_8ASYNC;
-
-	/* select input port */
-	pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
-
-	/* TXFIFO's filling level */
-	SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
-			ASCTXFCON_TXFITLOFF, DANUBEASC_TXFIFO_FL);
-	/* enable TXFIFO */
-	SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
-
-	/* RXFIFO's filling level */
-	SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
-			ASCRXFCON_RXFITLOFF, DANUBEASC_RXFIFO_FL);
-	/* enable RXFIFO */
-	SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
-
-	/* set baud rate */
-	serial_setbrg();
-
-	/* enable error signals &  Receiver enable  */
-	SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
-
-	return 0;
-}
-
-void serial_setbrg (void)
-{
-	u32 uiReloadValue, fdv;
-
-#if defined(ON_IKOS)
-	/*1200 @77K */
-	fdv=472;
-	uiReloadValue=5;
-#else
-	/*venus & tapeout */
-  u32 ddr_sel,fpi_sel;
-  ddr_sel = (* DANUBE_CGU_SYS) & 0x3;
-  fpi_sel = ((* DANUBE_CGU_SYS) & 0x40)?1:0;
-	fdv= g_danube_asc_baud[ddr_sel][fpi_sel].fdv;
-	uiReloadValue=g_danube_asc_baud[ddr_sel][fpi_sel].reload;
-#endif	//ON_IKOS
-	/* Disable Baud Rate Generator; BG should only be written when R=0 */
-	CLEAR_BIT(pAsc->asc_con, ASCCON_R);
-
-	/* Enable Fractional Divider */
-	SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
-
-	/* Set fractional divider value */
-	pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
-
-	/* Set reload value in BG */
-	pAsc->asc_bg = uiReloadValue;
-
-	/* Enable Baud Rate Generator */
-	SET_BIT(pAsc->asc_con, ASCCON_R);           /* R = 1 */
-}
-
-
-void serial_putc (const char c)
-{
-	u32 txFl = 0;
-#ifdef DEBUG_ASC_RAW
-	static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
-	*debug++=c;
-#endif
-	if (c == '\n')
-		serial_putc ('\r');
-	/* check do we have a free space in the TX FIFO */
-	/* get current filling level */
-	do
-	{
-		txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
-	}
-	while ( txFl == DANUBEASC_TXFIFO_FULL );
-
-	pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
-
-	/* check for errors */
-	if ( pAsc->asc_state & ASCSTATE_TOE )
-	{
-		SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_CLRTOE);
-		return;
-	}
-}
-
-void serial_puts (const char *s)
-{
-	while (*s)
-	{
-		serial_putc (*s++);
-	}
-}
-
-int asc_inb(int timeout)
-{
-	u32 symbol_mask;
-	char c;
-	while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) {
-	}
-	symbol_mask = ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
-	c = (char)(pAsc->asc_rbuf & symbol_mask);
-	return (c);
-}
-
-int serial_getc (void)
-{
-	char c;
-	while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 );
-	c = (char)(pAsc->asc_rbuf & 0xff);
-
-#ifdef 	DEBUG_ASC_RAW
-	static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
-	*debug++=c;
-#endif
-	return c;
-}
-
-
-
-int serial_tstc (void)
-{
-         int res = 1;
-
-#ifdef ASC_FIFO_PRESENT
-    if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
-    {
-        res = 0;
-    }
-#else
-    if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
-			    					FBS_ISR_AR))
-    
-    {
-        res = 0;
-    }
-#endif
-#if 0
-    else if ( pAsc->asc_con & ASCCON_FE )
-    {
-        SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
-        res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_PE )
-    {
-        SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
-        res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_OE )
-    {
-        SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
-        res = 0;
-    }
-#endif
-  return res;
-}
-
-
-int serial_start(void)
-{
-   return 1;
-}
-
-int serial_stop(void)
-{
-   return 1;
-}
diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S
deleted file mode 100644
index fc482dcd6..000000000
--- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S
+++ /dev/null
@@ -1,60 +0,0 @@
-
-#define IFX_CACHE_EXTRA_INVALID_TAG						\
-	mtc0	zero, CP0_TAGLO, 1;						\
-	mtc0	zero, CP0_TAGLO, 2;						\
-	mtc0	zero, CP0_TAGLO, 3;						\
-	mtc0	zero, CP0_TAGLO, 4;
-
-#define IFX_CACHE_EXTRA_OPERATION						\
-	/* set WST bit */							\
-	mfc0	a0, CP0_ECC;							\
-	li	a1, ECCF_WST;							\
-	or	a0, a1;								\
-	mtc0	a0, CP0_ECC;							\
-										\
-	li	a0, K0BASE;							\
-	move	a2, t2;		/* icacheSize */				\
-	move	a3, t4;		/* icacheLineSize */				\
-	move	a1, a2;								\
-	icacheop(a0,a1,a2,a3,(Index_Store_Tag_I));				\
-										\
-	/* clear WST bit */							\
-	mfc0	a0, CP0_ECC;							\
-	li	a1, ~ECCF_WST;							\
-	and	a0, a1;								\
-	mtc0	a0, CP0_ECC;							\
-										\
-	/* 1: initialise dcache tags. */					\
-										\
-	/* cache line size */							\
-	li	a2, CFG_CACHELINE_SIZE;						\
-	/* kseg0 mem address */							\
-	li	a1, 0;								\
-	li	a3, CFG_CACHE_SETS * CFG_CACHE_WAYS;				\
-1:										\
-	/* store tag (invalid, not locked) */					\
-	cache 0x8, 0(a1);							\
-	cache 0x9, 0(a1);							\
-										\
-	add	a3, -1;								\
-	bne	a3, zero, 1b;							\
-	add	a1, a2;								\
-										\
-	/* set WST bit */							\
-	mfc0	a0, CP0_ECC;							\
-	li	a1, ECCF_WST;							\
-	or	a0, a1;								\
-	mtc0	a0, CP0_ECC;							\
-										\
-	li	a0, K0BASE;							\
-	move	a2, t3;		/* dcacheSize */				\
-	move	a3, t5;		/* dcacheLineSize */				\
-	move	a1, a2;								\
-	icacheop(a0,a1,a2,a3,(Index_Store_Tag_D));				\
-										\
-	/* clear WST bit */							\
-	mfc0	a0, CP0_ECC;							\
-	li	a1, ~ECCF_WST;							\
-	and	a0, a1;								\
-	mtc0	a0, CP0_ECC;
-
diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c
deleted file mode 100644
index c67cf15eb..000000000
--- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm-mips/danube.h>
-
-
-
-/*******************************************************************************
-*
-* get_cpuclk - returns the frequency of the CPU. 
-*
-* NOTE:
-*   This functions should be used by the hardware driver to get the correct
-*   frequency of the CPU. 
-*/
-
-unsigned int danube_get_ddr_hz(void)
-{
-	switch((*DANUBE_CGU_SYS) & 0x3){
-		case 0:
-		default:
-			return 166666667;
-		case 1:
-			return 133333333;
-		case 2:
-			return 111111111;
-		case 3:
-			return 83333333;
-	}
-}
-
-
-uint danube_get_cpuclk(void)
-{
-#ifdef CONFIG_USE_EMULATOR
-	return EMULATOR_CPU_SPEED;
-#else //NOT CONFIG_USE_EMULATOR
-	unsigned int ddr_clock=danube_get_ddr_hz();
-	switch((*DANUBE_CGU_SYS) & 0xc){
-		case 0:
-		default:
-			return 333333333;
-		case 4:
-			return ddr_clock;
-		case 8:
-			return ddr_clock << 1;
-	}
-#endif
-}
-
-
-uint danube_get_fpiclk(void)
-{
-#ifdef CONFIG_USE_EMULATOR
-	unsigned int  clkCPU;
-	clkCPU = danube_get_cpu_hz();
-	return clkCPU >> 2;
-#else //NOT CONFIG_USE_EMULATOR
-	unsigned int ddr_clock=danube_get_ddr_hz();
-	if ((*DANUBE_CGU_SYS) & 0x40){
-		return ddr_clock >> 1;
-	}
-	return ddr_clock;
-#endif
-}
-
-
diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c
deleted file mode 100644
index 49355de55..000000000
--- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c
+++ /dev/null
@@ -1,5 +0,0 @@
-
-#define IFX_CPU_RESET					\
-{	*DANUBE_RCU_RST_REQ |=1<<30;			\
-}
-
diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S
deleted file mode 100644
index 17c0b0ae5..000000000
--- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * IFX Platform Dependent CPU Initializations
- * - for Danube
- */
-
-#define IFX_EBU_BOOTCFG_DWORD							\
-	.word INFINEON_EBU_BOOTCFG; /* EBU init code, fetched during booting */	\
-	.word 0x00000000;           /* phases of the flash */
-
-#define IFX_MORE_RESERVED_VECTORS						\
-	XVECENT(romExcHandle,0x400);	/* Int, CauseIV=1 */			\
-	RVECENT(romReserved,129);						\
-	RVECENT(romReserved,130);						\
-	RVECENT(romReserved,131);						\
-	RVECENT(romReserved,132);						\
-	RVECENT(romReserved,133);						\
-	RVECENT(romReserved,134);						\
-	RVECENT(romReserved,135);						\
-	RVECENT(romReserved,136);						\
-	RVECENT(romReserved,137);						\
-	RVECENT(romReserved,138);						\
-	RVECENT(romReserved,139);						\
-	RVECENT(romReserved,140);						\
-	RVECENT(romReserved,141);						\
-	RVECENT(romReserved,142);						\
-	RVECENT(romReserved,143);						\
-	RVECENT(romExcHandle,0x480);	/* EJTAG debug exception */
-
-#define IFX_RESET_PRECHECK							\
-	mfc0	k0, CP0_EBASE;							\
-	and	k0, EBASEF_CPUNUM;						\
-	bne	k0, zero, ifx_mips_handler_1;					\
-	nop;
-
-#define IFX_CPU_EXTRA_INIT							\
-	mfc0	k0, CP0_CONFIG, 7;						\
-	li	k1, 0x04;							\
-	or	k0, k1;								\
-	mtc0	k0, CP0_CONFIG, 7;
-
-#define IFX_CACHE_OPER_MODE							\
-	li	t0, CONF_CM_CACHABLE_NO_WA;
-
-/*
- * Stop VCPU
- */
-#define IFX_MIPS_HANDLER_1							\
-	wait;									\
-	b ifx_mips_handler_1;							\
-	nop;
-