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From 9c83b58b49f88a48565fad6acea921a0ae222856 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 21 Mar 2013 17:50:05 +0100
Subject: [PATCH 112/121] MIPS: add MT7620 dts files
Adds the dtsi file for MT7620 SoC. This is the latest and greatest SoC shipped
by Mediatek.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Kconfig | 4 +
arch/mips/ralink/dts/Makefile | 1 +
arch/mips/ralink/dts/mt7620.dtsi | 138 ++++++++++++++++++++++++++++++++++
arch/mips/ralink/dts/mt7620_eval.dts | 22 ++++++
4 files changed, 165 insertions(+)
create mode 100644 arch/mips/ralink/dts/mt7620.dtsi
create mode 100644 arch/mips/ralink/dts/mt7620_eval.dts
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 493411f..8254502 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -46,6 +46,10 @@ choice
bool "RT3883 eval kit"
depends on SOC_RT3883
+ config DTB_MT7620_EVAL
+ bool "MT7620 eval kit"
+ depends on SOC_MT7620
+
endchoice
endif
diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
index 040a986..036603a 100644
--- a/arch/mips/ralink/dts/Makefile
+++ b/arch/mips/ralink/dts/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
+obj-$(CONFIG_DTB_MT7620_EVAL) := mt7620_eval.dtb.o
diff --git a/arch/mips/ralink/dts/mt7620.dtsi b/arch/mips/ralink/dts/mt7620.dtsi
new file mode 100644
index 0000000..59f057f
--- /dev/null
+++ b/arch/mips/ralink/dts/mt7620.dtsi
@@ -0,0 +1,138 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mtk7620n-soc", "ralink,mt7620-soc";
+
+ cpus {
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600 init=/init";
+ };
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@10000000 {
+ compatible = "palmbus";
+ reg = <0x10000000 0x200000>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@0 {
+ compatible = "ralink,mt7620-sysc", "ralink,mt7620n-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ timer@100 {
+ compatible = "ralink,mt7620-timer", "ralink,rt2880-timer";
+ reg = <0x100 0x20>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <1>;
+
+ status = "disabled";
+ };
+
+ watchdog@120 {
+ compatible = "ralink,mt7620-wdt", "ralink,rt2880-wdt";
+ reg = <0x120 0x10>;
+ };
+
+ intc: intc@200 {
+ compatible = "ralink,mt7620-intc", "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ memc@300 {
+ compatible = "ralink,mt7620-memc", "ralink,rt3050-memc";
+ reg = <0x300 0x100>;
+ };
+
+ gpio0: gpio@600 {
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
+ reg = <0x600 0x34>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <24>;
+ ralink,register-map = [ 00 04 08 0c
+ 20 24 28 2c
+ 30 34 ];
+ };
+
+ gpio1: gpio@638 {
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
+ reg = <0x638 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <16>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+ };
+
+ gpio2: gpio@660 {
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
+ reg = <0x660 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <32>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+ };
+
+ gpio3: gpio@688 {
+ compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
+ reg = <0x688 0x24>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ralink,num-gpios = <1>;
+ ralink,register-map = [ 00 04 08 0c
+ 10 14 18 1c
+ 20 24 ];
+ };
+
+ spi@b00 {
+ compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uartlite@c00 {
+ compatible = "ralink,mt7620-uart", "ralink,rt2880-uart", "ns16550a";
+ reg = <0xc00 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+
+ reg-shift = <2>;
+ };
+ };
+};
diff --git a/arch/mips/ralink/dts/mt7620_eval.dts b/arch/mips/ralink/dts/mt7620_eval.dts
new file mode 100644
index 0000000..dda0f4d
--- /dev/null
+++ b/arch/mips/ralink/dts/mt7620_eval.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+
+/include/ "mt7620.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
+ model = "Ralink MT7620 evaluation board";
+
+ memory@0 {
+ reg = <0x0 0x4000000>;
+ };
+
+ palmbus@10000000 {
+ sysc@0 {
+ ralink,pinmmux = "uartlite", "spi";
+ ralink,uartmux = "gpio";
+ ralink,wdtmux = <0>;
+ };
+ };
+};
--
1.7.10.4
|
