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--- a/drivers/staging/octeon/cvmx-helper-board.c
+++ b/drivers/staging/octeon/cvmx-helper-board.c
@@ -90,7 +90,7 @@ int cvmx_helper_board_get_mii_address(in
case CVMX_BOARD_TYPE_KODAMA:
case CVMX_BOARD_TYPE_EBH3100:
case CVMX_BOARD_TYPE_HIKARI:
- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
/*
@@ -103,6 +103,12 @@ int cvmx_helper_board_get_mii_address(in
return 9;
else
return -1;
+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
+ /* We have only one port, using GMII */
+ if (ipd_port == 0)
+ return 9;
+ else
+ return -1;
case CVMX_BOARD_TYPE_NAC38:
/* Board has 8 RGMII ports PHYs are 0-7 */
if ((ipd_port >= 0) && (ipd_port < 4))
@@ -205,7 +211,7 @@ cvmx_helper_link_info_t __cvmx_helper_bo
result.s.speed = 1000;
return result;
case CVMX_BOARD_TYPE_EBH3100:
- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
/* Port 1 on these boards is always Gigabit */
@@ -217,6 +223,9 @@ cvmx_helper_link_info_t __cvmx_helper_bo
}
/* Fall through to the generic code below */
break;
+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
+ is_broadcom_phy = 1;
+ break;
case CVMX_BOARD_TYPE_CUST_NB5:
/* Port 1 on these boards is always Gigabit */
if (ipd_port == 1) {
--- a/drivers/staging/octeon/cvmx-helper-rgmii.c
+++ b/drivers/staging/octeon/cvmx-helper-rgmii.c
@@ -66,13 +66,15 @@ int __cvmx_helper_rgmii_probe(int interf
cvmx_dprintf("ERROR: RGMII initialize called in "
"SPI interface\n");
} else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
- || OCTEON_IS_MODEL(OCTEON_CN30XX)
+ //|| OCTEON_IS_MODEL(OCTEON_CN30XX)
|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
/*
* On these chips "type" says we're in
* GMII/MII mode. This limits us to 2 ports
*/
num_ports = 2;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+ num_ports = 1;
} else {
cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
__func__);
--- a/arch/mips/cavium-octeon/pci.c
+++ b/arch/mips/cavium-octeon/pci.c
@@ -95,9 +95,11 @@ const char *octeon_get_pci_interrupts(vo
case CVMX_BOARD_TYPE_EBH3000:
return "";
case CVMX_BOARD_TYPE_EBH3100:
- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+ return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
case CVMX_BOARD_TYPE_BBGW_REF:
return "AABCD";
default:
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