blob: 15e301a45b9d427c4f3133e4201206c2b0c01de6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
|
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -365,6 +365,7 @@ config ARCH_CNS3XXX
select MIGHT_HAVE_CACHE_L2X0
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
+ select CLKDEV_LOOKUP
help
Support for Cavium Networks CNS3XXX platform.
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -9,8 +9,11 @@
*/
#include <linux/init.h>
+#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
#include <linux/io.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
@@ -20,6 +23,10 @@
#include <mach/cns3xxx.h>
#include "core.h"
+struct clk {
+ unsigned long rate;
+};
+
static struct map_desc cns3xxx_io_desc[] __initdata = {
{
.virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
@@ -277,3 +284,33 @@ void __init cns3xxx_l2x0_init(void)
}
#endif /* CONFIG_CACHE_L2X0 */
+
+int clk_enable(struct clk *clk)
+{
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+static struct clk_lookup cns3xxx_clocks[] = {
+ {
+ /* TODO */
+ },
+};
+
+int __init cns3xxx_clocks_init(void)
+{
+ clkdev_add_table(cns3xxx_clocks, ARRAY_SIZE(cns3xxx_clocks));
+ return 0;
+}
+postcore_initcall(cns3xxx_clocks_init);
|
