1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
|
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,4 +1,4 @@
-obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
+obj-$(CONFIG_ARCH_CNS3XXX) += core.o gpio.o pm.o devices.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
obj-$(CONFIG_MACH_GW2388) += laguna.o
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -199,7 +199,10 @@ static void __init cns3420_init(void)
cns3xxx_ahci_init();
cns3xxx_sdhci_init();
-
+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
+ NR_IRQS_CNS3XXX);
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
+ NR_IRQS_CNS3XXX + 32);
cns3xxx_pcie_init(0x3);
pm_power_off = cns3xxx_power_off;
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -21,7 +21,6 @@
#include <asm/hardware/gic.h>
#include <asm/smp_twd.h>
#include <asm/hardware/cache-l2x0.h>
-#include <asm/gpio.h>
#include <mach/cns3xxx.h>
#include "core.h"
@@ -83,73 +82,12 @@ static struct map_desc cns3xxx_io_desc[]
},
};
-static inline void gpio_line_config(u8 line, u32 direction)
-{
- u32 reg;
- if (direction) {
- if (line < 32) {
- reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
- reg |= (1 << line);
- __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
- } else {
- reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
- reg |= (1 << (line - 32));
- __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
- }
- } else {
- if (line < 32) {
- reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
- reg &= ~(1 << line);
- __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
- } else {
- reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
- reg &= ~(1 << (line - 32));
- __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
- }
- }
-}
-
-static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- gpio_line_config(gpio, CNS3XXX_GPIO_IN);
- return 0;
-}
-
-static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
-{
- gpio_line_set(gpio, level);
- gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
- return 0;
-}
-
-static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- return gpio_get_value(gpio);
-}
-
-static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- gpio_set_value(gpio, value);
-}
-
-static struct gpio_chip cns3xxx_gpio_chip = {
- .label = "CNS3XXX_GPIO_CHIP",
- .direction_input = cns3xxx_gpio_direction_input,
- .direction_output = cns3xxx_gpio_direction_output,
- .get = cns3xxx_gpio_get_value,
- .set = cns3xxx_gpio_set_value,
- .base = 0,
- .ngpio = 64,
-};
-
void __init cns3xxx_common_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
#endif
iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
-
- gpiochip_add(&cns3xxx_gpio_chip);
}
/* used by entry-macro.S */
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -366,7 +366,8 @@ config ARCH_CLPS711X
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family"
select CPU_V6K
- select ARCH_WANT_OPTIONAL_GPIOLIB
+ select ARCH_REQUIRE_GPIOLIB
+ select GENERIC_IRQ_CHIP
select GENERIC_CLOCKEVENTS
select ARM_GIC
select CLKDEV_LOOKUP
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
#undef NR_IRQS
-#define NR_IRQS NR_IRQS_CNS3XXX
+#define NR_IRQS (NR_IRQS_CNS3XXX + 64)
#endif
#endif /* __MACH_BOARD_CNS3XXX_H */
|
