1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
|
/*
* Atheros AR71xx SoC GPIO API support
*
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/gpio.h>
#include <asm/mach-ar71xx/ar71xx.h>
static DEFINE_SPINLOCK(ar71xx_gpio_lock);
unsigned long ar71xx_gpio_count;
EXPORT_SYMBOL(ar71xx_gpio_count);
void __ar71xx_gpio_set_value(unsigned gpio, int value)
{
unsigned long flags;
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
if (value)
ar71xx_gpio_wr(GPIO_REG_SET, (1 << gpio));
else
ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << gpio));
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
EXPORT_SYMBOL(__ar71xx_gpio_set_value);
int __ar71xx_gpio_get_value(unsigned gpio)
{
return (ar71xx_gpio_rr(GPIO_REG_IN) & (1 << gpio)) ? 1 : 0;
}
EXPORT_SYMBOL(__ar71xx_gpio_get_value);
static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset)
{
return __ar71xx_gpio_get_value(offset);
}
static void ar71xx_gpio_set_value(struct gpio_chip *chip,
unsigned offset, int value)
{
__ar71xx_gpio_set_value(offset, value);
}
static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
unsigned long flags;
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
ar71xx_gpio_wr(GPIO_REG_OE,
ar71xx_gpio_rr(GPIO_REG_OE) & ~(1 << offset));
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
return 0;
}
static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
unsigned long flags;
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
if (value)
ar71xx_gpio_wr(GPIO_REG_SET, (1 << offset));
else
ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << offset));
ar71xx_gpio_wr(GPIO_REG_OE,
ar71xx_gpio_rr(GPIO_REG_OE) | (1 << offset));
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
return 0;
}
static struct gpio_chip ar71xx_gpio_chip = {
.label = "ar71xx",
.get = ar71xx_gpio_get_value,
.set = ar71xx_gpio_set_value,
.direction_input = ar71xx_gpio_direction_input,
.direction_output = ar71xx_gpio_direction_output,
.base = 0,
.ngpio = AR71XX_GPIO_COUNT,
};
void ar71xx_gpio_function_enable(u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) | mask);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
void ar71xx_gpio_function_disable(u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&ar71xx_gpio_lock, flags);
ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) & ~mask);
spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
}
void __init ar71xx_gpio_init(void)
{
int err;
if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
"AR71xx GPIO controller"))
panic("cannot allocate AR71xx GPIO registers page");
switch (ar71xx_soc) {
case AR71XX_SOC_AR7130:
case AR71XX_SOC_AR7141:
case AR71XX_SOC_AR7161:
ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT;
break;
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT;
break;
default:
BUG();
}
err = gpiochip_add(&ar71xx_gpio_chip);
if (err)
panic("cannot add AR71xx GPIO chip, error=%d", err);
}
|
