From 780a64cd52209fad15c7133f950b2b2d6b9b59e2 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sat, 27 Aug 2011 21:44:32 +0200 Subject: [PATCH 23/24] MIPS: lantiq: adds basic vr9 support --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 + arch/mips/lantiq/Kconfig | 9 ++ arch/mips/lantiq/Platform | 1 + arch/mips/lantiq/machtypes.h | 3 + arch/mips/lantiq/xway/Kconfig | 12 +++ arch/mips/lantiq/xway/Makefile | 2 + arch/mips/lantiq/xway/clk-vr9.c | 78 ++++++++++++++++++++ arch/mips/lantiq/xway/mach-fritz.c | 74 +++++++++++++++++++ arch/mips/lantiq/xway/prom-vr9.c | 55 ++++++++++++++ arch/mips/pci/Makefile | 2 +- 10 files changed, 237 insertions(+), 1 deletions(-) create mode 100644 arch/mips/lantiq/xway/clk-vr9.c create mode 100644 arch/mips/lantiq/xway/mach-fritz.c create mode 100644 arch/mips/lantiq/xway/prom-vr9.c --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -21,6 +21,7 @@ #define SOC_ID_ARX188 0x16C #define SOC_ID_ARX168 0x16D #define SOC_ID_ARX182 0x16F +#define SOC_ID_VRX288 0x1C0 /* SoC Types */ #define SOC_TYPE_DANUBE 0x01 @@ -91,6 +92,7 @@ /* ETOP - ethernet */ #define LTQ_ETOP_BASE_ADDR 0x1E180000 +#define LTQ_ETOP_BASE_ADDR_VR9 0x1E200000 #define LTQ_ETOP_SIZE 0x40000 /* GBIT - gigabit switch */ --- a/arch/mips/lantiq/Kconfig +++ b/arch/mips/lantiq/Kconfig @@ -1,5 +1,8 @@ if LANTIQ +config LANTIQ_PCIE + bool + config SOC_TYPE_XWAY bool default n @@ -17,6 +20,12 @@ config SOC_XWAY select SOC_TYPE_XWAY select HW_HAS_PCI +config SOC_VR9 + bool "VR9" + select SOC_TYPE_XWAY + select HW_HAS_PCI + select LANTIQ_PCIE + config SOC_FALCON bool "FALCON" endchoice --- a/arch/mips/lantiq/Platform +++ b/arch/mips/lantiq/Platform @@ -6,4 +6,5 @@ platform-$(CONFIG_LANTIQ) += lantiq/ cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq load-$(CONFIG_LANTIQ) = 0xffffffff80002000 cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway +cflags-$(CONFIG_SOC_TYPE_VR9) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon --- a/arch/mips/lantiq/machtypes.h +++ b/arch/mips/lantiq/machtypes.h @@ -20,6 +20,9 @@ enum lantiq_mach_type { LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ + + /* FRITZ!BOX */ + LANTIQ_MACH_FRITZ3370, /* FRITZ!BOX 3370 vdsl cpe */ }; #endif --- a/arch/mips/lantiq/xway/Kconfig +++ b/arch/mips/lantiq/xway/Kconfig @@ -21,3 +21,15 @@ config LANTIQ_MACH_EASY50601 endmenu endif + +if SOC_VR9 + +menu "MIPS Machine" + +config LANTIQ_MACH_FRITZ3370 + bool "Fritz!Box 3370" + default y + +endmenu + +endif --- a/arch/mips/lantiq/xway/Makefile +++ b/arch/mips/lantiq/xway/Makefile @@ -2,6 +2,8 @@ obj-y := sysctrl.o reset.o gpio.o gpio_s obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o +obj-$(CONFIG_SOC_VR9) += clk-vr9.o prom-vr9.o obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o +obj-$(CONFIG_LANTIQ_MACH_FRITZ3370) += mach-fritz.o --- /dev/null +++ b/arch/mips/lantiq/xway/clk-vr9.c @@ -0,0 +1,78 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define CLOCK_62_5M 62500000 +#define CLOCK_83_5M 83500000 +#define CLOCK_125M 125000000 +#define CLOCK_200M 200000000 +#define CLOCK_250M 250000000 +#define CLOCK_300M 300000000 +#define CLOCK_98_304M 98304000 +#define CLOCK_150M 150000000 +#define CLOCK_196_608M 196608000 +#define CLOCK_600M 600000000 +#define CLOCK_500M 500000000 +#define CLOCK_393M 393215332 +#define CLOCK_166M 166666666 + +#define LTQ_CGU_SYS 0x0c +#define LTQ_CGU_IF_CLK 0x24 + +unsigned int ltq_get_cpu_hz(void) +{ + int clks[] = { + CLOCK_600M, CLOCK_500M, CLOCK_393M, CLOCK_333M, CLOCK_125M, + CLOCK_125M, CLOCK_196_608M, CLOCK_166M, CLOCK_125M, CLOCK_125M }; + int val = (ltq_cgu_r32(LTQ_CGU_SYS) >> 4) & 0xf; + + if (val > 9) + panic("bad cpu speed\n"); + if (val == 2) + panic("missing workaround\n"); + //cgu_get_pll1_fosc(); //CLOCK_393M; + return clks[val]; +} +EXPORT_SYMBOL(ltq_get_cpu_hz); + +unsigned int ltq_get_fpi_hz(void) +{ + int clks[] = { + CLOCK_62_5M, CLOCK_62_5M, CLOCK_83_5M, CLOCK_125M, CLOCK_125M, + CLOCK_125M, CLOCK_167M, CLOCK_200M, CLOCK_250M, CLOCK_300M, + CLOCK_62_5M, CLOCK_98_304M, CLOCK_150M, CLOCK_196_608M }; + int val = ((ltq_cgu_r32(LTQ_CGU_IF_CLK) >> 25) & 0xf); + + if (val > 13) + panic("bad fpi speed\n"); + + return clks[val]; +} +EXPORT_SYMBOL(ltq_get_fpi_hz); + +unsigned int ltq_get_io_region_clock(void) +{ + return ltq_get_fpi_hz() / 2; +} +EXPORT_SYMBOL(ltq_get_io_region_clock); + +unsigned int ltq_get_fpi_bus_clock(int fpi) +{ + return ltq_get_fpi_hz(); +} +EXPORT_SYMBOL(ltq_get_fpi_bus_clock); --- /dev/null +++ b/arch/mips/lantiq/xway/prom-vr9.c @@ -0,0 +1,55 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "devices.h" +#include "../prom.h" + +#define SOC_VRX288 "VRX288" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +void __init ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_VRX288: + i->name = SOC_VRX288; + i->type = SOC_TYPE_VR9; + break; + + default: + unreachable(); + break; + } + printk("%08X\n", i->partnum); +} + +void __init ltq_soc_setup(void) +{ + /* + reg = IFX_REG_R32(IFX_XBAR_ALWAYS_LAST); + reg &= ~ IFX_XBAR_FPI_BURST_EN; + IFX_REG_W32(reg, IFX_XBAR_ALWAYS_LAST); + */ + + ltq_register_asc(1); + ltq_register_gpio(); + ltq_register_wdt(); +} --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -41,7 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1 obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o -obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o +obj-$(CONFIG_LANTIQ) += pci-lantiq.o ops-lantiq.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o