From 5e679bb5e0ba948e5a1aa52ab50b6b60d175348d Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 21 Mar 2012 14:17:37 +0100 Subject: [PATCH 67/73] MIPS: lantiq: adds bootsel helper --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 12 ++++++++++++ arch/mips/lantiq/xway/reset.c | 12 +++++++++++- 2 files changed, 23 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index bfdeb16..1ec8f2a 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -144,6 +144,18 @@ #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) +/* BOOT_SEL - find what boot media we have */ +#define BS_EXT_ROM 0x0 +#define BS_FLASH 0x1 +#define BS_MII0 0x2 +#define BS_PCI 0x3 +#define BS_UART1 0x4 +#define BS_SPI 0x5 +#define BS_NAND 0x6 +#define BS_RMII0 0x7 + +extern unsigned char ltq_boot_select(void); + /* register access macros for EBU and CGU */ #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c index 8a5dff1..b8f7ffb 100644 --- a/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c @@ -27,7 +27,11 @@ #define RCU_RST_STAT 0x0014 /* reset cause */ -#define RCU_STAT_SHIFT 26 +#define RCU_STAT_SHIFT 26 +/* boot selection */ +#define RCU_BOOT_SEL_SHIFT 26 +#define RCU_BOOT_SEL_MASK 0x7 + /* Global SW Reset */ #define RCU_RD_SRST BIT(30) /* Memory Controller */ @@ -75,6 +79,12 @@ int ltq_reset_cause(void) } EXPORT_SYMBOL_GPL(ltq_reset_cause); +unsigned char ltq_boot_select(void) +{ + u32 val = ltq_rcu_r32(RCU_RST_STAT); + return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK; +} + void ltq_reset_once(unsigned int module, ulong usec) { ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ); -- 1.7.9.1