diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig index f9cc2b6..9274d3f 100644 --- a/drivers/net/arm/Kconfig +++ b/drivers/net/arm/Kconfig @@ -47,3 +47,13 @@ config EP93XX_ETH help This is a driver for the ethernet hardware included in EP93xx CPUs. Say Y if you are building a kernel for EP93xx based devices. + +config IXP4XX_ETH + tristate "IXP4xx Ethernet support" + depends on NET_ETHERNET && ARM && ARCH_IXP4XX + select IXP4XX_NPE + select IXP4XX_QMGR + select MII + help + Say Y here if you want to use built-in Ethernet ports + on IXP4xx processor. diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile index a4c8682..7c812ac 100644 --- a/drivers/net/arm/Makefile +++ b/drivers/net/arm/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3) += ether3.o obj-$(CONFIG_ARM_ETHER1) += ether1.o obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o +obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c new file mode 100644 index 0000000..d8bbbc7 --- /dev/null +++ b/drivers/net/arm/ixp4xx_eth.c @@ -0,0 +1,1264 @@ +/* + * Intel IXP4xx Ethernet driver for Linux + * + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * Ethernet port config (0x00 is not present on IXP42X): + * + * logical port 0x00 0x10 0x20 + * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) + * physical PortId 2 0 1 + * TX queue 23 24 25 + * RX-free queue 26 27 28 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable + * + * + * Queue entries: + * bits 0 -> 1 - NPE ID (RX and TX-done) + * bits 0 -> 2 - priority (TX, per 802.1D) + * bits 3 -> 4 - port ID (user-set?) + * bits 5 -> 31 - physical descriptor address + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEBUG_QUEUES 0 +#define DEBUG_DESC 0 +#define DEBUG_RX 0 +#define DEBUG_TX 0 +#define DEBUG_PKT_BYTES 0 +#define DEBUG_MDIO 0 +#define DEBUG_CLOSE 0 + +#define DRV_NAME "ixp4xx_eth" + +#define MAX_NPES 3 + +#define RX_DESCS 64 /* also length of all RX queues */ +#define TX_DESCS 16 /* also length of all TX queues */ +#define TXDONE_QUEUE_LEN 64 /* dwords */ + +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) +#define REGS_SIZE 0x1000 +#define MAX_MRU 1536 /* 0x600 */ +#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) + +#define NAPI_WEIGHT 16 +#define MDIO_INTERVAL (3 * HZ) +#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ +#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */ +#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ + +#define NPE_ID(port_id) ((port_id) >> 4) +#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) +#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) +#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) +#define TXDONE_QUEUE 31 + +/* TX Control Registers */ +#define TX_CNTRL0_TX_EN 0x01 +#define TX_CNTRL0_HALFDUPLEX 0x02 +#define TX_CNTRL0_RETRY 0x04 +#define TX_CNTRL0_PAD_EN 0x08 +#define TX_CNTRL0_APPEND_FCS 0x10 +#define TX_CNTRL0_2DEFER 0x20 +#define TX_CNTRL0_RMII 0x40 /* reduced MII */ +#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ + +/* RX Control Registers */ +#define RX_CNTRL0_RX_EN 0x01 +#define RX_CNTRL0_PADSTRIP_EN 0x02 +#define RX_CNTRL0_SEND_FCS 0x04 +#define RX_CNTRL0_PAUSE_EN 0x08 +#define RX_CNTRL0_LOOP_EN 0x10 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20 +#define RX_CNTRL0_RX_RUNT_EN 0x40 +#define RX_CNTRL0_BCAST_DIS 0x80 +#define RX_CNTRL1_DEFER_EN 0x01 + +/* Core Control Register */ +#define CORE_RESET 0x01 +#define CORE_RX_FIFO_FLUSH 0x02 +#define CORE_TX_FIFO_FLUSH 0x04 +#define CORE_SEND_JAM 0x08 +#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ + +#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ + TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ + TX_CNTRL0_2DEFER) +#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN +#define DEFAULT_CORE_CNTRL CORE_MDC_EN + + +/* NPE message codes */ +#define NPE_GETSTATUS 0x00 +#define NPE_EDB_SETPORTADDRESS 0x01 +#define NPE_EDB_GETMACADDRESSDATABASE 0x02 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03 +#define NPE_GETSTATS 0x04 +#define NPE_RESETSTATS 0x05 +#define NPE_SETMAXFRAMELENGTHS 0x06 +#define NPE_VLAN_SETRXTAGMODE 0x07 +#define NPE_VLAN_SETDEFAULTRXVID 0x08 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A +#define NPE_VLAN_SETRXQOSENTRY 0x0B +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C +#define NPE_STP_SETBLOCKINGSTATE 0x0D +#define NPE_FW_SETFIREWALLMODE 0x0E +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F +#define NPE_PC_SETAPMACTABLE 0x11 +#define NPE_SETLOOPBACK_MODE 0x12 +#define NPE_PC_SETBSSIDTABLE 0x13 +#define NPE_ADDRESS_FILTER_CONFIG 0x14 +#define NPE_APPENDFCSCONFIG 0x15 +#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 +#define NPE_MAC_RECOVERY_START 0x17 + + +#ifdef __ARMEB__ +typedef struct sk_buff buffer_t; +#define free_buffer dev_kfree_skb +#define free_buffer_irq dev_kfree_skb_irq +#else +typedef void buffer_t; +#define free_buffer kfree +#define free_buffer_irq kfree +#endif + +struct eth_regs { + u32 tx_control[2], __res1[2]; /* 000 */ + u32 rx_control[2], __res2[2]; /* 010 */ + u32 random_seed, __res3[3]; /* 020 */ + u32 partial_empty_threshold, __res4; /* 030 */ + u32 partial_full_threshold, __res5; /* 038 */ + u32 tx_start_bytes, __res6[3]; /* 040 */ + u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */ + u32 tx_2part_deferral[2], __res8[2]; /* 060 */ + u32 slot_time, __res9[3]; /* 070 */ + u32 mdio_command[4]; /* 080 */ + u32 mdio_status[4]; /* 090 */ + u32 mcast_mask[6], __res10[2]; /* 0A0 */ + u32 mcast_addr[6], __res11[2]; /* 0C0 */ + u32 int_clock_threshold, __res12[3]; /* 0E0 */ + u32 hw_addr[6], __res13[61]; /* 0F0 */ + u32 core_control; /* 1FC */ +}; + +struct port { + struct resource *mem_res; + struct eth_regs __iomem *regs; + struct npe *npe; + struct net_device *netdev; + struct napi_struct napi; + struct net_device_stats stat; + struct mii_if_info mii; + struct delayed_work mdio_thread; + struct eth_plat_info *plat; + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; + struct desc *desc_tab; /* coherent */ + u32 desc_tab_phys; + int id; /* logical port ID */ + u16 mii_bmcr; +}; + +/* NPE message structure */ +struct msg { +#ifdef __ARMEB__ + u8 cmd, eth_id, byte2, byte3; + u8 byte4, byte5, byte6, byte7; +#else + u8 byte3, byte2, eth_id, cmd; + u8 byte7, byte6, byte5, byte4; +#endif +}; + +/* Ethernet packet descriptor */ +struct desc { + u32 next; /* pointer to next buffer, unused */ + +#ifdef __ARMEB__ + u16 buf_len; /* buffer length */ + u16 pkt_len; /* packet length */ + u32 data; /* pointer to data buffer in RAM */ + u8 dest_id; + u8 src_id; + u16 flags; + u8 qos; + u8 padlen; + u16 vlan_tci; +#else + u16 pkt_len; /* packet length */ + u16 buf_len; /* buffer length */ + u32 data; /* pointer to data buffer in RAM */ + u16 flags; + u8 src_id; + u8 dest_id; + u16 vlan_tci; + u8 padlen; + u8 qos; +#endif + +#ifdef __ARMEB__ + u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; + u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; + u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; +#else + u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; + u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; + u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; +#endif +}; + + +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ + (n) * sizeof(struct desc)) +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) + +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ + ((n) + RX_DESCS) * sizeof(struct desc)) +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) + +#ifndef __ARMEB__ +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) +{ + int i; + for (i = 0; i < cnt; i++) + dest[i] = swab32(src[i]); +} +#endif + +static spinlock_t mdio_lock; +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ +static int ports_open; +static struct port *npe_port_tab[MAX_NPES]; +static struct dma_pool *dma_pool; + + +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location, + int write, u16 cmd) +{ + int cycles = 0; + + if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { + printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name); + return 0; + } + + if (write) { + __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); + __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); + } + __raw_writel(((phy_id << 5) | location) & 0xFF, + &mdio_regs->mdio_command[2]); + __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, + &mdio_regs->mdio_command[3]); + + while ((cycles < MAX_MDIO_RETRIES) && + (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { + udelay(1); + cycles++; + } + + if (cycles == MAX_MDIO_RETRIES) { + printk(KERN_ERR "%s: MII write failed\n", dev->name); + return 0; + } + +#if DEBUG_MDIO + printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name, + cycles); +#endif + + if (write) + return 0; + + if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { + printk(KERN_ERR "%s: MII read failed\n", dev->name); + return 0; + } + + return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | + (__raw_readl(&mdio_regs->mdio_status[1]) << 8); +} + +static int mdio_read(struct net_device *dev, int phy_id, int location) +{ + unsigned long flags; + u16 val; + + spin_lock_irqsave(&mdio_lock, flags); + val = mdio_cmd(dev, phy_id, location, 0, 0); + spin_unlock_irqrestore(&mdio_lock, flags); + return val; +} + +static void mdio_write(struct net_device *dev, int phy_id, int location, + int val) +{ + unsigned long flags; + + spin_lock_irqsave(&mdio_lock, flags); + mdio_cmd(dev, phy_id, location, 1, val); + spin_unlock_irqrestore(&mdio_lock, flags); +} + +static void phy_reset(struct net_device *dev, int phy_id) +{ + struct port *port = netdev_priv(dev); + int cycles = 0; + + mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET); + + while (cycles < MAX_MII_RESET_RETRIES) { + if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) { +#if DEBUG_MDIO + printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n", + dev->name, cycles); +#endif + return; + } + udelay(1); + cycles++; + } + + printk(KERN_ERR "%s: MII reset failed\n", dev->name); +} + +static void eth_set_duplex(struct port *port) +{ + if (port->mii.full_duplex) + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, + &port->regs->tx_control[0]); + else + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, + &port->regs->tx_control[0]); +} + + +static void phy_check_media(struct port *port, int init) +{ + if (mii_check_media(&port->mii, 1, init)) + eth_set_duplex(port); + if (port->mii.force_media) { /* mii_check_media() doesn't work */ + struct net_device *dev = port->netdev; + int cur_link = mii_link_ok(&port->mii); + int prev_link = netif_carrier_ok(dev); + + if (!prev_link && cur_link) { + printk(KERN_INFO "%s: link up\n", dev->name); + netif_carrier_on(dev); + } else if (prev_link && !cur_link) { + printk(KERN_INFO "%s: link down\n", dev->name); + netif_carrier_off(dev); + } + } +} + + +static void mdio_thread(struct work_struct *work) +{ + struct port *port = container_of(work, struct port, mdio_thread.work); + + phy_check_media(port, 0); + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL); +} + + +static inline void debug_pkt(struct net_device *dev, const char *func, + u8 *data, int len) +{ +#if DEBUG_PKT_BYTES + int i; + + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); + for (i = 0; i < len; i++) { + if (i >= DEBUG_PKT_BYTES) + break; + printk("%s%02X", + ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", + data[i]); + } + printk("\n"); +#endif +} + + +static inline void debug_desc(u32 phys, struct desc *desc) +{ +#if DEBUG_DESC + printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" + " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", + phys, desc->next, desc->buf_len, desc->pkt_len, + desc->data, desc->dest_id, desc->src_id, desc->flags, + desc->qos, desc->padlen, desc->vlan_tci, + desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, + desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, + desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, + desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); +#endif +} + +static inline void debug_queue(unsigned int queue, int is_get, u32 phys) +{ +#if DEBUG_QUEUES + static struct { + int queue; + char *name; + } names[] = { + { TX_QUEUE(0x10), "TX#0 " }, + { TX_QUEUE(0x20), "TX#1 " }, + { TX_QUEUE(0x00), "TX#2 " }, + { RXFREE_QUEUE(0x10), "RX-free#0 " }, + { RXFREE_QUEUE(0x20), "RX-free#1 " }, + { RXFREE_QUEUE(0x00), "RX-free#2 " }, + { TXDONE_QUEUE, "TX-done " }, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(names); i++) + if (names[i].queue == queue) + break; + + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue, + i < ARRAY_SIZE(names) ? names[i].name : "", + is_get ? "->" : "<-", phys); +#endif +} + +static inline u32 queue_get_entry(unsigned int queue) +{ + u32 phys = qmgr_get_entry(queue); + debug_queue(queue, 1, phys); + return phys; +} + +static inline int queue_get_desc(unsigned int queue, struct port *port, + int is_tx) +{ + u32 phys, tab_phys, n_desc; + struct desc *tab; + + if (!(phys = queue_get_entry(queue))) + return -1; + + phys &= ~0x1F; /* mask out non-address bits */ + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); + n_desc = (phys - tab_phys) / sizeof(struct desc); + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); + debug_desc(phys, &tab[n_desc]); + BUG_ON(tab[n_desc].next); + return n_desc; +} + +static inline void queue_put_desc(unsigned int queue, u32 phys, + struct desc *desc) +{ + debug_queue(queue, 0, phys); + debug_desc(phys, desc); + BUG_ON(phys & 0x1F); + qmgr_put_entry(queue, phys); + BUG_ON(qmgr_stat_overflow(queue)); +} + + +static inline void dma_unmap_tx(struct port *port, struct desc *desc) +{ +#ifdef __ARMEB__ + dma_unmap_single(&port->netdev->dev, desc->data, + desc->buf_len, DMA_TO_DEVICE); +#else + dma_unmap_single(&port->netdev->dev, desc->data & ~3, + ALIGN((desc->data & 3) + desc->buf_len, 4), + DMA_TO_DEVICE); +#endif +} + + +static void eth_rx_irq(void *pdev) +{ + struct net_device *dev = pdev; + struct port *port = netdev_priv(dev); + +#if DEBUG_RX + printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); +#endif + qmgr_disable_irq(port->plat->rxq); + netif_rx_schedule(dev, &port->napi); +} + +static int eth_poll(struct napi_struct *napi, int budget) +{ + struct port *port = container_of(napi, struct port, napi); + struct net_device *dev = port->netdev; + unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); + int received = 0; + +#if DEBUG_RX + printk(KERN_DEBUG "%s: eth_poll\n", dev->name); +#endif + + while (received < budget) { + struct sk_buff *skb; + struct desc *desc; + int n; +#ifdef __ARMEB__ + struct sk_buff *temp; + u32 phys; +#endif + + if ((n = queue_get_desc(rxq, port, 0)) < 0) { + received = 0; /* No packet received */ +#if DEBUG_RX + printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n", + dev->name); +#endif + netif_rx_complete(dev, napi); + qmgr_enable_irq(rxq); + if (!qmgr_stat_empty(rxq) && + netif_rx_reschedule(dev, napi)) { +#if DEBUG_RX + printk(KERN_DEBUG "%s: eth_poll" + " netif_rx_reschedule successed\n", + dev->name); +#endif + qmgr_disable_irq(rxq); + continue; + } +#if DEBUG_RX + printk(KERN_DEBUG "%s: eth_poll all done\n", + dev->name); +#endif + return 0; /* all work done */ + } + + desc = rx_desc_ptr(port, n); + +#ifdef __ARMEB__ + if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { + phys = dma_map_single(&dev->dev, skb->data, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(phys)) { + dev_kfree_skb(skb); + skb = NULL; + } + } +#else + skb = netdev_alloc_skb(dev, + ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); +#endif + + if (!skb) { + port->stat.rx_dropped++; + /* put the desc back on RX-ready queue */ + desc->buf_len = MAX_MRU; + desc->pkt_len = 0; + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); + continue; + } + + /* process received frame */ +#ifdef __ARMEB__ + temp = skb; + skb = port->rx_buff_tab[n]; + dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); +#else + dma_sync_single(&dev->dev, desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], + ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); +#endif + skb_reserve(skb, NET_IP_ALIGN); + skb_put(skb, desc->pkt_len); + + debug_pkt(dev, "eth_poll", skb->data, skb->len); + + skb->protocol = eth_type_trans(skb, dev); + dev->last_rx = jiffies; + port->stat.rx_packets++; + port->stat.rx_bytes += skb->len; + netif_receive_skb(skb); + + /* put the new buffer on RX-free queue */ +#ifdef __ARMEB__ + port->rx_buff_tab[n] = temp; + desc->data = phys + NET_IP_ALIGN; +#endif + desc->buf_len = MAX_MRU; + desc->pkt_len = 0; + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); + received++; + } + +#if DEBUG_RX + printk(KERN_DEBUG "eth_poll(): end, not all work done\n"); +#endif + return received; /* not all work done */ +} + + +static void eth_txdone_irq(void *unused) +{ + u32 phys; + +#if DEBUG_TX + printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); +#endif + while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) { + u32 npe_id, n_desc; + struct port *port; + struct desc *desc; + int start; + + npe_id = phys & 3; + BUG_ON(npe_id >= MAX_NPES); + port = npe_port_tab[npe_id]; + BUG_ON(!port); + phys &= ~0x1F; /* mask out non-address bits */ + n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); + BUG_ON(n_desc >= TX_DESCS); + desc = tx_desc_ptr(port, n_desc); + debug_desc(phys, desc); + + if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ + port->stat.tx_packets++; + port->stat.tx_bytes += desc->pkt_len; + + dma_unmap_tx(port, desc); +#if DEBUG_TX + printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", + port->netdev->name, port->tx_buff_tab[n_desc]); +#endif + free_buffer_irq(port->tx_buff_tab[n_desc]); + port->tx_buff_tab[n_desc] = NULL; + } + + start = qmgr_stat_empty(port->plat->txreadyq); + queue_put_desc(port->plat->txreadyq, phys, desc); + if (start) { +#if DEBUG_TX + printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", + port->netdev->name); +#endif + netif_wake_queue(port->netdev); + } + } +} + +static int eth_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + unsigned int txreadyq = port->plat->txreadyq; + int len, offset, bytes, n; + void *mem; + u32 phys; + struct desc *desc; + +#if DEBUG_TX + printk(KERN_DEBUG "%s: eth_xmit\n", dev->name); +#endif + + if (unlikely(skb->len > MAX_MRU)) { + dev_kfree_skb(skb); + port->stat.tx_errors++; + return NETDEV_TX_OK; + } + + debug_pkt(dev, "eth_xmit", skb->data, skb->len); + + len = skb->len; +#ifdef __ARMEB__ + offset = 0; /* no need to keep alignment */ + bytes = len; + mem = skb->data; +#else + offset = (int)skb->data & 3; /* keep 32-bit alignment */ + bytes = ALIGN(offset + len, 4); + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { + dev_kfree_skb(skb); + port->stat.tx_dropped++; + return NETDEV_TX_OK; + } + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); + dev_kfree_skb(skb); +#endif + + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); + if (dma_mapping_error(phys)) { +#ifdef __ARMEB__ + dev_kfree_skb(skb); +#else + kfree(mem); +#endif + port->stat.tx_dropped++; + return NETDEV_TX_OK; + } + + n = queue_get_desc(txreadyq, port, 1); + BUG_ON(n < 0); + desc = tx_desc_ptr(port, n); + +#ifdef __ARMEB__ + port->tx_buff_tab[n] = skb; +#else + port->tx_buff_tab[n] = mem; +#endif + desc->data = phys + offset; + desc->buf_len = desc->pkt_len = len; + + /* NPE firmware pads short frames with zeros internally */ + wmb(); + queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); + dev->trans_start = jiffies; + + if (qmgr_stat_empty(txreadyq)) { +#if DEBUG_TX + printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name); +#endif + netif_stop_queue(dev); + /* we could miss TX ready interrupt */ + if (!qmgr_stat_empty(txreadyq)) { +#if DEBUG_TX + printk(KERN_DEBUG "%s: eth_xmit ready again\n", + dev->name); +#endif + netif_wake_queue(dev); + } + } + +#if DEBUG_TX + printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name); +#endif + return NETDEV_TX_OK; +} + + +static struct net_device_stats *eth_stats(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + return &port->stat; +} + +static void eth_set_mcast_list(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + struct dev_mc_list *mclist = dev->mc_list; + u8 diffs[ETH_ALEN], *addr; + int cnt = dev->mc_count, i; + + if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) { + __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, + &port->regs->rx_control[0]); + return; + } + + memset(diffs, 0, ETH_ALEN); + addr = mclist->dmi_addr; /* first MAC address */ + + while (--cnt && (mclist = mclist->next)) + for (i = 0; i < ETH_ALEN; i++) + diffs[i] |= addr[i] ^ mclist->dmi_addr[i]; + + for (i = 0; i < ETH_ALEN; i++) { + __raw_writel(addr[i], &port->regs->mcast_addr[i]); + __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); + } + + __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, + &port->regs->rx_control[0]); +} + + +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) +{ + struct port *port = netdev_priv(dev); + unsigned int duplex_chg; + int err; + + if (!netif_running(dev)) + return -EINVAL; + err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg); + if (duplex_chg) + eth_set_duplex(port); + return err; +} + + +static int request_queues(struct port *port) +{ + int err; + + err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0); + if (err) + return err; + + err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0); + if (err) + goto rel_rxfree; + + err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0); + if (err) + goto rel_rx; + + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0); + if (err) + goto rel_tx; + + /* TX-done queue handles skbs sent out by the NPEs */ + if (!ports_open) { + err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0); + if (err) + goto rel_txready; + } + return 0; + +rel_txready: + qmgr_release_queue(port->plat->txreadyq); +rel_tx: + qmgr_release_queue(TX_QUEUE(port->id)); +rel_rx: + qmgr_release_queue(port->plat->rxq); +rel_rxfree: + qmgr_release_queue(RXFREE_QUEUE(port->id)); + printk(KERN_DEBUG "%s: unable to request hardware queues\n", + port->netdev->name); + return err; +} + +static void release_queues(struct port *port) +{ + qmgr_release_queue(RXFREE_QUEUE(port->id)); + qmgr_release_queue(port->plat->rxq); + qmgr_release_queue(TX_QUEUE(port->id)); + qmgr_release_queue(port->plat->txreadyq); + + if (!ports_open) + qmgr_release_queue(TXDONE_QUEUE); +} + +static int init_queues(struct port *port) +{ + int i; + + if (!ports_open) + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, + POOL_ALLOC_SIZE, 32, 0))) + return -ENOMEM; + + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, + &port->desc_tab_phys))) + return -ENOMEM; + memset(port->desc_tab, 0, POOL_ALLOC_SIZE); + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); + + /* Setup RX buffers */ + for (i = 0; i < RX_DESCS; i++) { + struct desc *desc = rx_desc_ptr(port, i); + buffer_t *buff; /* skb or kmalloc()ated memory */ + void *data; +#ifdef __ARMEB__ + if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) + return -ENOMEM; + data = buff->data; +#else + if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) + return -ENOMEM; + data = buff; +#endif + desc->buf_len = MAX_MRU; + desc->data = dma_map_single(&port->netdev->dev, data, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(desc->data)) { + free_buffer(buff); + return -EIO; + } + desc->data += NET_IP_ALIGN; + port->rx_buff_tab[i] = buff; + } + + return 0; +} + +static void destroy_queues(struct port *port) +{ + int i; + + if (port->desc_tab) { + for (i = 0; i < RX_DESCS; i++) { + struct desc *desc = rx_desc_ptr(port, i); + buffer_t *buff = port->rx_buff_tab[i]; + if (buff) { + dma_unmap_single(&port->netdev->dev, + desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + free_buffer(buff); + } + } + for (i = 0; i < TX_DESCS; i++) { + struct desc *desc = tx_desc_ptr(port, i); + buffer_t *buff = port->tx_buff_tab[i]; + if (buff) { + dma_unmap_tx(port, desc); + free_buffer(buff); + } + } + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); + port->desc_tab = NULL; + } + + if (!ports_open && dma_pool) { + dma_pool_destroy(dma_pool); + dma_pool = NULL; + } +} + +static int eth_open(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + struct npe *npe = port->npe; + struct msg msg; + int i, err; + + if (!npe_running(npe)) { + err = npe_load_firmware(npe, npe_name(npe), &dev->dev); + if (err) + return err; + + if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { + printk(KERN_ERR "%s: %s not responding\n", dev->name, + npe_name(npe)); + return -EIO; + } + } + + mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr); + + memset(&msg, 0, sizeof(msg)); + msg.cmd = NPE_VLAN_SETRXQOSENTRY; + msg.eth_id = port->id; + msg.byte5 = port->plat->rxq | 0x80; + msg.byte7 = port->plat->rxq << 4; + for (i = 0; i < 8; i++) { + msg.byte3 = i; + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) + return -EIO; + } + + msg.cmd = NPE_EDB_SETPORTADDRESS; + msg.eth_id = PHYSICAL_ID(port->id); + msg.byte2 = dev->dev_addr[0]; + msg.byte3 = dev->dev_addr[1]; + msg.byte4 = dev->dev_addr[2]; + msg.byte5 = dev->dev_addr[3]; + msg.byte6 = dev->dev_addr[4]; + msg.byte7 = dev->dev_addr[5]; + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) + return -EIO; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = NPE_FW_SETFIREWALLMODE; + msg.eth_id = port->id; + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) + return -EIO; + + if ((err = request_queues(port)) != 0) + return err; + + if ((err = init_queues(port)) != 0) { + destroy_queues(port); + release_queues(port); + return err; + } + + for (i = 0; i < ETH_ALEN; i++) + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); + __raw_writel(0x08, &port->regs->random_seed); + __raw_writel(0x12, &port->regs->partial_empty_threshold); + __raw_writel(0x30, &port->regs->partial_full_threshold); + __raw_writel(0x08, &port->regs->tx_start_bytes); + __raw_writel(0x15, &port->regs->tx_deferral); + __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); + __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); + __raw_writel(0x80, &port->regs->slot_time); + __raw_writel(0x01, &port->regs->int_clock_threshold); + + /* Populate queues with buffers, no failure after this point */ + for (i = 0; i < TX_DESCS; i++) + queue_put_desc(port->plat->txreadyq, + tx_desc_phys(port, i), tx_desc_ptr(port, i)); + + for (i = 0; i < RX_DESCS; i++) + queue_put_desc(RXFREE_QUEUE(port->id), + rx_desc_phys(port, i), rx_desc_ptr(port, i)); + + __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); + __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); + __raw_writel(0, &port->regs->rx_control[1]); + __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); + + napi_enable(&port->napi); + phy_check_media(port, 1); + eth_set_mcast_list(dev); + netif_start_queue(dev); + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL); + + qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, + eth_rx_irq, dev); + if (!ports_open) { + qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, + eth_txdone_irq, NULL); + qmgr_enable_irq(TXDONE_QUEUE); + } + ports_open++; + netif_rx_schedule(dev, &port->napi); /* we may already have RX data, enables IRQ */ + return 0; +} + +static int eth_close(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + struct msg msg; + int buffs = RX_DESCS; /* allocated RX buffers */ + int i; + + ports_open--; + qmgr_disable_irq(port->plat->rxq); + napi_disable(&port->napi); + netif_stop_queue(dev); + + while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) + buffs--; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = NPE_SETLOOPBACK_MODE; + msg.eth_id = port->id; + msg.byte3 = 1; + if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) + printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name); + + i = 0; + do { /* drain RX buffers */ + while (queue_get_desc(port->plat->rxq, port, 0) >= 0) + buffs--; + if (!buffs) + break; + if (qmgr_stat_empty(TX_QUEUE(port->id))) { + /* we have to inject some packet */ + struct desc *desc; + u32 phys; + int n = queue_get_desc(port->plat->txreadyq, port, 1); + BUG_ON(n < 0); + desc = tx_desc_ptr(port, n); + phys = tx_desc_phys(port, n); + desc->buf_len = desc->pkt_len = 1; + wmb(); + queue_put_desc(TX_QUEUE(port->id), phys, desc); + } + udelay(1); + } while (++i < MAX_CLOSE_WAIT); + + if (buffs) + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" + " left in NPE\n", dev->name, buffs); +#if DEBUG_CLOSE + if (!buffs) + printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i); +#endif + + buffs = TX_DESCS; + while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) + buffs--; /* cancel TX */ + + i = 0; + do { + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) + buffs--; + if (!buffs) + break; + } while (++i < MAX_CLOSE_WAIT); + + if (buffs) + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " + "left in NPE\n", dev->name, buffs); +#if DEBUG_CLOSE + if (!buffs) + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); +#endif + + msg.byte3 = 0; + if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) + printk(KERN_CRIT "%s: unable to disable loopback\n", + dev->name); + + port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) & + ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */ + mdio_write(dev, port->plat->phy, MII_BMCR, + port->mii_bmcr | BMCR_PDOWN); + + if (!ports_open) + qmgr_disable_irq(TXDONE_QUEUE); + cancel_rearming_delayed_work(&port->mdio_thread); + destroy_queues(port); + release_queues(port); + return 0; +} + +static int __devinit eth_init_one(struct platform_device *pdev) +{ + struct port *port; + struct net_device *dev; + struct eth_plat_info *plat = pdev->dev.platform_data; + u32 regs_phys; + int err; + + if (!(dev = alloc_etherdev(sizeof(struct port)))) + return -ENOMEM; + + SET_NETDEV_DEV(dev, &pdev->dev); + port = netdev_priv(dev); + port->netdev = dev; + port->id = pdev->id; + + switch (port->id) { + case IXP4XX_ETH_NPEA: + port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT; + regs_phys = IXP4XX_EthA_BASE_PHYS; + break; + case IXP4XX_ETH_NPEB: + port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; + regs_phys = IXP4XX_EthB_BASE_PHYS; + break; + case IXP4XX_ETH_NPEC: + port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; + regs_phys = IXP4XX_EthC_BASE_PHYS; + break; + default: + err = -ENOSYS; + goto err_free; + } + + dev->open = eth_open; + dev->hard_start_xmit = eth_xmit; + dev->stop = eth_close; + dev->get_stats = eth_stats; + dev->do_ioctl = eth_ioctl; + dev->set_multicast_list = eth_set_mcast_list; + dev->tx_queue_len = 100; + + netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT); + + if (!(port->npe = npe_request(NPE_ID(port->id)))) { + err = -EIO; + goto err_free; + } + + if (register_netdev(dev)) { + err = -EIO; + goto err_npe_rel; + } + + port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name); + if (!port->mem_res) { + err = -EBUSY; + goto err_unreg; + } + + port->plat = plat; + npe_port_tab[NPE_ID(port->id)] = port; + memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN); + + platform_set_drvdata(pdev, dev); + + __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, + &port->regs->core_control); + udelay(50); + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); + udelay(50); + + port->mii.dev = dev; + port->mii.mdio_read = mdio_read; + port->mii.mdio_write = mdio_write; + port->mii.phy_id = plat->phy; + port->mii.phy_id_mask = 0x1F; + port->mii.reg_num_mask = 0x1F; + + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, + npe_name(port->npe)); + + phy_reset(dev, plat->phy); + port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) & + ~(BMCR_RESET | BMCR_PDOWN); + mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN); + + INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread); + return 0; + +err_unreg: + unregister_netdev(dev); +err_npe_rel: + npe_release(port->npe); +err_free: + free_netdev(dev); + return err; +} + +static int __devexit eth_remove_one(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct port *port = netdev_priv(dev); + + unregister_netdev(dev); + npe_port_tab[NPE_ID(port->id)] = NULL; + platform_set_drvdata(pdev, NULL); + npe_release(port->npe); + release_resource(port->mem_res); + free_netdev(dev); + return 0; +} + +static struct platform_driver drv = { + .driver.name = DRV_NAME, + .probe = eth_init_one, + .remove = eth_remove_one, +}; + +static int __init eth_init_module(void) +{ + if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) + return -ENOSYS; + + /* All MII PHY accesses use NPE-B Ethernet registers */ + spin_lock_init(&mdio_lock); + mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); + + return platform_driver_register(&drv); +} + +static void __exit eth_cleanup_module(void) +{ + platform_driver_unregister(&drv); +} + +MODULE_AUTHOR("Krzysztof Halasa"); +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:ixp4xx_eth"); +module_init(eth_init_module); +module_exit(eth_cleanup_module); diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig index a3df09e..94e7aa7 100644 --- a/drivers/net/wan/Kconfig +++ b/drivers/net/wan/Kconfig @@ -334,6 +334,15 @@ config DSCC4_PCI_RST Say Y if your card supports this feature. +config IXP4XX_HSS + tristate "IXP4xx HSS (synchronous serial port) support" + depends on HDLC && ARM && ARCH_IXP4XX + select IXP4XX_NPE + select IXP4XX_QMGR + help + Say Y here if you want to use built-in HSS ports + on IXP4xx processor. + config DLCI tristate "Frame Relay DLCI support" ---help--- diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile index d61fef3..1b1d116 100644 --- a/drivers/net/wan/Makefile +++ b/drivers/net/wan/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o obj-$(CONFIG_WANXL) += wanxl.o obj-$(CONFIG_PCI200SYN) += pci200syn.o obj-$(CONFIG_PC300TOO) += pc300too.o +obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o clean-files := wanxlfw.inc $(obj)/wanxl.o: $(obj)/wanxlfw.inc diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c new file mode 100644 index 0000000..cf971b3 --- /dev/null +++ b/drivers/net/wan/ixp4xx_hss.c @@ -0,0 +1,2886 @@ +/* + * Intel IXP4xx HSS (synchronous serial port) driver for Linux + * + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEBUG_QUEUES 0 +#define DEBUG_DESC 0 +#define DEBUG_RX 0 +#define DEBUG_TX 0 +#define DEBUG_PKT_BYTES 0 +#define DEBUG_CLOSE 0 +#define DEBUG_FRAMER 0 + +#define DRV_NAME "ixp4xx_hss" + +#define PKT_EXTRA_FLAGS 0 /* orig 1 */ +#define TX_FRAME_SYNC_OFFSET 0 /* channelized */ +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */ +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */ + +#define RX_DESCS 16 /* also length of all RX queues */ +#define TX_DESCS 16 /* also length of all TX queues */ + +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */ +#define MAX_CLOSE_WAIT 1000 /* microseconds */ +#define HSS_COUNT 2 +#define MIN_FRAME_SIZE 16 /* bits */ +#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */ +#define MAX_CHANNELS (MAX_FRAME_SIZE / 8) +#define MAX_CHAN_DEVICES 32 +#define CHANNEL_HDLC 0xFE +#define CHANNEL_UNUSED 0xFF + +#define NAPI_WEIGHT 16 +#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */ +#define CHAN_RX_FRAMES 64 +#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3) +#define CHAN_TX_LIST_FRAMES 16 /* bytes/channel per list, 16 - 48 */ +#define CHAN_TX_LISTS 8 +#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS) +#define CHAN_QUEUE_LEN 16 /* minimum possible */ + + +/* Queue IDs */ +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */ +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */ +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */ +#define HSS0_PKT_TX1_QUEUE 15 +#define HSS0_PKT_TX2_QUEUE 16 +#define HSS0_PKT_TX3_QUEUE 17 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */ +#define HSS0_PKT_RXFREE1_QUEUE 19 +#define HSS0_PKT_RXFREE2_QUEUE 20 +#define HSS0_PKT_RXFREE3_QUEUE 21 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */ + +#define HSS1_CHL_RXTRIG_QUEUE 10 +#define HSS1_PKT_RX_QUEUE 0 +#define HSS1_PKT_TX0_QUEUE 5 +#define HSS1_PKT_TX1_QUEUE 6 +#define HSS1_PKT_TX2_QUEUE 7 +#define HSS1_PKT_TX3_QUEUE 8 +#define HSS1_PKT_RXFREE0_QUEUE 1 +#define HSS1_PKT_RXFREE1_QUEUE 2 +#define HSS1_PKT_RXFREE2_QUEUE 3 +#define HSS1_PKT_RXFREE3_QUEUE 4 +#define HSS1_PKT_TXDONE_QUEUE 9 + +#define NPE_PKT_MODE_HDLC 0 +#define NPE_PKT_MODE_RAW 1 +#define NPE_PKT_MODE_56KMODE 2 +#define NPE_PKT_MODE_56KENDIAN_MSB 4 + +/* PKT_PIPE_HDLC_CFG_WRITE flags */ +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */ +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */ + + +/* hss_config, PCRs */ +/* Frame sync sampling, default = active low */ +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000 + +/* Frame sync pin: input (default) or output generated off a given clk edge */ +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000 + +/* Frame and data clock sampling on edge, default = falling */ +#define PCR_FCLK_EDGE_RISING 0x08000000 +#define PCR_DCLK_EDGE_RISING 0x04000000 + +/* Clock direction, default = input */ +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000 + +/* Generate/Receive frame pulses, default = enabled */ +#define PCR_FRM_PULSE_DISABLED 0x01000000 + + /* Data rate is full (default) or half the configured clk speed */ +#define PCR_HALF_CLK_RATE 0x00200000 + +/* Invert data between NPE and HSS FIFOs? (default = no) */ +#define PCR_DATA_POLARITY_INVERT 0x00100000 + +/* TX/RX endianness, default = LSB */ +#define PCR_MSB_ENDIAN 0x00080000 + +/* Normal (default) / open drain mode (TX only) */ +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000 + +/* No framing bit transmitted and expected on RX? (default = framing bit) */ +#define PCR_SOF_NO_FBIT 0x00020000 + +/* Drive data pins? */ +#define PCR_TX_DATA_ENABLE 0x00010000 + +/* Voice 56k type: drive the data pins low (default), high, high Z */ +#define PCR_TX_V56K_HIGH 0x00002000 +#define PCR_TX_V56K_HIGH_IMP 0x00004000 + +/* Unassigned type: drive the data pins low (default), high, high Z */ +#define PCR_TX_UNASS_HIGH 0x00000800 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000 + +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */ +#define PCR_TX_FB_HIGH_IMP 0x00000400 + +/* 56k data endiannes - which bit unused: high (default) or low */ +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200 + +/* 56k data transmission type: 32/8 bit data (default) or 56K data */ +#define PCR_TX_56KS_56K_DATA 0x00000100 + +/* hss_config, cCR */ +/* Number of packetized clients, default = 1 */ +#define CCR_NPE_HFIFO_2_HDLC 0x04000000 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000 + +/* default = no loopback */ +#define CCR_LOOPBACK 0x02000000 + +/* HSS number, default = 0 (first) */ +#define CCR_SECOND_HSS 0x01000000 + + +/* hss_config, clkCR: main:10, num:10, denom:12 */ +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/ + +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15) +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47) +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192) +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63) +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127) +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255) + +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127) +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383) +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385) +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511) +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023) +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047) + + +/* hss_config, LUT entries */ +#define TDMMAP_UNASSIGNED 0 +#define TDMMAP_HDLC 1 /* HDLC - packetized */ +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */ + +/* offsets into HSS config */ +#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */ +#define HSS_CONFIG_RX_PCR 0x04 +#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */ +#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */ +#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */ +#define HSS_CONFIG_RX_FCR 0x14 +#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */ +#define HSS_CONFIG_RX_LUT 0x38 + + +/* NPE command codes */ +/* writes the ConfigWord value to the location specified by offset */ +#define PORT_CONFIG_WRITE 0x40 + +/* triggers the NPE to load the contents of the configuration table */ +#define PORT_CONFIG_LOAD 0x41 + +/* triggers the NPE to return an HssErrorReadResponse message */ +#define PORT_ERROR_READ 0x42 + +/* reset NPE internal status and enable the HssChannelized operation */ +#define CHAN_FLOW_ENABLE 0x43 +#define CHAN_FLOW_DISABLE 0x44 +#define CHAN_IDLE_PATTERN_WRITE 0x45 +#define CHAN_NUM_CHANS_WRITE 0x46 +#define CHAN_RX_BUF_ADDR_WRITE 0x47 +#define CHAN_RX_BUF_CFG_WRITE 0x48 +#define CHAN_TX_BLK_CFG_WRITE 0x49 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A +#define CHAN_TX_BUF_SIZE_WRITE 0x4B +#define CHAN_TSLOTSWITCH_ENABLE 0x4C +#define CHAN_TSLOTSWITCH_DISABLE 0x4D + +/* downloads the gainWord value for a timeslot switching channel associated + with bypassNum */ +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E + +/* triggers the NPE to reset internal status and enable the HssPacketized + operation for the flow specified by pPipe */ +#define PKT_PIPE_FLOW_ENABLE 0x50 +#define PKT_PIPE_FLOW_DISABLE 0x51 +#define PKT_NUM_PIPES_WRITE 0x52 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55 +#define PKT_PIPE_RX_SIZE_WRITE 0x56 +#define PKT_PIPE_MODE_WRITE 0x57 + +/* HDLC packet status values - desc->status */ +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */ +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving + this packet (if buf_len < pkt_len) */ +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */ +#define ERR_HDLC_ABORT 6 /* abort sequence received */ +#define ERR_DISCONNECTING 7 /* disconnect is in progress */ + + +enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704}; +enum error_bit {TX_ERROR_BIT = 0, RX_ERROR_BIT = 1}; +enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST }; + +#ifdef __ARMEB__ +typedef struct sk_buff buffer_t; +#define free_buffer dev_kfree_skb +#define free_buffer_irq dev_kfree_skb_irq +#else +typedef void buffer_t; +#define free_buffer kfree +#define free_buffer_irq kfree +#endif + +struct chan_device { + struct cdev cdev; + struct device *dev; + struct port *port; + unsigned int open_count, excl_open; + unsigned int tx_first, tx_count, rx_first, rx_count; /* bytes */ + unsigned long errors_bitmap; + u8 id, chan_count; + u8 log_channels[MAX_CHANNELS]; +}; + +struct port { + struct device *dev; + struct npe *npe; + struct net_device *netdev; + struct napi_struct napi; + struct hss_plat_info *plat; + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; + struct desc *desc_tab; /* coherent */ + u32 desc_tab_phys; + unsigned int id; + atomic_t chan_tx_irq_number, chan_rx_irq_number; + wait_queue_head_t chan_tx_waitq, chan_rx_waitq; + u8 hdlc_cfg; + + /* the following fields must be protected by npe_lock */ + enum mode mode; + unsigned int clock_type, clock_rate, loopback; + unsigned int frame_size, frame_sync_offset; + + struct chan_device *chan_devices[MAX_CHAN_DEVICES]; + u8 *chan_buf; + u32 chan_tx_buf_phys, chan_rx_buf_phys; + unsigned int chan_open_count, hdlc_open; + unsigned int chan_started, initialized, just_set_offset; + enum alignment aligned, carrier; + unsigned int chan_last_rx, chan_last_tx; + /* assigned channels, may be invalid with given frame length or mode */ + u8 channels[MAX_CHANNELS]; + int msg_count; +}; + +/* NPE message structure */ +struct msg { +#ifdef __ARMEB__ + u8 cmd, unused, hss_port, index; + union { + struct { u8 data8a, data8b, data8c, data8d; }; + struct { u16 data16a, data16b; }; + struct { u32 data32; }; + }; +#else + u8 index, hss_port, unused, cmd; + union { + struct { u8 data8d, data8c, data8b, data8a; }; + struct { u16 data16b, data16a; }; + struct { u32 data32; }; + }; +#endif +}; + +/* HDLC packet descriptor */ +struct desc { + u32 next; /* pointer to next buffer, unused */ + +#ifdef __ARMEB__ + u16 buf_len; /* buffer length */ + u16 pkt_len; /* packet length */ + u32 data; /* pointer to data buffer in RAM */ + u8 status; + u8 error_count; + u16 __reserved; +#else + u16 pkt_len; /* packet length */ + u16 buf_len; /* buffer length */ + u32 data; /* pointer to data buffer in RAM */ + u16 __reserved; + u8 error_count; + u8 status; +#endif + u32 __reserved1[4]; +}; + + +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ + (n) * sizeof(struct desc)) +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) + +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ + ((n) + RX_DESCS) * sizeof(struct desc)) +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) + +#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES) +#define chan_tx_lists_len(port) (port->frame_size / 8 * CHAN_TX_LISTS * \ + sizeof(u32)) +#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES) + +#define chan_tx_buf(port) ((port)->chan_buf) +#define chan_tx_lists(port) (chan_tx_buf(port) + chan_tx_buf_len(port)) +#define chan_rx_buf(port) (chan_tx_lists(port) + chan_tx_lists_len(port)) + +#define chan_tx_lists_phys(port) ((port)->chan_tx_buf_phys + \ + chan_tx_buf_len(port)) + +static int hss_prepare_chan(struct port *port); +void hss_chan_stop(struct port *port); + +/***************************************************************************** + * global variables + ****************************************************************************/ + +static struct class *hss_class; +static int chan_major; +static int ports_open; +static struct dma_pool *dma_pool; +static spinlock_t npe_lock; + +static const struct { + int tx, txdone, rx, rxfree, chan; +}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE, + HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE}, + {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE, + HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE}, +}; + +/***************************************************************************** + * utility functions + ****************************************************************************/ + +static inline struct port* dev_to_port(struct net_device *dev) +{ + return dev_to_hdlc(dev)->priv; +} + +static inline struct chan_device* inode_to_chan_dev(struct inode *inode) +{ + return container_of(inode->i_cdev, struct chan_device, cdev); +} + +#ifndef __ARMEB__ +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) +{ + int i; + for (i = 0; i < cnt; i++) + dest[i] = swab32(src[i]); +} +#endif + +static int get_number(const char **buf, size_t *len, unsigned int *ptr, + unsigned int min, unsigned int max) +{ + char *endp; + unsigned long val = simple_strtoul(*buf, &endp, 10); + + if (endp == *buf || endp - *buf > *len || val < min || val > max) + return -EINVAL; + *len -= endp - *buf; + *buf = endp; + *ptr = val; + return 0; +} + +static int parse_channels(const char **buf, size_t *len, u8 *channels) +{ + unsigned int ch, next = 0; + + if (*len && (*buf)[*len - 1] == '\n') + (*len)--; + + memset(channels, 0, MAX_CHANNELS); + + if (!*len) + return 0; + + /* Format: "A,B-C,...", A > B > C */ + while (1) { + if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1)) + return -EINVAL; + channels[ch] = 1; + next = ch + 1; + if (!*len) + break; + if (**buf == ',') { + (*buf)++; + (*len)--; + continue; + } + if (**buf != '-') + return -EINVAL; + (*buf)++; + (*len)--; + if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1)) + return -EINVAL; + while (next <= ch) + channels[next++] = 1; + if (!*len) + break; + if (**buf != ',') + return -EINVAL; + (*buf)++; + (*len)--; + } + return 1; +} + +static size_t print_channels(struct port *port, char *buf, u8 id) +{ + unsigned int ch, cnt = 0; + size_t len = 0; + + for (ch = 0; ch < MAX_CHANNELS; ch++) + if (port->channels[ch] == id) { + if (cnt == 0) { + sprintf(buf + len, "%s%u", len ? "," : "", ch); + len += strlen(buf + len); + } + cnt++; + } else { + if (cnt > 1) { + sprintf(buf + len, "-%u", ch - 1); + len += strlen(buf + len); + } + cnt = 0; + } + if (cnt > 1) { + sprintf(buf + len, "-%u", ch - 1); + len += strlen(buf + len); + } + + buf[len++] = '\n'; + return len; +} + +static inline unsigned int sub_offset(unsigned int a, unsigned int b, + unsigned int modulo) +{ + return (modulo /* make sure the result >= 0 */ + a - b) % modulo; +} + +/***************************************************************************** + * HSS access + ****************************************************************************/ + +static void hss_config_load(struct port *port) +{ + struct msg msg; + + do { + memset(&msg, 0, sizeof(msg)); + msg.cmd = PORT_CONFIG_LOAD; + msg.hss_port = port->id; + if (npe_send_message(port->npe, &msg, "HSS_LOAD_CONFIG")) + break; + if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG")) + break; + + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) + break; + + /* HDLC may stop working without this */ + npe_recv_message(port->npe, &msg, "FLUSH_IT"); + return; + } while (0); + + printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n", + port->id); + BUG(); +} + +static void hss_config_set_pcr(struct port *port) +{ + struct msg msg; + + do { + memset(&msg, 0, sizeof(msg)); + msg.cmd = PORT_CONFIG_WRITE; + msg.hss_port = port->id; + msg.index = HSS_CONFIG_TX_PCR; + msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN | + PCR_TX_DATA_ENABLE; + if (port->frame_size % 8 == 0) + msg.data32 |= PCR_SOF_NO_FBIT; + if (port->clock_type == CLOCK_INT) + msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT; + if (npe_send_message(port->npe, &msg, "HSS_SET_TX_PCR")) + break; + + msg.index = HSS_CONFIG_RX_PCR; + msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING; + if (npe_send_message(port->npe, &msg, "HSS_SET_RX_PCR")) + break; + return; + } while (0); + + printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id); + BUG(); +} + +static void hss_config_set_hdlc_cfg(struct port *port) +{ + struct msg msg; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = PKT_PIPE_HDLC_CFG_WRITE; + msg.hss_port = port->id; + msg.data8a = port->hdlc_cfg; /* rx_cfg */ + msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */ + if (npe_send_message(port->npe, &msg, "HSS_SET_HDLC_CFG")) { + printk(KERN_CRIT "HSS-%i: unable to set HSS HDLC" + " configuration\n", port->id); + BUG(); + } +} + +static void hss_config_set_core(struct port *port) +{ + struct msg msg; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = PORT_CONFIG_WRITE; + msg.hss_port = port->id; + msg.index = HSS_CONFIG_CORE_CR; + msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) | + (port->id ? CCR_SECOND_HSS : 0); + if (npe_send_message(port->npe, &msg, "HSS_SET_CORE_CR")) { + printk(KERN_CRIT "HSS-%i: unable to set HSS core control" + " register\n", port->id); + BUG(); + } +} + +static void hss_config_set_line(struct port *port) +{ + struct msg msg; + + hss_config_set_pcr(port); + hss_config_set_core(port); + + memset(&msg, 0, sizeof(msg)); + msg.cmd = PORT_CONFIG_WRITE; + msg.hss_port = port->id; + msg.index = HSS_CONFIG_CLOCK_CR; + msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */; + if (npe_send_message(port->npe, &msg, "HSS_SET_CLOCK_CR")) { + printk(KERN_CRIT "HSS-%i: unable to set HSS clock control" + " register\n", port->id); + BUG(); + } +} + +static void hss_config_set_rx_frame(struct port *port) +{ + struct msg msg; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = PORT_CONFIG_WRITE; + msg.hss_port = port->id; + msg.index = HSS_CONFIG_RX_FCR; + msg.data16a = port->frame_sync_offset; + msg.data16b = port->frame_size - 1; + if (npe_send_message(port->npe, &msg, "HSS_SET_RX_FCR")) { + printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size" + " and offset\n", port->id); + BUG(); + } +} + +static void hss_config_set_frame(struct port *port) +{ + struct msg msg; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = PORT_CONFIG_WRITE; + msg.hss_port = port->id; + msg.index = HSS_CONFIG_TX_FCR; + msg.data16a = TX_FRAME_SYNC_OFFSET; + msg.data16b = port->frame_size - 1; + if (npe_send_message(port->npe, &msg, "HSS_SET_TX_FCR")) { + printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size" + " and offset\n", port->id); + BUG(); + } + hss_config_set_rx_frame(port); +} + +static void hss_config_set_lut(struct port *port) +{ + struct msg msg; + int chan_count = 0, log_chan = 0, i, ch; + u32 lut[MAX_CHANNELS / 4]; + + memset(lut, 0, sizeof(lut)); + for (i = 0; i < MAX_CHAN_DEVICES; i++) + if (port->chan_devices[i]) + port->chan_devices[i]->chan_count = 0; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = PORT_CONFIG_WRITE; + msg.hss_port = port->id; + + for (ch = 0; ch < MAX_CHANNELS; ch++) { + struct chan_device *chdev = NULL; + unsigned int entry; + + if (port->channels[ch] < MAX_CHAN_DEVICES /* assigned */) + chdev = port->chan_devices[port->channels[ch]]; + + if (port->mode == MODE_G704 && ch == 0) + entry = TDMMAP_VOICE64K; /* PCM-31 pattern */ + else if (port->mode == MODE_HDLC || + port->channels[ch] == CHANNEL_HDLC) + entry = TDMMAP_HDLC; + else if (chdev && chdev->open_count) { + entry = TDMMAP_VOICE64K; + chdev->log_channels[chdev->chan_count++] = log_chan; + } else + entry = TDMMAP_UNASSIGNED; + if (entry == TDMMAP_VOICE64K) { + chan_count++; + log_chan++; + } + + msg.data32 >>= 2; + msg.data32 |= entry << 30; + + if (ch % 16 == 15) { + msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3); + if (npe_send_message(port->npe, &msg, "HSS_SET_TX_LUT")) + break; + + msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT; + if (npe_send_message(port->npe, &msg, "HSS_SET_RX_LUT")) + break; + } + } + if (ch != MAX_CHANNELS) { + printk(KERN_CRIT "HSS-%i: unable to set HSS channel look-up" + " table\n", port->id); + BUG(); + } + + hss_config_set_frame(port); + + if (!chan_count) + return; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = CHAN_NUM_CHANS_WRITE; + msg.hss_port = port->id; + msg.data8a = chan_count; + if (npe_send_message(port->npe, &msg, "CHAN_NUM_CHANS_WRITE")) { + printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n", + port->id); + BUG(); + } + + /* don't leak data */ + // FIXME memset(chan_tx_buf(port), 0, CHAN_TX_FRAMES * chan_count); + if (port->mode == MODE_G704) /* G.704 PCM-31 sync pattern */ + for (i = 0; i < CHAN_TX_FRAMES; i += 4) + *(u32*)(chan_tx_buf(port) + i) = 0x9BDF9BDF; + + for (i = 0; i < CHAN_TX_LISTS; i++) { + u32 phys = port->chan_tx_buf_phys + i * CHAN_TX_LIST_FRAMES; + u32 *list = ((u32 *)chan_tx_lists(port)) + i * chan_count; + for (ch = 0; ch < chan_count; ch++) + list[ch] = phys + ch * CHAN_TX_FRAMES; + } + dma_sync_single(port->dev, port->chan_tx_buf_phys, + chan_tx_buf_len(port) + chan_tx_lists_len(port), + DMA_TO_DEVICE); +} + +static u32 hss_config_get_status(struct port *port) +{ + struct msg msg; + + do { + memset(&msg, 0, sizeof(msg)); + msg.cmd = PORT_ERROR_READ; + msg.hss_port = port->id; + if (npe_send_message(port->npe, &msg, "PORT_ERROR_READ")) + break; + if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) + break; + + return msg.data32; + } while (0); + + printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id); + BUG(); +} + +static void hss_config_start_chan(struct port *port) +{ + struct msg msg; + + port->chan_last_tx = 0; + port->chan_last_rx = 0; + + do { + memset(&msg, 0, sizeof(msg)); + msg.cmd = CHAN_RX_BUF_ADDR_WRITE; + msg.hss_port = port->id; + msg.data32 = port->chan_rx_buf_phys; + if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_ADDR_WRITE")) + break; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = CHAN_TX_BUF_ADDR_WRITE; + msg.hss_port = port->id; + msg.data32 = chan_tx_lists_phys(port); + if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_ADDR_WRITE")) + break; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = CHAN_FLOW_ENABLE; + msg.hss_port = port->id; + if (npe_send_message(port->npe, &msg, "CHAN_FLOW_ENABLE")) + break; + port->chan_started = 1; + return; + } while (0); + + printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n", + port->id); + BUG(); +} + +static void hss_config_stop_chan(struct port *port) +{ + struct msg msg; + + if (!port->chan_started) + return; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = CHAN_FLOW_DISABLE; + msg.hss_port = port->id; + if (npe_send_message(port->npe, &msg, "CHAN_FLOW_DISABLE")) { + printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n", + port->id); + BUG(); + } + hss_config_get_status(port); /* make sure it's halted */ +} + +static void hss_config_start_hdlc(struct port *port) +{ + struct msg msg; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = PKT_PIPE_FLOW_ENABLE; + msg.hss_port = port->id; + msg.data32 = 0; + if (npe_send_message(port->npe, &msg, "HSS_ENABLE_PKT_PIPE")) { + printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n", + port->id); + BUG(); + } +} + +static void hss_config_stop_hdlc(struct port *port) +{ + struct msg msg; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = PKT_PIPE_FLOW_DISABLE; + msg.hss_port = port->id; + if (npe_send_message(port->npe, &msg, "HSS_DISABLE_PKT_PIPE")) { + printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n", + port->id); + BUG(); + } + hss_config_get_status(port); /* make sure it's halted */ +} + +static int hss_config_load_firmware(struct port *port) +{ + struct msg msg; + + if (port->initialized) + return 0; + + if (!npe_running(port->npe)) { + int err; + if ((err = npe_load_firmware(port->npe, npe_name(port->npe), + port->dev))) + return err; + } + + do { + /* HSS main configuration */ + hss_config_set_line(port); + + hss_config_set_frame(port); + + /* HDLC mode configuration */ + memset(&msg, 0, sizeof(msg)); + msg.cmd = PKT_NUM_PIPES_WRITE; + msg.hss_port = port->id; + msg.data8a = PKT_NUM_PIPES; + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_PIPES")) + break; + + msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE; + msg.data8a = PKT_PIPE_FIFO_SIZEW; + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_FIFO")) + break; + + msg.cmd = PKT_PIPE_MODE_WRITE; + msg.data8a = NPE_PKT_MODE_HDLC; + /* msg.data8b = inv_mask */ + /* msg.data8c = or_mask */ + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_MODE")) + break; + + msg.cmd = PKT_PIPE_RX_SIZE_WRITE; + msg.data16a = HDLC_MAX_MRU; /* including CRC */ + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_RX_SIZE")) + break; + + msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE; + msg.data32 = 0x7F7F7F7F; /* ??? FIXME */ + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_IDLE")) + break; + + /* Channelized operation settings */ + memset(&msg, 0, sizeof(msg)); + msg.cmd = CHAN_TX_BLK_CFG_WRITE; + msg.hss_port = port->id; + msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2; + msg.data8a = msg.data8b / 4; + msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b; + msg.data8c = msg.data8d / 4; + if (npe_send_message(port->npe, &msg, "CHAN_TX_BLK_CFG_WRITE")) + break; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = CHAN_RX_BUF_CFG_WRITE; + msg.hss_port = port->id; + msg.data8a = CHAN_RX_TRIGGER / 8; + msg.data8b = CHAN_RX_FRAMES; + if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_CFG_WRITE")) + break; + + memset(&msg, 0, sizeof(msg)); + msg.cmd = CHAN_TX_BUF_SIZE_WRITE; + msg.hss_port = port->id; + msg.data8a = CHAN_TX_LISTS; + if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_SIZE_WRITE")) + break; + + port->initialized = 1; + return 0; + } while (0); + + printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id); + BUG(); +} + +/***************************************************************************** + * packetized (HDLC) operation + ****************************************************************************/ + +static inline void debug_pkt(struct net_device *dev, const char *func, + u8 *data, int len) +{ +#if DEBUG_PKT_BYTES + int i; + + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); + for (i = 0; i < len; i++) { + if (i >= DEBUG_PKT_BYTES) + break; + printk(KERN_DEBUG "%s%02X", !(i % 4) ? " " : "", data[i]); + } + printk(KERN_DEBUG "\n"); +#endif +} + + +static inline void debug_desc(u32 phys, struct desc *desc) +{ +#if DEBUG_DESC + printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n", + phys, desc->next, desc->buf_len, desc->pkt_len, + desc->data, desc->status, desc->error_count); +#endif +} + +static inline void debug_queue(unsigned int queue, int is_get, u32 phys) +{ +#if DEBUG_QUEUES + static struct { + int queue; + char *name; + } names[] = { + { HSS0_PKT_TX0_QUEUE, "TX#0 " }, + { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " }, + { HSS0_PKT_RX_QUEUE, "RX#0 " }, + { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " }, + { HSS1_PKT_TX0_QUEUE, "TX#1 " }, + { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " }, + { HSS1_PKT_RX_QUEUE, "RX#1 " }, + { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " }, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(names); i++) + if (names[i].queue == queue) + break; + + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue, + i < ARRAY_SIZE(names) ? names[i].name : "", + is_get ? "->" : "<-", phys); +#endif +} + +static inline u32 queue_get_entry(unsigned int queue) +{ + u32 phys = qmgr_get_entry(queue); + debug_queue(queue, 1, phys); + return phys; +} + +static inline int queue_get_desc(unsigned int queue, struct port *port, + int is_tx) +{ + u32 phys, tab_phys, n_desc; + struct desc *tab; + + if (!(phys = queue_get_entry(queue))) + return -1; + + BUG_ON(phys & 0x1F); + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); + n_desc = (phys - tab_phys) / sizeof(struct desc); + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); + debug_desc(phys, &tab[n_desc]); + BUG_ON(tab[n_desc].next); + return n_desc; +} + +static inline void queue_put_desc(unsigned int queue, u32 phys, + struct desc *desc) +{ + debug_queue(queue, 0, phys); + debug_desc(phys, desc); + BUG_ON(phys & 0x1F); + qmgr_put_entry(queue, phys); + BUG_ON(qmgr_stat_overflow(queue)); +} + + +static inline void dma_unmap_tx(struct port *port, struct desc *desc) +{ +#ifdef __ARMEB__ + dma_unmap_single(&port->netdev->dev, desc->data, + desc->buf_len, DMA_TO_DEVICE); +#else + dma_unmap_single(&port->netdev->dev, desc->data & ~3, + ALIGN((desc->data & 3) + desc->buf_len, 4), + DMA_TO_DEVICE); +#endif +} + + +static void hss_hdlc_set_carrier(void *pdev, int carrier) +{ + struct net_device *netdev = pdev; + struct port *port = dev_to_port(netdev); + unsigned long flags; + + spin_lock_irqsave(&npe_lock, flags); + port->carrier = carrier; + if (!port->loopback) { + if (carrier) + netif_carrier_on(netdev); + else + netif_carrier_off(netdev); + } + spin_unlock_irqrestore(&npe_lock, flags); +} + +static void hss_hdlc_rx_irq(void *pdev) +{ + struct net_device *dev = pdev; + struct port *port = dev_to_port(dev); + +#if DEBUG_RX + printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name); +#endif + qmgr_disable_irq(queue_ids[port->id].rx); + netif_rx_schedule(dev, &port->napi); +} + +static int hss_hdlc_poll(struct napi_struct *napi, int budget) +{ + struct port *port = container_of(napi, struct port, napi); + struct net_device *dev = port->netdev; + unsigned int rxq = queue_ids[port->id].rx; + unsigned int rxfreeq = queue_ids[port->id].rxfree; + struct net_device_stats *stats = hdlc_stats(dev); + int received = 0; + +#if DEBUG_RX + printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name); +#endif + + while (received < budget) { + struct sk_buff *skb; + struct desc *desc; + int n; +#ifdef __ARMEB__ + struct sk_buff *temp; + u32 phys; +#endif + + if ((n = queue_get_desc(rxq, port, 0)) < 0) { + received = 0; /* No packet received */ +#if DEBUG_RX + printk(KERN_DEBUG "%s: hss_hdlc_poll" + " netif_rx_complete\n", dev->name); +#endif + netif_rx_complete(dev, napi); + qmgr_enable_irq(rxq); + if (!qmgr_stat_empty(rxq) && + netif_rx_reschedule(dev, napi)) { +#if DEBUG_RX + printk(KERN_DEBUG "%s: hss_hdlc_poll" + " netif_rx_reschedule succeeded\n", + dev->name); +#endif + qmgr_disable_irq(rxq); + continue; + } +#if DEBUG_RX + printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n", + dev->name); +#endif + return 0; /* all work done */ + } + + desc = rx_desc_ptr(port, n); +#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */ + if (desc->error_count) + printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X" + " errors %u\n", dev->name, desc->status, + desc->error_count); +#endif + skb = NULL; + switch (desc->status) { + case 0: +#ifdef __ARMEB__ + if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) { + phys = dma_map_single(&dev->dev, skb->data, + RX_SIZE, + DMA_FROM_DEVICE); + if (dma_mapping_error(phys)) { + dev_kfree_skb(skb); + skb = NULL; + } + } +#else + skb = netdev_alloc_skb(dev, desc->pkt_len); +#endif + if (!skb) + stats->rx_dropped++; + break; + case ERR_HDLC_ALIGN: + case ERR_HDLC_ABORT: + stats->rx_frame_errors++; + stats->rx_errors++; + break; + case ERR_HDLC_FCS: + stats->rx_crc_errors++; + stats->rx_errors++; + break; + case ERR_HDLC_TOO_LONG: + stats->rx_length_errors++; + stats->rx_errors++; + break; + default: /* FIXME - remove printk */ + printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X" + " errors %u\n", dev->name, desc->status, + desc->error_count); + stats->rx_errors++; + } + + if (!skb) { + /* put the desc back on RX-ready queue */ + desc->buf_len = RX_SIZE; + desc->pkt_len = desc->status = 0; + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); + continue; + } + + /* process received frame */ +#ifdef __ARMEB__ + temp = skb; + skb = port->rx_buff_tab[n]; + dma_unmap_single(&dev->dev, desc->data, + RX_SIZE, DMA_FROM_DEVICE); +#else + dma_sync_single(&dev->dev, desc->data, + RX_SIZE, DMA_FROM_DEVICE); + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], + ALIGN(desc->pkt_len, 4) / 4); +#endif + skb_put(skb, desc->pkt_len); + + debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len); + + skb->protocol = hdlc_type_trans(skb, dev); + dev->last_rx = jiffies; + stats->rx_packets++; + stats->rx_bytes += skb->len; + netif_receive_skb(skb); + + /* put the new buffer on RX-free queue */ +#ifdef __ARMEB__ + port->rx_buff_tab[n] = temp; + desc->data = phys; +#endif + desc->buf_len = RX_SIZE; + desc->pkt_len = 0; + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); + received++; + } +#if DEBUG_RX + printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n"); +#endif + return received; /* not all work done */ +} + + +static void hss_hdlc_txdone_irq(void *pdev) +{ + struct net_device *dev = pdev; + struct port *port = dev_to_port(dev); + struct net_device_stats *stats = hdlc_stats(dev); + int n_desc; + +#if DEBUG_TX + printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n"); +#endif + while ((n_desc = queue_get_desc(queue_ids[port->id].txdone, + port, 1)) >= 0) { + struct desc *desc; + int start; + + desc = tx_desc_ptr(port, n_desc); + + stats->tx_packets++; + stats->tx_bytes += desc->pkt_len; + + dma_unmap_tx(port, desc); +#if DEBUG_TX + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n", + dev->name, port->tx_buff_tab[n_desc]); +#endif + free_buffer_irq(port->tx_buff_tab[n_desc]); + port->tx_buff_tab[n_desc] = NULL; + + start = qmgr_stat_empty(port->plat->txreadyq); + queue_put_desc(port->plat->txreadyq, + tx_desc_phys(port, n_desc), desc); + if (start) { +#if DEBUG_TX + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit" + " ready\n", dev->name); +#endif + netif_wake_queue(dev); + } + } +} + +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct port *port = dev_to_port(dev); + struct net_device_stats *stats = hdlc_stats(dev); + unsigned int txreadyq = port->plat->txreadyq; + int len, offset, bytes, n; + void *mem; + u32 phys; + struct desc *desc; + +#if DEBUG_TX + printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name); +#endif + + if (unlikely(skb->len > HDLC_MAX_MRU)) { + dev_kfree_skb(skb); + stats->tx_errors++; + return NETDEV_TX_OK; + } + + debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len); + + len = skb->len; +#ifdef __ARMEB__ + offset = 0; /* no need to keep alignment */ + bytes = len; + mem = skb->data; +#else + offset = (int)skb->data & 3; /* keep 32-bit alignment */ + bytes = ALIGN(offset + len, 4); + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { + dev_kfree_skb(skb); + stats->tx_dropped++; + return NETDEV_TX_OK; + } + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); + dev_kfree_skb(skb); +#endif + + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); + if (dma_mapping_error(phys)) { +#ifdef __ARMEB__ + dev_kfree_skb(skb); +#else + kfree(mem); +#endif + stats->tx_dropped++; + return NETDEV_TX_OK; + } + + n = queue_get_desc(txreadyq, port, 1); + BUG_ON(n < 0); + desc = tx_desc_ptr(port, n); + +#ifdef __ARMEB__ + port->tx_buff_tab[n] = skb; +#else + port->tx_buff_tab[n] = mem; +#endif + desc->data = phys + offset; + desc->buf_len = desc->pkt_len = len; + + wmb(); + queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc); + dev->trans_start = jiffies; + + if (qmgr_stat_empty(txreadyq)) { +#if DEBUG_TX + printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name); +#endif + netif_stop_queue(dev); + /* we could miss TX ready interrupt */ + if (!qmgr_stat_empty(txreadyq)) { +#if DEBUG_TX + printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n", + dev->name); +#endif + netif_wake_queue(dev); + } + } + +#if DEBUG_TX + printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name); +#endif + return NETDEV_TX_OK; +} + + +static int request_hdlc_queues(struct port *port) +{ + int err; + + err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0); + if (err) + return err; + + err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0); + if (err) + goto rel_rxfree; + + err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0); + if (err) + goto rel_rx; + + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0); + if (err) + goto rel_tx; + + err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0); + if (err) + goto rel_txready; + return 0; + +rel_txready: + qmgr_release_queue(port->plat->txreadyq); +rel_tx: + qmgr_release_queue(queue_ids[port->id].tx); +rel_rx: + qmgr_release_queue(queue_ids[port->id].rx); +rel_rxfree: + qmgr_release_queue(queue_ids[port->id].rxfree); + printk(KERN_DEBUG "%s: unable to request hardware queues\n", + port->netdev->name); + return err; +} + +static void release_hdlc_queues(struct port *port) +{ + qmgr_release_queue(queue_ids[port->id].rxfree); + qmgr_release_queue(queue_ids[port->id].rx); + qmgr_release_queue(queue_ids[port->id].txdone); + qmgr_release_queue(queue_ids[port->id].tx); + qmgr_release_queue(port->plat->txreadyq); +} + +static int init_hdlc_queues(struct port *port) +{ + int i; + + if (!ports_open) + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, + POOL_ALLOC_SIZE, 32, 0))) + return -ENOMEM; + + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, + &port->desc_tab_phys))) + return -ENOMEM; + memset(port->desc_tab, 0, POOL_ALLOC_SIZE); + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); + + /* Setup RX buffers */ + for (i = 0; i < RX_DESCS; i++) { + struct desc *desc = rx_desc_ptr(port, i); + buffer_t *buff; + void *data; +#ifdef __ARMEB__ + if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE))) + return -ENOMEM; + data = buff->data; +#else + if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL))) + return -ENOMEM; + data = buff; +#endif + desc->buf_len = RX_SIZE; + desc->data = dma_map_single(&port->netdev->dev, data, + RX_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(desc->data)) { + free_buffer(buff); + return -EIO; + } + port->rx_buff_tab[i] = buff; + } + + return 0; +} + +static void destroy_hdlc_queues(struct port *port) +{ + int i; + + if (port->desc_tab) { + for (i = 0; i < RX_DESCS; i++) { + struct desc *desc = rx_desc_ptr(port, i); + buffer_t *buff = port->rx_buff_tab[i]; + if (buff) { + dma_unmap_single(&port->netdev->dev, + desc->data, RX_SIZE, + DMA_FROM_DEVICE); + free_buffer(buff); + } + } + for (i = 0; i < TX_DESCS; i++) { + struct desc *desc = tx_desc_ptr(port, i); + buffer_t *buff = port->tx_buff_tab[i]; + if (buff) { + dma_unmap_tx(port, desc); + free_buffer(buff); + } + } + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); + port->desc_tab = NULL; + } + + if (!ports_open && dma_pool) { + dma_pool_destroy(dma_pool); + dma_pool = NULL; + } +} + +static int hss_hdlc_open(struct net_device *dev) +{ + struct port *port = dev_to_port(dev); + unsigned long flags; + int i, err = 0; + + if ((err = hdlc_open(dev))) + return err; + + if ((err = request_hdlc_queues(port))) + goto err_hdlc_close; + + if ((err = init_hdlc_queues(port))) + goto err_destroy_queues; + + spin_lock_irqsave(&npe_lock, flags); + + if (port->mode == MODE_G704 && port->channels[0] == CHANNEL_HDLC) { + err = -EBUSY; /* channel #0 is used for G.704 framing */ + goto err_unlock; + } + if (port->mode != MODE_HDLC) + for (i = port->frame_size / 8; i < MAX_CHANNELS; i++) + if (port->channels[i] == CHANNEL_HDLC) { + err = -ECHRNG; /* frame too short */ + goto err_unlock; + } + + if ((err = hss_config_load_firmware(port))) + goto err_unlock; + + if (!port->chan_open_count && port->plat->open) + if ((err = port->plat->open(port->id, dev, + hss_hdlc_set_carrier))) + goto err_unlock; + + if (port->mode == MODE_G704 && !port->chan_open_count) + if ((err = hss_prepare_chan(port))) + goto err_plat_close; + + spin_unlock_irqrestore(&npe_lock, flags); + + /* Populate queues with buffers, no failure after this point */ + for (i = 0; i < TX_DESCS; i++) + queue_put_desc(port->plat->txreadyq, + tx_desc_phys(port, i), tx_desc_ptr(port, i)); + + for (i = 0; i < RX_DESCS; i++) + queue_put_desc(queue_ids[port->id].rxfree, + rx_desc_phys(port, i), rx_desc_ptr(port, i)); + + napi_enable(&port->napi); + netif_start_queue(dev); + + qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY, + hss_hdlc_rx_irq, dev); + + qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY, + hss_hdlc_txdone_irq, dev); + qmgr_enable_irq(queue_ids[port->id].txdone); + + ports_open++; + port->hdlc_open = 1; + + hss_config_set_hdlc_cfg(port); + hss_config_set_lut(port); + hss_config_load(port); + + if (port->mode == MODE_G704 && !port->chan_open_count) + hss_config_start_chan(port); + + hss_config_start_hdlc(port); + + /* we may already have RX data, enables IRQ */ + netif_rx_schedule(dev, &port->napi); + return 0; + +err_plat_close: + if (!port->chan_open_count && port->plat->close) + port->plat->close(port->id, dev); +err_unlock: + spin_unlock_irqrestore(&npe_lock, flags); +err_destroy_queues: + destroy_hdlc_queues(port); + release_hdlc_queues(port); +err_hdlc_close: + hdlc_close(dev); + return err; +} + +static int hss_hdlc_close(struct net_device *dev) +{ + struct port *port = dev_to_port(dev); + unsigned long flags; + int i, buffs = RX_DESCS; /* allocated RX buffers */ + + spin_lock_irqsave(&npe_lock, flags); + ports_open--; + port->hdlc_open = 0; + qmgr_disable_irq(queue_ids[port->id].rx); + netif_stop_queue(dev); + napi_disable(&port->napi); + + hss_config_stop_hdlc(port); + + if (port->mode == MODE_G704 && !port->chan_open_count) + hss_chan_stop(port); + + while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0) + buffs--; + while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0) + buffs--; + + if (buffs) + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" + " left in NPE\n", dev->name, buffs); + + buffs = TX_DESCS; + while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0) + buffs--; /* cancel TX */ + + i = 0; + do { + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) + buffs--; + if (!buffs) + break; + } while (++i < MAX_CLOSE_WAIT); + + if (buffs) + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " + "left in NPE\n", dev->name, buffs); +#if DEBUG_CLOSE + if (!buffs) + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); +#endif + qmgr_disable_irq(queue_ids[port->id].txdone); + + if (!port->chan_open_count && port->plat->close) + port->plat->close(port->id, dev); + spin_unlock_irqrestore(&npe_lock, flags); + + destroy_hdlc_queues(port); + release_hdlc_queues(port); + hdlc_close(dev); + return 0; +} + + +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding, + unsigned short parity) +{ + struct port *port = dev_to_port(dev); + + if (encoding != ENCODING_NRZ) + return -EINVAL; + + switch(parity) { + case PARITY_CRC16_PR1_CCITT: + port->hdlc_cfg = 0; + return 0; + + case PARITY_CRC32_PR1_CCITT: + port->hdlc_cfg = PKT_HDLC_CRC_32; + return 0; + + default: + return -EINVAL; + } +} + + +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + const size_t size = sizeof(sync_serial_settings); + sync_serial_settings new_line; + sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; + struct port *port = dev_to_port(dev); + unsigned long flags; + int i, clk; + + if (cmd != SIOCWANDEV) + return hdlc_ioctl(dev, ifr, cmd); + + switch(ifr->ifr_settings.type) { + case IF_GET_IFACE: + ifr->ifr_settings.type = IF_IFACE_V35; + if (ifr->ifr_settings.size < size) { + ifr->ifr_settings.size = size; /* data size wanted */ + return -ENOBUFS; + } + memset(&new_line, 0, sizeof(new_line)); + new_line.clock_type = port->clock_type; + new_line.clock_rate = port->clock_rate; + new_line.loopback = port->loopback; + if (copy_to_user(line, &new_line, size)) + return -EFAULT; + + if (!port->chan_buf) + return 0; + + dma_sync_single(&dev->dev, port->chan_rx_buf_phys, + chan_rx_buf_len(port), DMA_FROM_DEVICE); + printk(KERN_DEBUG "RX:\n"); + for (i = 0; i < chan_rx_buf_len(port); i++) { + if (i % 32 == 0) + printk(KERN_DEBUG "%03X ", i); + printk("%02X%c", chan_rx_buf(port)[i], + (i + 1) % 32 ? ' ' : '\n'); + } + +#if 0 + printk(KERN_DEBUG "TX:\n"); + for (i = 0; i < /*CHAN_TX_FRAMES * 2*/ chan_tx_buf_len(port) + + chan_tx_lists_len(port); i++) { + if (i % 32 == 0) + printk(KERN_DEBUG "%03X ", i); + printk("%02X%c", chan_tx_buf(port)[i], + (i + 1) % 32 ? ' ' : '\n'); + } +#endif + port->msg_count = 10; + return 0; + + case IF_IFACE_SYNC_SERIAL: + case IF_IFACE_V35: + if(!capable(CAP_NET_ADMIN)) + return -EPERM; + if (copy_from_user(&new_line, line, size)) + return -EFAULT; + + clk = new_line.clock_type; + if (port->plat->set_clock) + clk = port->plat->set_clock(port->id, clk); + + if (clk != CLOCK_EXT && clk != CLOCK_INT) + return -EINVAL; /* No such clock setting */ + + if (new_line.loopback != 0 && new_line.loopback != 1) + return -EINVAL; + + port->clock_type = clk; /* Update settings */ + /* FIXME port->clock_rate = new_line.clock_rate */; + port->loopback = new_line.loopback; + + spin_lock_irqsave(&npe_lock, flags); + + if (port->chan_open_count || port->hdlc_open) { + hss_config_set_line(port); + hss_config_load(port); + } + if (port->loopback || port->carrier) + netif_carrier_on(port->netdev); + else + netif_carrier_off(port->netdev); + spin_unlock_irqrestore(&npe_lock, flags); + + return 0; + + default: + return hdlc_ioctl(dev, ifr, cmd); + } +} + +/***************************************************************************** + * channelized (G.704) operation + ****************************************************************************/ + +static void g704_rx_framer(struct port *port, unsigned int offset) +{ + u8 *data = chan_rx_buf(port) + sub_offset(offset, CHAN_RX_TRIGGER, + CHAN_RX_FRAMES); + unsigned int bit, frame, bad_even = 0, bad_odd = 0, cnt; + unsigned int is_first = port->just_set_offset; + u8 zeros_even, zeros_odd, ones_even, ones_odd; + enum alignment aligned; + + port->just_set_offset = 0; + dma_sync_single(port->dev, port->chan_rx_buf_phys, CHAN_RX_FRAMES, + DMA_FROM_DEVICE); + + /* check if aligned first */ + for (frame = 0; frame < CHAN_RX_TRIGGER && + (bad_even <= MAX_CHAN_RX_BAD_SYNC || + bad_odd <= MAX_CHAN_RX_BAD_SYNC); frame += 2) { + u8 ve = data[frame]; + u8 vo = data[frame + 1]; + + if ((ve & 0x7F) != 0x1B || !(vo & 0x40)) + bad_even++; + + if ((vo & 0x7F) != 0x1B || !(ve & 0x40)) + bad_odd++; + } + + if (bad_even <= MAX_CHAN_RX_BAD_SYNC) + aligned = EVEN_FIRST; + else if (bad_odd <= MAX_CHAN_RX_BAD_SYNC) + aligned = ODD_FIRST; + else + aligned = NOT_ALIGNED; + + if (aligned != NOT_ALIGNED) { + if (aligned == port->aligned) + return; /* no change */ + if (printk_ratelimit()) + printk(KERN_INFO "HSS-%i: synchronized at %u (%s frame" + " first)\n", port->id, port->frame_sync_offset, + aligned == EVEN_FIRST ? "even" : "odd"); + port->aligned = aligned; + + atomic_inc(&port->chan_tx_irq_number); + wake_up_interruptible(&port->chan_tx_waitq); + atomic_inc(&port->chan_rx_irq_number); + wake_up_interruptible(&port->chan_rx_waitq); + return; + } + + /* not aligned */ + if (port->aligned != NOT_ALIGNED && printk_ratelimit()) { + printk(KERN_INFO "HSS-%i: lost alignment\n", port->id); + port->aligned = NOT_ALIGNED; +#if DEBUG_FRAMER + for (cnt = 0; cnt < CHAN_RX_FRAMES; cnt++) + printk("%c%02X%s", cnt == offset ? '>' : ' ', + chan_rx_buf(port)[cnt], + (cnt + 1) % 32 ? "" : "\n"); +#endif + + for (cnt = 0; cnt < MAX_CHAN_DEVICES; cnt++) + if (port->chan_devices[cnt]) { + set_bit(TX_ERROR_BIT, &port->chan_devices[cnt] + ->errors_bitmap); + set_bit(RX_ERROR_BIT, &port->chan_devices[cnt] + ->errors_bitmap); + } + atomic_inc(&port->chan_tx_irq_number); + wake_up_interruptible(&port->chan_tx_waitq); + atomic_inc(&port->chan_rx_irq_number); + wake_up_interruptible(&port->chan_rx_waitq); + } + + if (is_first) + return; + + zeros_even = zeros_odd = 0; + ones_even = ones_odd = 0xFF; + for (frame = 0; frame < CHAN_RX_TRIGGER; frame += 2) { + zeros_even |= data[frame]; + zeros_odd |= data[frame + 1]; + ones_even &= data[frame]; + ones_odd &= data[frame + 1]; + } + + for (bit = 0; bit < 7; bit++) { + if ((zeros_even & ~0x9B) == 0 && (ones_even & 0x1B) == 0x1B && + (ones_odd & 0x40) == 0x40) { + aligned = EVEN_FIRST; /* maybe */ + break; + } + if ((zeros_odd & ~0x9B) == 0 && (ones_odd & 0x1B) == 0x1B && + (ones_even & 0x40) == 0x40) { + aligned = ODD_FIRST; /* maybe */ + break; + } + zeros_even <<= 1; + ones_even = ones_even << 1 | 1; + zeros_odd <<= 1; + ones_odd = ones_odd << 1 | 1; + } + + port->frame_sync_offset += port->frame_size - bit; + port->frame_sync_offset %= port->frame_size; + port->just_set_offset = 1; + +#if DEBUG_FRAMER + if (bit == 7) + printk(KERN_DEBUG "HSS-%i: trying frame sync at %u\n", + port->id, port->frame_sync_offset); + else + printk(KERN_DEBUG "HSS-%i: found possible frame sync pattern at" + " %u (%s frame first)\n", port->id, + port->frame_sync_offset, + aligned == EVEN_FIRST ? "even" : "odd"); +#endif + + hss_config_set_rx_frame(port); + hss_config_load(port); +} + +static void chan_process_tx_irq(struct chan_device *chan_dev, int offset) +{ + /* in bytes */ + unsigned int buff_len = CHAN_TX_FRAMES * chan_dev->chan_count; + unsigned int list_len = CHAN_TX_LIST_FRAMES * chan_dev->chan_count; + int eaten, last_offset = chan_dev->port->chan_last_tx * list_len; + + offset *= list_len; + eaten = sub_offset(offset, last_offset, buff_len); + + if (chan_dev->tx_count > eaten + 2 * list_len) { + /* two pages must be reserved for the transmitter */ + chan_dev->tx_first += eaten; + chan_dev->tx_first %= buff_len; + chan_dev->tx_count -= eaten; + } else { + /* FIXME check + 0 + 1 tx_first (may still be transmited) + 2 tx_offset (currently reported by the NPE) + 3 tx_first + 2 * list_len (free to write here) + 4 + 5 + */ + + /* printk(KERN_DEBUG "TX buffer underflow\n"); */ + chan_dev->tx_first = sub_offset(offset, list_len, buff_len); + chan_dev->tx_count = 2 * list_len; /* reserve */ + set_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap); + } +} + +static void chan_process_rx_irq(struct chan_device *chan_dev, int offset) +{ + /* in bytes */ + unsigned int buff_len = CHAN_RX_FRAMES * chan_dev->chan_count; + unsigned int trig_len = CHAN_RX_TRIGGER * chan_dev->chan_count; + int last_offset = chan_dev->port->chan_last_rx * chan_dev->chan_count; + + offset *= chan_dev->chan_count; + chan_dev->rx_count += sub_offset(offset, last_offset + trig_len, + buff_len) + trig_len; + if (chan_dev->rx_count > buff_len - 2 * trig_len) { + /* two pages - offset[0] and offset[1] are lost - FIXME check */ + /* printk(KERN_DEBUG "RX buffer overflow\n"); */ + chan_dev->rx_first = (offset + 2 * trig_len) % buff_len; + chan_dev->rx_count = buff_len - 2 * trig_len; + set_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap); + } +} + +static void hss_chan_irq(void *pdev) +{ + struct port *port = pdev; + u32 v; + +#if DEBUG_RX + printk(KERN_DEBUG DRV_NAME ": hss_chan_irq\n"); +#endif + spin_lock(&npe_lock); + while ((v = qmgr_get_entry(queue_ids[port->id].chan))) { + unsigned int first, errors, tx_list, rx_frame; + int i, bad; + + first = v >> 24; + errors = (v >> 16) & 0xFF; + tx_list = (v >> 8) & 0xFF; + rx_frame = v & 0xFF; + + if (port->msg_count) { + printk(KERN_DEBUG "chan_irq hss %i jiffies %lu first" + " 0x%02X errors 0x%02X tx_list 0x%02X rx_frame" + " 0x%02X\n", port->id, jiffies, first, errors, + tx_list, rx_frame); + port->msg_count--; + } + + BUG_ON(rx_frame % CHAN_RX_TRIGGER); + BUG_ON(rx_frame >= CHAN_RX_FRAMES); + BUG_ON(tx_list >= CHAN_TX_LISTS); + + bad = port->mode == MODE_G704 && port->aligned == NOT_ALIGNED; + if (!bad && tx_list != port->chan_last_tx) { + if (tx_list != (port->chan_last_tx + 1) % CHAN_TX_LISTS) + printk(KERN_DEBUG "Skipped an IRQ? Tx last %i" + " current %i\n", port->chan_last_tx, + tx_list); + for (i = 0; i < MAX_CHAN_DEVICES; i++) { + if (!port->chan_devices[i] || + !port->chan_devices[i]->open_count) + continue; + chan_process_tx_irq(port->chan_devices[i], + tx_list); + } + atomic_inc(&port->chan_tx_irq_number); +#if 0 + printk(KERN_DEBUG "wakeing up TX jiff %lu\n", + jiffies, errors); +#endif + wake_up_interruptible(&port->chan_tx_waitq); + } + + if (rx_frame != (port->chan_last_rx + CHAN_RX_TRIGGER) % + CHAN_RX_FRAMES) + printk(KERN_DEBUG "Skipped an IRQ? Rx last %i" + " current %i\n", port->chan_last_rx, rx_frame); + + if (port->mode == MODE_G704) + g704_rx_framer(port, rx_frame); + + if (!bad && + (port->mode != MODE_G704 || port->aligned != NOT_ALIGNED)) { + for (i = 0; i < MAX_CHAN_DEVICES; i++) { + if (!port->chan_devices[i] || + !port->chan_devices[i]->open_count) + continue; + chan_process_rx_irq(port->chan_devices[i], + rx_frame); + } + atomic_inc(&port->chan_rx_irq_number); + wake_up_interruptible(&port->chan_rx_waitq); + } + port->chan_last_tx = tx_list; + port->chan_last_rx = rx_frame; + } + spin_unlock(&npe_lock); +} + + +static int hss_prepare_chan(struct port *port) +{ + int err; + + if ((err = hss_config_load_firmware(port))) + return err; + + if ((err = qmgr_request_queue(queue_ids[port->id].chan, + CHAN_QUEUE_LEN, 0, 0))) + return err; + + if (!(port->chan_buf = kmalloc(chan_tx_buf_len(port) + + chan_tx_lists_len(port) + + chan_rx_buf_len(port), GFP_KERNEL))) { + goto release_queue; + err = -ENOBUFS; + } + + port->chan_tx_buf_phys = dma_map_single(port->dev, chan_tx_buf(port), + chan_tx_buf_len(port) + + chan_tx_lists_len(port), + DMA_TO_DEVICE); + if (dma_mapping_error(port->chan_tx_buf_phys)) { + err = -EIO; + goto free; + } + + port->chan_rx_buf_phys = dma_map_single(port->dev, chan_rx_buf(port), + chan_rx_buf_len(port), + DMA_FROM_DEVICE); + if (dma_mapping_error(port->chan_rx_buf_phys)) { + err = -EIO; + goto unmap_tx; + } + + qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY, + hss_chan_irq, port); + qmgr_enable_irq(queue_ids[port->id].chan); + hss_chan_irq(port); + return 0; + +unmap_tx: + dma_unmap_single(port->dev, port->chan_tx_buf_phys, + chan_tx_buf_len(port) + chan_tx_lists_len(port), + DMA_TO_DEVICE); +free: + kfree(port->chan_buf); + port->chan_buf = NULL; +release_queue: + qmgr_release_queue(queue_ids[port->id].chan); + return err; +} + +void hss_chan_stop(struct port *port) +{ + if (!port->chan_open_count && !port->hdlc_open) + qmgr_disable_irq(queue_ids[port->id].chan); + + hss_config_stop_chan(port); + hss_config_set_lut(port); + hss_config_load(port); + + if (!port->chan_open_count && !port->hdlc_open) { + dma_unmap_single(port->dev, port->chan_tx_buf_phys, + chan_tx_buf_len(port) + + chan_tx_lists_len(port), DMA_TO_DEVICE); + dma_unmap_single(port->dev, port->chan_rx_buf_phys, + chan_rx_buf_len(port), DMA_FROM_DEVICE); + kfree(port->chan_buf); + port->chan_buf = NULL; + qmgr_release_queue(queue_ids[port->id].chan); + } +} + +static int hss_chan_open(struct inode *inode, struct file *file) +{ + struct chan_device *chan_dev = inode_to_chan_dev(inode); + struct port *port = chan_dev->port; + unsigned long flags; + int i, err = 0; + + spin_lock_irqsave(&npe_lock, flags); + + if (chan_dev->open_count) { + if (chan_dev->excl_open || (file->f_flags & O_EXCL)) + err = -EBUSY; + else + chan_dev->open_count++; + goto out; + } + + if (port->mode == MODE_HDLC) { + err = -ENOSYS; + goto out; + } + + if (port->mode == MODE_G704 && port->channels[0] == chan_dev->id) { + err = -EBUSY; /* channel #0 is used for G.704 signaling */ + goto out; + } + for (i = MAX_CHANNELS; i > port->frame_size / 8; i--) + if (port->channels[i - 1] == chan_dev->id) { + err = -ECHRNG; /* frame too short */ + goto out; + } + + chan_dev->rx_first = chan_dev->tx_first = 0; + chan_dev->rx_count = chan_dev->tx_count = 0; + clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap); + clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap); + + if (!port->chan_open_count && !port->hdlc_open) { + if (port->plat->open) + if ((err = port->plat->open(port->id, port->netdev, + hss_hdlc_set_carrier))) + goto out; + if ((err = hss_prepare_chan(port))) { + if (port->plat->close) + port->plat->close(port->id, port->netdev); + goto out; + } + } + + hss_config_stop_chan(port); + chan_dev->open_count++; + port->chan_open_count++; + chan_dev->excl_open = !!file->f_flags & O_EXCL; + + hss_config_set_lut(port); + hss_config_load(port); + hss_config_start_chan(port); +out: + spin_unlock_irqrestore(&npe_lock, flags); + return err; +} + +static int hss_chan_release(struct inode *inode, struct file *file) +{ + struct chan_device *chan_dev = inode_to_chan_dev(inode); + struct port *port = chan_dev->port; + unsigned long flags; + + spin_lock_irqsave(&npe_lock, flags); + + if (!--chan_dev->open_count) { + if (!--port->chan_open_count && !port->hdlc_open) { + hss_chan_stop(port); + if (port->plat->close) + port->plat->close(port->id, port->netdev); + } else { + hss_config_stop_chan(port); + hss_config_set_lut(port); + hss_config_set_line(port); // + hss_config_start_chan(port); + } + } + + spin_unlock_irqrestore(&npe_lock, flags); + return 0; +} + +static ssize_t hss_chan_read(struct file *file, char __user *buf, size_t count, + loff_t *f_pos) +{ + struct chan_device *chan_dev = inode_to_chan_dev + (file->f_path.dentry->d_inode); + struct port *port = chan_dev->port; + unsigned long flags; + u8 *rx_buf; + int res = 0, loops = 0; + + spin_lock_irqsave(&npe_lock, flags); + + while (1) { + int prev_irq = atomic_read(&port->chan_rx_irq_number); +#if 0 + if (test_and_clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap) + || (port->mode == G704 && port->aligned == NOT_ALIGNED)) { + res = -EIO; + goto out; + } +#endif + if (count == 0) + goto out; /* no need to wait */ + + if (chan_dev->rx_count) + break; + + spin_unlock_irqrestore(&npe_lock, flags); + loops++; + if ((res = wait_event_interruptible + (port->chan_rx_waitq, + atomic_read(&port->chan_rx_irq_number) != prev_irq))) + goto out; + spin_lock_irqsave(&npe_lock, flags); + continue; + } + + dma_sync_single(port->dev, port->chan_rx_buf_phys, + chan_rx_buf_len(port), DMA_FROM_DEVICE); + +#if 0 + if (loops > 1) + printk(KERN_DEBUG "ENTRY rx_first %u rx_count %u count %i" + " last_rx %u loops %i\n", chan_dev->rx_first, + chan_dev->rx_count, count, port->chan_last_rx, loops); +#endif + rx_buf = chan_rx_buf(port); + while (chan_dev->rx_count > 0 && res < count) { + unsigned int chan = chan_dev->rx_first % chan_dev->chan_count; + unsigned int frame = chan_dev->rx_first / chan_dev->chan_count; + + chan = chan_dev->log_channels[chan]; + if (put_user(rx_buf[chan * CHAN_RX_FRAMES + frame], buf++)) { + res = -EFAULT; + goto out; + } + chan_dev->rx_first++; + chan_dev->rx_first %= CHAN_RX_FRAMES * chan_dev->chan_count; + chan_dev->rx_count--; + res++; + } +out: +#if 0 + printk(KERN_DEBUG "EXIT rx_first %u rx_count %u res %i\n", + chan_dev->rx_first, chan_dev->rx_count, res); +#endif + spin_unlock_irqrestore(&npe_lock, flags); + return res; +} + +static ssize_t hss_chan_write(struct file *file, const char __user *buf, + size_t count, loff_t *f_pos) +{ + struct chan_device *chan_dev = inode_to_chan_dev + (file->f_path.dentry->d_inode); + struct port *port = chan_dev->port; + unsigned long flags; + u8 *tx_buf; + int res = 0, loops = 0; + + spin_lock_irqsave(&npe_lock, flags); + while (1) { + int prev_irq = atomic_read(&port->chan_tx_irq_number); +#if 0 + if (test_and_clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap) + || (port->mode == G704 && port->aligned == NOT_ALIGNED)) { + res = -EIO; + goto out; + } +#endif + if (count == 0) + goto out; /* no need to wait */ + + if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count) + break; + + spin_unlock_irqrestore(&npe_lock, flags); + loops++; + if ((res = wait_event_interruptible + (port->chan_tx_waitq, + atomic_read (&port->chan_tx_irq_number) != prev_irq))) + goto out; + spin_lock_irqsave(&npe_lock, flags); + continue; + } + +#if 0 + if (loops > 1) + printk(KERN_DEBUG "ENTRY TX_first %u tx_count %u count %i" + " last_tx %u loops %i\n", chan_dev->tx_first, + chan_dev->tx_count, count, port->chan_last_tx, loops); +#endif + tx_buf = chan_tx_buf(port); + while (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count && + res < count) { + unsigned int tail, chan, frame; + + tail = (chan_dev->tx_first + chan_dev->tx_count) % + (CHAN_TX_FRAMES * chan_dev->chan_count); + chan = tail % chan_dev->chan_count; + frame = tail / chan_dev->chan_count; + chan = chan_dev->log_channels[chan]; + + if (get_user(tx_buf[chan * CHAN_TX_FRAMES + frame], buf++)) { + printk(KERN_DEBUG "BUG? TX %u %u %u\n", + tail, chan, frame); + res = -EFAULT; + goto out_sync; + } + chan_dev->tx_count++; + res++; + } +out_sync: + dma_sync_single(port->dev, port->chan_tx_buf_phys, + chan_tx_buf_len(port), DMA_TO_DEVICE); +out: +#if 0 + printk(KERN_DEBUG "EXIT TX_first %u tx_count %u res %i\n", + chan_dev->tx_first, chan_dev->tx_count, res); +#endif + spin_unlock_irqrestore(&npe_lock, flags); + return res; +} + + +static unsigned int hss_chan_poll(struct file *file, poll_table *wait) +{ + struct chan_device *chan_dev = inode_to_chan_dev + (file->f_path.dentry->d_inode); + struct port *port = chan_dev->port; + unsigned long flags; + unsigned int mask = 0; + + spin_lock_irqsave(&npe_lock, flags); + poll_wait(file, &port->chan_tx_waitq, wait); + poll_wait(file, &port->chan_rx_waitq, wait); + + if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count) + mask |= POLLOUT | POLLWRNORM; + if (chan_dev->rx_count) + mask |= POLLIN | POLLRDNORM; + spin_unlock_irqrestore(&npe_lock, flags); + return mask; +} + +/***************************************************************************** + * channelized device sysfs attributes + ****************************************************************************/ + +static ssize_t chan_show_chan(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct chan_device *chan_dev = dev_get_drvdata(dev); + + return print_channels(chan_dev->port, buf, chan_dev->id); +} + +static ssize_t chan_set_chan(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct chan_device *chan_dev = dev_get_drvdata(dev); + struct port *port = chan_dev->port; + unsigned long flags; + unsigned int ch; + size_t orig_len = len; + int err; + + if (len && buf[len - 1] == '\n') + len--; + + if (len != 7 || memcmp(buf, "destroy", 7)) + return -EINVAL; + + spin_lock_irqsave(&npe_lock, flags); + cdev_del(&chan_dev->cdev); + + for (ch = 0; ch < MAX_CHANNELS; ch++) + if (port->channels[ch] == chan_dev->id) + port->channels[ch] = CHANNEL_UNUSED; + port->chan_devices[chan_dev->id] = NULL; + kfree(chan_dev); + spin_unlock_irqrestore(&npe_lock, flags); + + if ((err = device_schedule_callback(dev, device_unregister))) + return err; + return orig_len; +} + +static struct device_attribute chan_attr = + __ATTR(channels, 0644, chan_show_chan, chan_set_chan); + +/***************************************************************************** + * main sysfs attributes + ****************************************************************************/ + +static const struct file_operations chan_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .read = hss_chan_read, + .write = hss_chan_write, + .poll = hss_chan_poll, + .open = hss_chan_open, + .release = hss_chan_release, +}; + +static ssize_t create_chan(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct port *port = dev_get_drvdata(dev); + struct chan_device *chan_dev; + u8 channels[MAX_CHANNELS]; + size_t orig_len = len; + unsigned long flags; + unsigned int ch, id; + int minor, err; + + if ((err = parse_channels(&buf, &len, channels)) < 1) + return err; + + if (!(chan_dev = kzalloc(sizeof(struct chan_device), GFP_KERNEL))) + return -ENOBUFS; + + spin_lock_irqsave(&npe_lock, flags); + + if (port->mode != MODE_RAW && port->mode != MODE_G704) { + err = -EINVAL; + goto free; + } + + for (ch = 0; ch < MAX_CHANNELS; ch++) + if (channels[ch] && port->channels[ch] != CHANNEL_UNUSED) { + printk(KERN_DEBUG "Channel #%i already in use\n", ch); + err = -EBUSY; + goto free; + } + + for (id = 0; id < MAX_CHAN_DEVICES; id++) + if (port->chan_devices[id] == NULL) + break; + + if (id == MAX_CHAN_DEVICES) { + err = -EBUSY; + goto free; + } + + for (ch = 0; ch < MAX_CHANNELS; ch++) + if (channels[ch]) + break; + + minor = port->id * MAX_CHAN_DEVICES + ch; + chan_dev->id = id; + chan_dev->port = port; + chan_dev->dev = device_create(hss_class, dev, MKDEV(chan_major, minor), + "hss%uch%u", port->id, ch); + if (IS_ERR(chan_dev->dev)) { + err = PTR_ERR(chan_dev->dev); + goto free; + } + + cdev_init(&chan_dev->cdev, &chan_fops); + chan_dev->cdev.owner = THIS_MODULE; + if ((err = cdev_add(&chan_dev->cdev, MKDEV(chan_major, minor), 1))) + goto destroy_device; + + for (ch = 0; ch < MAX_CHANNELS; ch++) + if (channels[ch]) + port->channels[ch] = id; + port->chan_devices[id] = chan_dev; + dev_set_drvdata(chan_dev->dev, chan_dev); + BUG_ON(device_create_file(chan_dev->dev, &chan_attr)); + + spin_unlock_irqrestore(&npe_lock, flags); + return orig_len; + +destroy_device: + device_unregister(chan_dev->dev); +free: + kfree(chan_dev); + spin_unlock_irqrestore(&npe_lock, flags); + return err; +} + +static ssize_t show_hdlc_chan(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return print_channels(dev_get_drvdata(dev), buf, CHANNEL_HDLC); +} + +static ssize_t set_hdlc_chan(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct port *port = dev_get_drvdata(dev); + u8 channels[MAX_CHANNELS]; + size_t orig_len = len; + unsigned long flags; + unsigned int ch; + int err; + + if ((err = parse_channels(&buf, &len, channels)) < 0) + return err; + + spin_lock_irqsave(&npe_lock, flags); + + if (port->mode != MODE_RAW && port->mode != MODE_G704) { + err = -EINVAL; + goto err; + } + + for (ch = 0; ch < MAX_CHANNELS; ch++) + if (channels[ch] && + port->channels[ch] != CHANNEL_UNUSED && + port->channels[ch] != CHANNEL_HDLC) { + printk(KERN_DEBUG "Channel #%i already in use\n", ch); + err = -EBUSY; + goto err; + } + + for (ch = 0; ch < MAX_CHANNELS; ch++) + if (channels[ch]) + port->channels[ch] = CHANNEL_HDLC; + else if (port->channels[ch] == CHANNEL_HDLC) + port->channels[ch] = CHANNEL_UNUSED; + + if (port->chan_open_count || port->hdlc_open) { + hss_config_set_lut(port); + hss_config_load(port); + } + + spin_unlock_irqrestore(&npe_lock, flags); + return orig_len; + +err: + spin_unlock_irqrestore(&npe_lock, flags); + return err; +} + +static ssize_t show_clock_type(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct port *port = dev_get_drvdata(dev); + + strcpy(buf, port->clock_type == CLOCK_INT ? "int\n" : "ext\n"); + return 5; +} + +static ssize_t set_clock_type(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct port *port = dev_get_drvdata(dev); + size_t orig_len = len; + unsigned long flags; + unsigned int clk, err; + + if (len && buf[len - 1] == '\n') + len--; + + if (len != 3) + return -EINVAL; + if (!memcmp(buf, "ext", 3)) + clk = CLOCK_EXT; + else if (!memcmp(buf, "int", 3)) + clk = CLOCK_INT; + else + return -EINVAL; + + spin_lock_irqsave(&npe_lock, flags); + if (port->plat->set_clock) + clk = port->plat->set_clock(port->id, clk); + if (clk != CLOCK_EXT && clk != CLOCK_INT) { + err = -EINVAL; /* plat->set_clock shouldn't change the state */ + goto err; + } + port->clock_type = clk; + if (port->chan_open_count || port->hdlc_open) { + hss_config_set_line(port); + hss_config_load(port); + } + spin_unlock_irqrestore(&npe_lock, flags); + + return orig_len; +err: + spin_unlock_irqrestore(&npe_lock, flags); + return err; +} + +static ssize_t show_clock_rate(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct port *port = dev_get_drvdata(dev); + + sprintf(buf, "%u\n", port->clock_rate); + return strlen(buf) + 1; +} + +static ssize_t set_clock_rate(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ +#if 0 + struct port *port = dev_get_drvdata(dev); + size_t orig_len = len; + unsigned long flags; + unsigned int rate; + + if (len && buf[len - 1] == '\n') + len--; + + if (get_number(&buf, &len, &rate, 1, 0xFFFFFFFFu)) + return -EINVAL; + if (len) + return -EINVAL; + + spin_lock_irqsave(&npe_lock, flags); + port->clock_rate = rate; + spin_unlock_irqrestore(&npe_lock, flags); + return orig_len; +#endif + return -EINVAL; /* FIXME not yet supported */ +} + +static ssize_t show_frame_size(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct port *port = dev_get_drvdata(dev); + + if (port->mode != MODE_RAW && port->mode != MODE_G704) + return -EINVAL; + + sprintf(buf, "%u\n", port->frame_size); + return strlen(buf) + 1; +} + +static ssize_t set_frame_size(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct port *port = dev_get_drvdata(dev); + size_t ret = len; + unsigned long flags; + unsigned int size; + + if (len && buf[len - 1] == '\n') + len--; + + if (get_number(&buf, &len, &size, MIN_FRAME_SIZE, MAX_FRAME_SIZE)) + return -EINVAL; + if (len || size % 8 > 1) + return -EINVAL; + + spin_lock_irqsave(&npe_lock, flags); + if (port->mode != MODE_RAW && port->mode != MODE_G704) + ret = -EINVAL; + else if (!port->chan_open_count && !port->hdlc_open) + ret = -EBUSY; + else { + port->frame_size = size; + port->frame_sync_offset = 0; + } + spin_unlock_irqrestore(&npe_lock, flags); + return ret; +} + +static ssize_t show_frame_offset(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct port *port = dev_get_drvdata(dev); + + sprintf(buf, "%u\n", port->frame_sync_offset); + return strlen(buf) + 1; +} + +static ssize_t set_frame_offset(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct port *port = dev_get_drvdata(dev); + size_t orig_len = len; + unsigned long flags; + unsigned int offset; + + if (len && buf[len - 1] == '\n') + len--; + + if (get_number(&buf, &len, &offset, 0, port->frame_size - 1)) + return -EINVAL; + if (len) + return -EINVAL; + + spin_lock_irqsave(&npe_lock, flags); + + port->frame_sync_offset = offset; + if (port->chan_open_count || port->hdlc_open) { + hss_config_set_rx_frame(port); + hss_config_load(port); + } + + spin_unlock_irqrestore(&npe_lock, flags); + return orig_len; +} + +static ssize_t show_loopback(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct port *port = dev_get_drvdata(dev); + + sprintf(buf, "%u\n", port->loopback); + return strlen(buf) + 1; +} + +static ssize_t set_loopback(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct port *port = dev_get_drvdata(dev); + size_t orig_len = len; + unsigned long flags; + unsigned int lb; + + if (len && buf[len - 1] == '\n') + len--; + + if (get_number(&buf, &len, &lb, 0, 1)) + return -EINVAL; + if (len) + return -EINVAL; + + spin_lock_irqsave(&npe_lock, flags); + + if (port->loopback != lb) { + port->loopback = lb; + if (port->chan_open_count || port->hdlc_open) { + hss_config_set_core(port); + hss_config_load(port); + } + if (port->loopback || port->carrier) + netif_carrier_on(port->netdev); + else + netif_carrier_off(port->netdev); + } + + spin_unlock_irqrestore(&npe_lock, flags); + return orig_len; +} + +static ssize_t show_mode(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct port *port = dev_get_drvdata(dev); + + switch(port->mode) { + case MODE_RAW: + strcpy(buf, "raw\n"); + break; + case MODE_G704: + strcpy(buf, "g704\n"); + break; + default: + strcpy(buf, "hdlc\n"); + break; + } + return strlen(buf) + 1; +} + +static ssize_t set_mode(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + struct port *port = dev_get_drvdata(dev); + size_t ret = len; + unsigned long flags; + + if (len && buf[len - 1] == '\n') + len--; + + spin_lock_irqsave(&npe_lock, flags); + + if (port->chan_open_count || port->hdlc_open) { + ret = -EBUSY; + } else if (len == 4 && !memcmp(buf, "hdlc", 4)) + port->mode = MODE_HDLC; + else if (len == 3 && !memcmp(buf, "raw", 3)) + port->mode = MODE_RAW; + else if (len == 4 && !memcmp(buf, "g704", 4)) + port->mode = MODE_G704; + else + ret = -EINVAL; + + spin_unlock_irqrestore(&npe_lock, flags); + return ret; +} + +static struct device_attribute hss_attrs[] = { + __ATTR(create_chan, 0200, NULL, create_chan), + __ATTR(hdlc_chan, 0644, show_hdlc_chan, set_hdlc_chan), + __ATTR(clock_type, 0644, show_clock_type, set_clock_type), + __ATTR(clock_rate, 0644, show_clock_rate, set_clock_rate), + __ATTR(frame_size, 0644, show_frame_size, set_frame_size), + __ATTR(frame_offset, 0644, show_frame_offset, set_frame_offset), + __ATTR(loopback, 0644, show_loopback, set_loopback), + __ATTR(mode, 0644, show_mode, set_mode), +}; + +/***************************************************************************** + * initialization + ****************************************************************************/ + +static int __devinit hss_init_one(struct platform_device *pdev) +{ + struct port *port; + struct net_device *dev; + hdlc_device *hdlc; + int i, err; + + if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL) + return -ENOMEM; + platform_set_drvdata(pdev, port); + port->id = pdev->id; + + if ((port->npe = npe_request(0)) == NULL) { + err = -ENOSYS; + goto err_free; + } + + port->dev = &pdev->dev; + port->plat = pdev->dev.platform_data; + if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) { + err = -ENOMEM; + goto err_plat; + } + + SET_NETDEV_DEV(dev, &pdev->dev); + hdlc = dev_to_hdlc(dev); + hdlc->attach = hss_hdlc_attach; + hdlc->xmit = hss_hdlc_xmit; + dev->open = hss_hdlc_open; + dev->stop = hss_hdlc_close; + dev->do_ioctl = hss_hdlc_ioctl; + dev->tx_queue_len = 100; + port->clock_type = CLOCK_EXT; + port->clock_rate = 2048000; + port->frame_size = 256; /* E1 */ + memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels)); + init_waitqueue_head(&port->chan_tx_waitq); + init_waitqueue_head(&port->chan_rx_waitq); + netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT); + + if ((err = register_hdlc_device(dev))) /* HDLC mode by default */ + goto err_free_netdev; + + for (i = 0; i < ARRAY_SIZE(hss_attrs); i++) + BUG_ON(device_create_file(port->dev, &hss_attrs[i])); + + printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id); + return 0; + +err_free_netdev: + free_netdev(dev); +err_plat: + npe_release(port->npe); + platform_set_drvdata(pdev, NULL); +err_free: + kfree(port); + return err; +} + +static int __devexit hss_remove_one(struct platform_device *pdev) +{ + struct port *port = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < ARRAY_SIZE(hss_attrs); i++) + device_remove_file(port->dev, &hss_attrs[i]); + + unregister_hdlc_device(port->netdev); + free_netdev(port->netdev); + npe_release(port->npe); + platform_set_drvdata(pdev, NULL); + kfree(port); + return 0; +} + +static struct platform_driver drv = { + .driver.name = DRV_NAME, + .probe = hss_init_one, + .remove = hss_remove_one, +}; + +static int __init hss_init_module(void) +{ + int err; + dev_t rdev; + + if ((ixp4xx_read_feature_bits() & + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) != + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) + return -ENOSYS; + + if ((err = alloc_chrdev_region(&rdev, 0, HSS_COUNT * MAX_CHAN_DEVICES, + "hss"))) + return err; + + spin_lock_init(&npe_lock); + + if (IS_ERR(hss_class = class_create(THIS_MODULE, "hss"))) { + printk(KERN_ERR "Can't register device class 'hss'\n"); + err = PTR_ERR(hss_class); + goto free_chrdev; + } + if ((err = platform_driver_register(&drv))) + goto destroy_class; + + chan_major = MAJOR(rdev); + return 0; + +destroy_class: + class_destroy(hss_class); +free_chrdev: + unregister_chrdev_region(MKDEV(chan_major, 0), + HSS_COUNT * MAX_CHAN_DEVICES); + return err; +} + +static void __exit hss_cleanup_module(void) +{ + platform_driver_unregister(&drv); + class_destroy(hss_class); + unregister_chrdev_region(MKDEV(chan_major, 0), + HSS_COUNT * MAX_CHAN_DEVICES); +} + +MODULE_AUTHOR("Krzysztof Halasa"); +MODULE_DESCRIPTION("Intel IXP4xx HSS driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:ixp4xx_hss"); +module_init(hss_init_module); +module_exit(hss_cleanup_module);