From 10ea7fd6b854c3ecf745d053beba10c7e00c33c9 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Sat, 9 Jul 2011 12:15:06 -0700 Subject: [PATCH 01/13] MIPS: BCM63XX: Add SMP support to prom.c This involves two changes to the BSP code: 1) register_smp_ops() for BMIPS SMP 2) The CPU1 boot vector on some of the BCM63xx platforms conflicts with the special interrupt vector (IV). Move it to 0x8000_0380 at boot time, to resolve the conflict. Signed-off-by: Kevin Cernekee [jogo@openwrt: move smp ops registration below #ifdef guard, don't enable smp for 6328/6358] Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/prom.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -8,7 +8,11 @@ #include #include +#include #include +#include +#include +#include #include #include #include @@ -52,6 +56,35 @@ void __init prom_init(void) /* do low level board init */ board_prom_init(); + +#if defined(CONFIG_CPU_BMIPS4350) && defined(CONFIG_SMP) + /* set up SMP */ + register_smp_ops(&bmips_smp_ops); + + /* + * BCM6328 does not have its second CPU enabled, while BCM6358 + * needs special handling for its shared TLB, so disable SMP for now. + */ + if (BCMCPU_IS_6328() || BCMCPU_IS_6358()) { + bmips_smp_enabled = 0; + return; + } + + /* + * The bootloader has set up the CPU1 reset vector at 0xa000_0200. + * This conflicts with the special interrupt vector (IV). + * The bootloader has also set up CPU1 to respond to the wrong + * IPI interrupt. + * Here we will start up CPU1 in the background and ask it to + * reconfigure itself then go back to sleep. + */ + memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); + __sync(); + set_c0_cause(C_SW0); + cpumask_set_cpu(1, &bmips_booted_mask); + + /* FIXME: we really should have some sort of hazard barrier here */ +#endif } void __init prom_free_prom_memory(void)