From 7b8e7bc9806b61be2f07bf2bbb5e3ee6e0f333e9 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sun, 21 Apr 2013 15:38:56 +0200 Subject: [PATCH 10/13] MIPS: BCM63XX: protect irq register accesses with a spinlock Since IRQs can be handled on both CPUs, we need to ensure that we don't try to modify the IRQ registers at the same time. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/irq.c | 47 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 5 deletions(-) --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,9 @@ static void __internal_irq_mask_64(unsig static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; +static DEFINE_SPINLOCK(ipic_lock); +static DEFINE_SPINLOCK(epic_lock); + #ifndef BCMCPU_RUNTIME_DETECT #ifdef CONFIG_BCM63XX_CPU_6328 #define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0) @@ -290,7 +294,9 @@ void __dispatch_internal_##width(int cpu static int i; \ u32 irq_stat_addr = get_irq_stat_addr(cpu); \ u32 irq_mask_addr = get_irq_mask_addr(cpu); \ + unsigned long flags; \ \ + spin_lock_irqsave(&ipic_lock, flags); \ /* read registers in reverse order */ \ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ u32 val; \ @@ -302,6 +308,7 @@ void __dispatch_internal_##width(int cpu if (val) \ irqs_pending = true; \ } \ + spin_unlock_irqrestore(&ipic_lock, flags); \ \ if (!irqs_pending) \ return; \ @@ -381,12 +388,20 @@ asmlinkage void plat_irq_dispatch(void) */ static void bcm63xx_internal_irq_mask(struct irq_data *d) { + unsigned long flags; + + spin_lock_irqsave(&ipic_lock, flags); internal_irq_mask(d->irq - IRQ_INTERNAL_BASE); + spin_unlock_irqrestore(&ipic_lock, flags); } static void bcm63xx_internal_irq_unmask(struct irq_data *d) { + unsigned long flags; + + spin_lock_irqsave(&ipic_lock, flags); internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE); + spin_unlock_irqrestore(&ipic_lock, flags); } /* @@ -397,8 +412,11 @@ static void bcm63xx_external_irq_mask(st { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); + + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) @@ -407,16 +425,24 @@ static void bcm63xx_external_irq_mask(st reg &= ~EXTIRQ_CFG_MASK(irq % 4); bcm_perf_writel(reg, regaddr); - if (is_ext_irq_cascaded) - internal_irq_mask(irq + ext_irq_start); + spin_unlock_irqrestore(&epic_lock, flags); + + if (is_ext_irq_cascaded) { + struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start); + + bcm63xx_internal_irq_mask(cd); + } } static void bcm63xx_external_irq_unmask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); + + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) @@ -425,16 +451,22 @@ static void bcm63xx_external_irq_unmask( reg |= EXTIRQ_CFG_MASK(irq % 4); bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); + + if (is_ext_irq_cascaded) { + struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start); - if (is_ext_irq_cascaded) - internal_irq_unmask(irq + ext_irq_start); + bcm63xx_internal_irq_unmask(cd); + } } static void bcm63xx_external_irq_clear(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; + spin_lock_irqsave(&epic_lock, flags); regaddr = get_ext_irq_perf_reg(irq); reg = bcm_perf_readl(regaddr); @@ -444,6 +476,7 @@ static void bcm63xx_external_irq_clear(s reg |= EXTIRQ_CFG_CLEAR(irq % 4); bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); } static int bcm63xx_external_irq_set_type(struct irq_data *d, @@ -452,6 +485,7 @@ static int bcm63xx_external_irq_set_type unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; int levelsense, sense, bothedge; + unsigned long flags; flow_type &= IRQ_TYPE_SENSE_MASK; @@ -486,9 +520,11 @@ static int bcm63xx_external_irq_set_type } regaddr = get_ext_irq_perf_reg(irq); - reg = bcm_perf_readl(regaddr); irq %= 4; + spin_lock_irqsave(&epic_lock, flags); + reg = bcm_perf_readl(regaddr); + switch (bcm63xx_get_cpu_id()) { case BCM6348_CPU_ID: if (levelsense) @@ -529,6 +565,7 @@ static int bcm63xx_external_irq_set_type } bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); irqd_set_trigger_type(d, flow_type); if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))