Index: linux-2.6.32.7/arch/mips/kernel/cevt-r4k.c =================================================================== --- linux-2.6.32.7.orig/arch/mips/kernel/cevt-r4k.c 2010-02-03 16:59:28.310430064 +0100 +++ linux-2.6.32.7/arch/mips/kernel/cevt-r4k.c 2010-02-03 16:59:54.578430015 +0100 @@ -16,6 +16,22 @@ #include /* + * Compare interrupt can be routed and latched outside the core, + * so a single execution hazard barrier may not be enough to give + * it time to clear as seen in the Cause register. 4 time the + * pipeline depth seems reasonably conservative, and empirically + * works better in configurations with high CPU/bus clock ratios. + */ + +#define compare_change_hazard() \ + do { \ + irq_disable_hazard(); \ + irq_disable_hazard(); \ + irq_disable_hazard(); \ + irq_disable_hazard(); \ + } while (0) + +/* * The SMTC Kernel for the 34K, 1004K, et. al. replaces several * of these routines with SMTC-specific variants. */ @@ -31,6 +47,7 @@ cnt = read_c0_count(); cnt += delta; write_c0_compare(cnt); + compare_change_hazard(); res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; return res; } @@ -100,22 +117,6 @@ return (read_c0_cause() >> cp0_compare_irq) & 0x100; } -/* - * Compare interrupt can be routed and latched outside the core, - * so a single execution hazard barrier may not be enough to give - * it time to clear as seen in the Cause register. 4 time the - * pipeline depth seems reasonably conservative, and empirically - * works better in configurations with high CPU/bus clock ratios. - */ - -#define compare_change_hazard() \ - do { \ - irq_disable_hazard(); \ - irq_disable_hazard(); \ - irq_disable_hazard(); \ - irq_disable_hazard(); \ - } while (0) - int c0_compare_int_usable(void) { unsigned int delta;