/*
 *  ADM5120 NAND interface definitions
 *
 *  This header file defines the hardware registers of the ADM5120 SoC
 *  built-in NAND interface.
 *
 *  Copyright (C) 2007 OpenWrt.org
 *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
 *
 *  NAND interface routines was based on a driver for Linux 2.6.19+ which
 *  was derived from the driver for Linux 2.4.xx published by Mikrotik for
 *  their RouterBoard 1xx and 5xx series boards.
 *    Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
 *    Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
 *    The original Mikrotik code seems not to have a license.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version 2
 *  of the License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the
 *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 *  Boston, MA  02110-1301, USA.
 *
 */

#ifndef _ADM5120_NAND_H_
#define _ADM5120_NAND_H_

#include <linux/types.h>
#include <linux/io.h>

#include <adm5120_defs.h>
#include <adm5120_switch.h>

/* NAND control registers */
#define NAND_REG_DATA		0x0 /* data register */
#define NAND_REG_SET_CEn	0x1 /* CE# low */
#define NAND_REG_CLR_CEn	0x2 /* CE# high */
#define NAND_REG_CLR_CLE	0x3 /* CLE low */
#define NAND_REG_SET_CLE	0x4 /* CLE high */
#define NAND_REG_CLR_ALE	0x5 /* ALE low */
#define NAND_REG_SET_ALE	0x6 /* ALE high */
#define NAND_REG_SET_SPn	0x7 /* SP# low (use spare area) */
#define NAND_REG_CLR_SPn	0x8 /* SP# high (do not use spare area) */
#define NAND_REG_SET_WPn	0x9 /* WP# low */
#define NAND_REG_CLR_WPn	0xA /* WP# high */
#define NAND_REG_STATUS		0xB /* Status register */

#define ADM5120_NAND_STATUS_READY	0x80

#define NAND_READ_REG(r) \
	readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))
#define NAND_WRITE_REG(r, v) \
	writeb((v),(void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r))

/*-------------------------------------------------------------------------*/

static inline void adm5120_nand_enable(void)
{
	SW_WRITE_REG(BW_CNTL1, BW_CNTL1_NAND_ENABLE);
	SW_WRITE_REG(BOOT_DONE, 1);
}

static inline void adm5120_nand_set_wpn(unsigned int set)
{
	NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1);
}

static inline void adm5120_nand_set_spn(unsigned int set)
{
	NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1);
}

static inline void adm5120_nand_set_cle(unsigned int set)
{
	NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1);
}

static inline void adm5120_nand_set_ale(unsigned int set)
{
	NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1);
}

static inline void adm5120_nand_set_cen(unsigned int set)
{
	NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1);
}

static inline u8 adm5120_nand_get_status(void)
{
	return NAND_READ_REG(NAND_REG_STATUS);
}

#endif /* _ADM5120_NAND_H_ */