From 83cccb37e9c5a36b06bf0ad05df0b61ba7e75f34 Mon Sep 17 00:00:00 2001
From: kaloz <kaloz@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Date: Thu, 4 Nov 2010 14:17:06 +0000
Subject: [toolchain]: add avr32 support to gcc 4.3.5

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23865 3c298f89-4303-0410-b956-a3cf2f4a3e73
---
 .../gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch  | 66 ++++++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch

(limited to 'toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch')

diff --git a/toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch b/toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch
new file mode 100644
index 000000000..b5d526c2a
--- /dev/null
+++ b/toolchain/gcc/patches/4.3.5/943-avr32_fix_f64_cmp.patch
@@ -0,0 +1,66 @@
+--- a/gcc/config/avr32/lib1funcs.S
++++ b/gcc/config/avr32/lib1funcs.S
+@@ -1389,25 +1389,30 @@ __avr32_f64_cmp_lt:
+ #endif  
+  
+         /* compare magnitude of op1 and op2 */
++        st.w    --sp, lr
++        st.w    --sp, r7
+         lsl     r11,1                   /* Remove sign bit of op1 */
+         srcs    r12                     /* Sign op1 to lsb of r12*/
+-	subfeq	r10, 0
+-	breq	3f			/* op1 zero */
+         lsl     r9,1                    /* Remove sign bit of op2 */
++        srcs    r7
+         rol     r12                     /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/
+ 	
+  
+         /* Check for Nan */
+-	pushm	lr
+-	mov_imm	lr, 0xffe00000
++        mov_imm lr, 0xffe00000
+         cp.w    r10,0
+         cpc     r11,lr
+         brhi    0f      /* We have NaN */
+         cp.w    r8,0
+         cpc     r9,lr
+         brhi    0f      /* We have NaN */
+-	popm	lr
+- 
++
++        cp.w    r11, 0
++        subfeq  r10, 0
++        breq    3f			/* op1 zero */
++        ld.w    r7, sp++
++        ld.w    lr, sp++
++
+         cp.w    r12,3                   /* both operands negative ?*/    
+         breq    1f
+  
+@@ -1453,18 +1458,22 @@ __avr32_f64_cmp_lt:
+ #endif
+ 
+ 0:      
++        ld.w    r7, sp++
+         popm    pc, r12=0
+ #endif
+  
+ 3:
+-        lsl     r9,1                   /* Remove sign bit of op1 */
++        cp.w    r7, 1          /* Check sign bit from r9 */
+ #ifdef L_avr32_f64_cmp_ge
+-        srcs    r12		       /* If op2 is negative then op1 >= op2. */	
++        sreq    r12		       /* If op2 is negative then op1 >= op2. */	
+ #endif
+ #ifdef L_avr32_f64_cmp_lt
+-        srcc    r12		       /* If op2 is positve then op1 <= op2. */
++        srne    r12		       /* If op2 is positve then op1 <= op2. */
+ #endif
+-	subfeq	r8, 0		       
++        cp.w    r9, 0
++        subfeq  r8, 0
++        ld.w    r7, sp++
++        ld.w    lr, sp++
+ #ifdef L_avr32_f64_cmp_ge
+ 	reteq	1		       /* Both operands are zero. Return true. */
+ #endif
-- 
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