From ea6e386f6f5bbad234c1ec138ba71e01b23ff77e Mon Sep 17 00:00:00 2001 From: blogic Date: Tue, 24 Jul 2012 20:37:50 +0000 Subject: [ramips] uart_clk on Rt3352F is always 40MHz Currently, sys_clk/10 is used which is just wrong. cpu_clk/10 would work for systems with 400MHz CPU clock. Signed-off-by: Daniel Golle git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32812 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/linux') diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c index 4a99cf39e..958547611 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c @@ -60,7 +60,7 @@ void __init rt305x_clocks_init(void) break; } rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; - rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10; + rt305x_uart_clk.rate = 40000000; rt305x_wdt_clk.rate = rt305x_sys_clk.rate; } else { BUG(); -- cgit v1.2.3