From e6d87036412b952cb083eff2dc716aee97a771f2 Mon Sep 17 00:00:00 2001
From: Roman Yeryomin <roman@advem.lv>
Date: Fri, 17 May 2013 20:40:24 +0300
Subject: Move to rsdk 3.2.4. Compiles cleanly.

Signed-off-by: Roman Yeryomin <roman@advem.lv>
---
 .../wireless/rtl8192e/data_88e/AGC_TAB_1T_88E.txt  | 131 ++++++++++++
 .../net/wireless/rtl8192e/data_88e/MAC_REG_88E.txt |  92 ++++++++
 .../wireless/rtl8192e/data_88e/MAC_REG_88E_TC.txt  |  94 +++++++++
 .../wireless/rtl8192e/data_88e/PHY_REG_1T_88E.txt  | 225 ++++++++++++++++++++
 .../rtl8192e/data_88e/PHY_REG_1T_88E_TC.txt        | 231 +++++++++++++++++++++
 .../wireless/rtl8192e/data_88e/PHY_REG_MP_88E.txt  |   4 +
 .../wireless/rtl8192e/data_88e/PHY_REG_PG_88E.txt  | 144 +++++++++++++
 .../wireless/rtl8192e/data_88e/radio_a_1T_88E.txt  | 153 ++++++++++++++
 .../rtl8192e/data_88e/radio_a_1T_88E_TC.txt        | 132 ++++++++++++
 9 files changed, 1206 insertions(+)
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/AGC_TAB_1T_88E.txt
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/MAC_REG_88E.txt
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/MAC_REG_88E_TC.txt
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_1T_88E.txt
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_1T_88E_TC.txt
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_MP_88E.txt
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_PG_88E.txt
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/radio_a_1T_88E.txt
 create mode 100644 target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/radio_a_1T_88E_TC.txt

(limited to 'target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e')

diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/AGC_TAB_1T_88E.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/AGC_TAB_1T_88E.txt
new file mode 100644
index 000000000..93d138eb5
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/AGC_TAB_1T_88E.txt
@@ -0,0 +1,131 @@
+// AGC_TABLE 1
+0xc78	0xfb000001  //-110  //03  fb
+0xc78	0xfb010001          //04  fb
+0xc78	0xfb020001          //05  fb
+0xc78	0xfb030001          //06  fb          
+0xc78	0xfb040001          //07  fb
+0xc78	0xfb050001  //-100  //08  fb
+0xc78	0xfa060001          //09  fb
+0xc78	0xf9070001          //0A  fa
+0xc78	0xf8080001          //0B  f9
+0xc78	0xf7090001          //0C  f8
+0xc78	0xf60A0001  //-90   //0D  f7
+0xc78	0xf50B0001          //0E  f6
+0xc78	0xf40C0001          //0F  f5
+0xc78	0xf30D0001          //10  f4
+0xc78	0xf20E0001          //11  f3
+0xc78	0xf10F0001  //-80   //12  f2              
+0xc78	0xf0100001          //13  f1              
+0xc78	0xef110001          //14  f0              
+0xc78	0xee120001          //15  ef              
+0xc78	0xed130001          //16  ee  14            
+0xc78	0xec140001  //-70   //17  ed         12          
+0xc78	0xeb150001          //18  ec         13     
+0xc78	0xea160001          //19  eb         14     
+0xc78	0xe9170001          //1A  ea         15
+0xc78	0xe8180001          //1B  e9         16
+0xc78	0xe7190001  //-60   //1C  e8  1A     17
+0xc78	0xe61A0001          //1D  e7
+0xc78	0xe51B0001          //1E  e6
+0xc78	0xe41C0001          //1F  e5
+0xc78	0xe31D0001          //20  e4
+0xc78	0xe21E0001  //-50   //21  e3  1F
+0xc78	0xe11F0001          //22  e2
+0xc78	0x8a200001          //23  e1
+0xc78	0x89210001          //24  e0      
+0xc78	0x88220001          //25  88      8a
+0xc78	0x87230001  //-40   //88  87  24  89
+0xc78	0x86240001          //87  86  25  88
+0xc78	0x85250001          //86  85  26  87        
+0xc78	0x84260001          //85  84      86
+0xc78	0x83270001          //84  83        
+0xc78	0x82280001  //-30   //2A  82                
+0xc78	0x6b290001          //2B  6a        
+0xc78	0x6a2A0001          //2C  69        
+0xc78	0x692B0001          //2D  68
+0xc78	0x682C0001          //2E  67
+0xc78	0x672D0001  //-20   //2F  66
+0xc78	0x662E0001          //30  65
+0xc78	0x652F0001          //31  64
+0xc78	0x64300001          //32  4a
+0xc78	0x63310001          //3   49
+0xc78	0x62320001  //-10   //34  48
+0xc78	0x61330001	    //35  47
+0xc78	0x46340001          //36  46
+0xc78	0x45350001	    //37  45
+0xc78	0x44360001	    //38  44
+0xc78	0x43370001  //0     //39  43
+0xc78	0x42380001          //44  42
+0xc78	0x41390001          //43  41
+0xc78	0x403A0001          //42  40
+0xc78	0x403B0001          //41  40
+0xc78	0x403C0001  //10    //40  40
+0xc78	0x403D0001          //40  40
+0xc78	0x403E0001          //40  40
+0xc78	0x403F0001  //16    //40  40
+// AGC_TAB40 2
+0xc78	0xfb400001 //-110  
+0xc78	0xfb410001        
+0xc78	0xfb420001        
+0xc78	0xfb430001        
+0xc78	0xfb440001        
+0xc78	0xfb450001 //-100  
+0xc78	0xfb460001        
+0xc78	0xfb470001        
+0xc78	0xfb480001        
+0xc78	0xfa490001        
+0xc78	0xf94a0001 //-90   
+0xc78	0xf84b0001        
+0xc78	0xf74c0001        
+0xc78	0xf64d0001        
+0xc78	0xf54e0001        
+0xc78	0xf44f0001 //-80   
+0xc78	0xf3500001        
+0xc78	0xf2510001        
+0xc78	0xf1520001        
+0xc78	0xf0530001        
+0xc78	0xef540001 //-70  
+0xc78	0xee550001        
+0xc78	0xed560001        
+0xc78	0xec570001        
+0xc78	0xeb580001        
+0xc78	0xea590001 //-60  
+0xc78	0xe95a0001        
+0xc78	0xe85b0001        
+0xc78	0xe75c0001        
+0xc78	0xe65d0001        
+0xc78	0xe55e0001 //-50   
+0xc78	0xe45f0001        
+0xc78	0xe3600001        
+0xc78	0xe2610001        
+0xc78	0xc3620001        
+0xc78	0xc2630001 //-40   
+0xc78	0xc1640001        
+0xc78	0x8b650001        
+0xc78	0x8a660001        
+0xc78	0x89670001        
+0xc78	0x88680001 //-30   //a5
+0xc78	0x87690001        
+0xc78	0x866a0001        
+0xc78	0x856b0001        
+0xc78	0x846c0001        
+0xc78	0x676d0001 //-20   
+0xc78	0x666e0001        
+0xc78	0x656f0001        
+0xc78	0x64700001        //64
+0xc78	0x63710001        //63
+0xc78	0x62720001 //-10   //62
+0xc78	0x61730001          //61
+0xc78	0x60740001         //60
+0xc78	0x46750001        
+0xc78	0x45760001        
+0xc78	0x44770001 //0     
+0xc78	0x43780001        
+0xc78	0x42790001        
+0xc78	0x417a0001        
+0xc78	0x407b0001        
+0xc78	0x407c0001 //10    
+0xc78	0x407d0001        
+0xc78	0x407e0001        
+0xc78	0x407f0001 //16
+0xffff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/MAC_REG_88E.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/MAC_REG_88E.txt
new file mode 100644
index 000000000..5b2e2d72a
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/MAC_REG_88E.txt
@@ -0,0 +1,92 @@
+//Release version: RTL8188E_MP.1.0221.2012
+0x026	0x41
+0x027 	0x35
+0x428	0x0a
+0x429	0x10
+0x430   0x00
+0x431   0x01
+0x432   0x02
+0x433	0x04
+0x434	0x05
+0x435	0x06
+0x436	0x07
+0x437	0x08
+0x438	0x00
+0x439	0x00
+0x43a	0x01
+0x43b	0x02
+0x43c	0x04
+0x43d	0x05
+0x43e	0x06
+0x43f	0x07
+0x440	0x5d
+0x441	0x01
+0x442	0x00
+0x444	0x15
+0x445	0xf0
+0x446	0x0f
+0x447	0x00
+0x458	0x41
+0x459	0xa8
+0x45a	0x72
+0x45b	0xb9
+0x460	0x66
+0x461	0x66
+0x480	0x08
+0x4c8	0xff
+0x4c9	0x08
+0x4cc	0xff
+0x4cd	0xff
+0x4ce	0x01
+0x4d3	0x01
+0x500	0x26
+0x501	0xa2
+0x502	0x2f
+0x503	0x00
+0x504	0x28
+0x505	0xa3
+0x506	0x5e
+0x507	0x00
+0x508	0x2b
+0x509	0xa4
+0x50a	0x5e
+0x50b	0x00
+0x50c	0x4f
+0x50d	0xa4
+0x50e	0x00
+0x50f	0x00
+0x512	0x1c
+0x514	0x0a
+0x516	0x0a
+0x525	0x4f
+0x550	0x10
+0x551	0x10
+0x559	0x02
+0x55d	0xff
+0x605	0x30
+0x608	0x0e
+0x609	0x2a
+0x620	0xff
+0x621	0xff
+0x622	0xff
+0x623	0xff
+0x624	0xff
+0x625	0xff
+0x626	0xff
+0x627	0xff
+0x652	0x20
+0x63c	0x08
+0x63d	0x08
+0x63e	0x0c
+0x63f	0x0c
+0x640	0x40
+0x66e	0x05
+0x700	0x21
+0x701	0x43
+0x702	0x65
+0x703	0x87
+0x708	0x21
+0x709	0x43
+0x70a	0x65
+0x70b	0x87
+0xffff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/MAC_REG_88E_TC.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/MAC_REG_88E_TC.txt
new file mode 100644
index 000000000..eea2e555e
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/MAC_REG_88E_TC.txt
@@ -0,0 +1,94 @@
+//Release version: RTL8188E.2.0104.2012
+0x024 	0x21
+0x025 	0x04
+0x026 	0x41
+0x027 	0x37
+0x428	0x0a
+0x429	0x10
+0x430   0x00
+0x431   0x01
+0x432   0x02
+0x433	0x04
+0x434	0x05
+0x435	0x06
+0x436	0x07
+0x437	0x08
+0x438	0x00
+0x439	0x00
+0x43a	0x01
+0x43b	0x02
+0x43c	0x04
+0x43d	0x05
+0x43e	0x06
+0x43f	0x07
+0x440	0x5d
+0x441	0x01
+0x442	0x00
+0x444	0x15
+0x445	0xf0
+0x446	0x0f
+0x447	0x00
+0x458	0x41
+0x459	0xa8
+0x45a	0x72
+0x45b	0xb9
+0x460	0x66
+0x461	0x66
+0x480	0x08
+0x4c8	0xff
+0x4c9	0x08
+0x4cc	0xff
+0x4cd	0xff
+0x4ce	0x01
+0x4d3	0x01
+0x500	0x26
+0x501	0xa2
+0x502	0x2f
+0x503	0x00
+0x504	0x28
+0x505	0xa3
+0x506	0x5e
+0x507	0x00
+0x508	0x2b
+0x509	0xa4
+0x50a	0x5e
+0x50b	0x00
+0x50c	0x4f
+0x50d	0xa4
+0x50e	0x00
+0x50f	0x00
+0x512	0x1c
+0x514	0x0a
+0x516	0x0a
+0x525	0x4f
+0x550	0x10
+0x551	0x10
+0x559	0x02
+0x55d	0xff
+0x605	0x30
+0x608	0x0e
+0x609	0x2a
+0x620	0xff
+0x621	0xff
+0x622	0xff
+0x623	0xff
+0x624	0xff
+0x625	0xff
+0x626	0xff
+0x627	0xff
+0x652	0x20
+0x63c	0x0a
+0x63d	0x0e
+0x63e	0x0a
+0x63f	0x0e
+0x640	0x40
+0x66e	0x05
+0x700	0x21
+0x701	0x43
+0x702	0x65
+0x703	0x87
+0x708	0x21
+0x709	0x43
+0x70a	0x65
+0x70b	0x87
+0xffff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_1T_88E.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_1T_88E.txt
new file mode 100644
index 000000000..e27e5e368
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_1T_88E.txt
@@ -0,0 +1,225 @@
+////Release version: RTL8188E.009.0105.2012
+//=======================
+// PAGE_8 ( FPGA_PHY0 )
+//=======================
+0x800 0x80040000
+0x804 0x00000003
+0x808 0x0000fc00
+0x80c 0x0000000A
+0x810 0x10001331
+0x814 0x020c3d10
+0x818 0x02200385	// [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385
+0x81c 0x00000000
+0x820 0x01000100	// 0x01000000 (SI); 0x01000100 (PI)
+0x824 0x00390204	//88E: 0x824[9]=1'b1 
+0x828 0x00000000
+0x82c 0x00000000 
+0x830 0x00000000
+0x834 0x00000000
+0x838 0x00000000
+0x83c 0x00000000
+0x840 0x00010000	//RF to standby mode
+0x844 0x00000000
+0x848 0x00000000
+0x84c 0x00000000
+0x850 0x00000000	// RF wakeup, TBD    
+0x854 0x00000000	// RF sleep, TBD
+0x858 0x569a11a9	//88E:R130 0x858[15:0]=16h11a9					//0x569a569a 
+0x85c 0x01000014	// AFE ctrl reg (ASIC)  RX AD3 CCA mode
+0x860 0x66f60110	//88E:R133 0x860[14:12]=3'd0					//8723E default WiFi for 1 anatenna solution
+0x864 0x061f0649	//88E:R130 0x864[15:0]=16'h0641					//0x061f0130 
+0x868 0x00000000
+0x86c 0x27272700	//0x32323200	//Path-A 11M/5.5M/2M TX AGC codeword
+0x870 0x07000760	// z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA)
+0x874 0x25004000	// 0x874[27:24]=4'b0101 ADC Gain x 1	//0x22004000
+0x878 0x00000808	//88E:R130+R132 0x878[15:0]=16'h0808,0x878[31:16]=16'h0000 	// RF mode for standby & rx_low_power codeword
+0x87c 0x00000000 	// TST mode
+0x880 0xb0000c1c	// AFE ctrl reg (ASIC), 0x880[17]=1'b0 
+0x884 0x00000001	// AFE ctrl reg (ASIC), 0x884[2:1]=0 
+0x888 0x00000000	// AFE ctrl reg (ASIC) 
+0x88c 0xccc000c0	// [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND
+0x890 0x00000800
+0x894 0xfffffffe 
+0x898 0x40302010 
+0x89c 0x00706050 
+//
+//=======================
+// PAGE_9 ( FPGA_PHY1 )
+//=======================
+0x900 0x00000000
+0x904 0x00000023 
+0x908 0x00000000  
+0x90c 0x81121111	// tx antenna by contorl register
+0x910 0x00000002	// 88E:RX_Status, Reg910[15:0]=16'd2
+0x914 0x00000201	// 88E:Antenna Diversity, 0x914[7:0]=0, 0x914[15:8]=1
+//
+//=======================
+// PAGE_A ( CCK_PHY0 )
+//=======================
+0xa00 0x00d047c8
+0xa04 0x80ff000c
+0xa08 0x8c838300	// MP: 0x88838300, driver: 0x8ccd8300
+0xa0c 0x2e7f120f
+0xa10 0x9500bb78 
+0xa14 0x1114D028
+0xa18 0x00881117
+0xa1c 0x89140f00
+0xa20 0x1a1b0000 
+0xa24 0x090e1317 
+0xa28 0x00000204
+0xa2c 0x00d30000
+0xa70 0x101fbf00
+0xa74 0x00000007	//88E:R124+R127 RegA76=0x00,RegA77=0x00
+0xa78 0x00000900	//88E:R124+R127 RegA78=0x00,RegA79=0x09
+0xa7c 0x225b0606	//88E:R134 RegA7C=0x06,RegA7D=0x06,RegA7E=0xc0,RegA7F=0x22
+0xa80 0x218075b1	//88E: CCK LNA 2 to 3 bit mapping, 0xa80[23]=1'b1. 0xa80[7]=1'b1, CCK agc_rpt as new format
+//0xa80 0x21003210	//88E:R134 RegA80=0x10,RegA81=0x32,RegA82=0x00,RegA83=0x21
+
+//
+//=======================
+// PAGE_B
+//=======================
+0xb2c 0x80000000	//default LNA
+//
+//=======================
+// PAGE_C ( OFDM_PHY0 )
+//=======================
+0xc00 0x48071d40 
+0xc04 0x03a05611  
+0xc08 0x000000e4	// [8:4] is about DBG_GPIO selection 
+0xc0c 0x6c6c6c6c 
+0xc10 0x08800000 
+0xc14 0x40000100
+0xc18 0x08800000
+0xc1c 0x40000100
+0xc20 0x00000000	// DTR TH
+0xc24 0x00000000	// DTR TH
+0xc28 0x00000000	// DTR TH
+0xc2c 0x00000000	// DTR TH
+0xc30 0x69e9ac47	// PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44
+0xc34 0x469652af   
+0xc38 0x49795994   
+0xc3c 0x0a97971c  
+0xc40 0x1f7c403f	//88E:R122							//0x1f7c403f  
+0xc44 0x000100b7  
+0xc48 0xec020107	//[1]=1:enable L1_SBD 
+0xc4c 0x007f037f	// turn off edcca 
+0xc50 0x69553420	//88E:R122							//0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 
+0xc54 0x43bc0094 
+0xc58 0x00013169     	// simple agc settling time    //0x00000967	//88E:R122							//0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420   
+0xc5c 0x00250492	// switch RXHP corner	//0x00681492	//88E:R122+mantis2467 0xc5c[20:18]=3'd1, 0xc5c[23:21]=3'd1, 0xc5c[26:24]=3'd0	//0x433c0094
+0xc60 0x00000000	// DTR TH
+0xc64 0x7112848b	//L1-SBD  //31168a8b for 6M sen. 0x5116828b, 0x5116848b //by Gary
+0xc68 0x47c00bff	//L1-SBD
+0xc6c 0x00000036	//88E:R129 0xc6c[8:7]=0						//L1-SBD
+0xc70 0x2c7f000d	// disable AGC flow-1 
+0xc74 0x020610db   	// 1st and 2nd BB PW time = 400ns   //0x038610db
+0xc78 0x0000001f
+0xc7c 0x00b91612  
+0xc80 0x390000e4 	//-1dB  
+0xc84 0x20f60000 
+0xc88 0x40000100 
+0xc8c 0x20200000 
+0xc90 0x00091521	// TX Power Training for path-A	
+0xc94 0x00000000 	
+0xc98 0x00121820	// TX Power Training for path-B
+0xc9c 0x00007f7f	// turn off pre-cca
+0xca0 0x00000000 
+0xca4 0x000300A0	//88E: 0xca4[10:0]=0xa0, 0xca4[22:12]=0x30						//0x00000080 // reserved
+0xca8 0x00000000	// reserved
+0xcac 0x00000000	// reserved
+0xcb0 0x00000000	// reserved
+0xcb4 0x00000000	// reserved
+0xcb8 0x00000000	// reserved
+0xcbc 0x28000000
+0xcc0 0x00000000	// reserved
+0xcc4 0x00000000	// reserved
+0xcc8 0x00000000	// reserved
+0xccc 0x00000000	// reserved
+0xcd0 0x00000000	// reserved
+0xcd4 0x00000000	// reserved
+0xcd8 0x64b22427	// reserved
+0xcdc 0x00766932	// reserved
+0xce0 0x00222222  
+0xce4 0x00000000
+0xce8 0x37644302
+0xcec 0x2f97d40c
+//
+//=======================
+// PAGE_D ( OFDM_PHY1 )
+//=======================
+0xd00 0x00000740	//88E: support<mcs8						//0x00080740	
+0xd04 0x00020401  
+0xd08 0x0000907f  
+0xd0c 0x20010201 
+0xd10 0xa0633333  
+0xd14 0x3333bc43  
+0xd18 0x7a8f5b6f	//88E: R128 0xd18[2]=0
+0xd2c 0xcc979975  
+0xd30 0x00000000
+0xd34 0x80608000
+0xd38 0x00000000
+0xd3c 0x00127353	//0xd3c[8:6]=3'b101 	0x00027293//88E: R128 0xd3c[24:20]=0
+0xd40 0x00000000
+0xd44 0x00000000
+0xd48 0x00000000
+0xd4c 0x00000000
+0xd50 0x6437140a 
+0xd54 0x00000000 
+0xd58 0x00000282	//88E: R128 0xd58[11:0]=0, 0xd58[23:16]=0
+0xd5c 0x30032064 
+0xd60 0x4653de68
+0xd64 0x04518a3c	//[26]=1:enable L1-SBD//
+0xd68 0x00002101
+0xd6c 0x2a201c16	// DTR
+0xd70 0x1812362e	// DTR
+0xd74 0x322c2220	// DTR
+0xd78 0x000e3c24	// DTR
+//=======================
+// PAGE_E
+//=======================
+0xe00 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, 6M, 9M, 12M, 18M 
+0xe04 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, 24M, 36M, 48M, 54M 
+0xe08 0x0390272d	//0x03902a2a	// Path-A TX AGC codewod, MCS32, 1M 
+0xe10 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 
+0xe14 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 
+0xe18 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 
+0xe1c 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 
+0xe28 0x00000000        
+0xe30 0x1000dc1f	// 0xe30~0xe60: IQK
+0xe34 0x10008c1f
+0xe38 0x02140102
+0xe3C 0x681604c2
+0xe40 0x01007c00
+0xe44 0x01004800
+0xe48 0xfb000000
+0xe4c 0x000028d1
+0xe50 0x1000dc1f
+0xe54 0x10008c1f
+0xe58 0x02140102
+0xe5C 0x28160d05
+0xe60 0x00000008
+//0xe64 0x281600a0	// Reserved in 92C/88C
+0xe68 0x001b25a4
+0xe6c 0x00c00014	// AFE ctrl reg (ASIC)  Blue-Tooth   
+0xe70 0x00c00014	// AFE ctrl reg (ASIC)  RX_WAIT_CCA 
+0xe74 0x01000014	// AFE ctrl reg (ASIC)  TX_CCK_RFON
+0xe78 0x01000014	// AFE ctrl reg (ASIC)  TX_CCK_BBON
+0xe7c 0x01000014	// AFE ctrl reg (ASIC)  TX_OFDM_RFON
+0xe80 0x01000014	// AFE ctrl reg (ASIC)  TX_OFDM_BBON
+0xe84 0x00c00014	// AFE ctrl reg (ASIC)  TX_TO_RX
+0xe88 0x01000014	// AFE ctrl reg (ASIC)  TX_TO_TX 
+0xe8c 0x00c00014	// AFE ctrl reg (ASIC)  RX_CCK 
+0xed0 0x00c00014	// AFE ctrl reg (ASIC)  RX_OFDM 
+0xed4 0x00c00014	// AFE ctrl reg (ASIC)  RX_WAIT_RIFS 
+0xed8 0x00c00014	// AFE ctrl reg (ASIC)  RX_TO_RX
+0xedc 0x00000014	// AFE ctrl reg (ASIC)  Standby 
+0xee0 0x00000014	// AFE ctrl reg (ASIC)  Sleep
+0xeec 0x01c00014	// AFE ctrl reg (ASIC)  PMPD_ANAEN 
+//=======================	
+// PAGE_F              	
+//=======================
+0xf14 0x00000003	// debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG
+0xf4c 0x00000000	// Only for FPGA PMAC
+0xf00 0x00000300	// enable BBRSTB, bcz HSSI use clk_bb
+0xffff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_1T_88E_TC.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_1T_88E_TC.txt
new file mode 100644
index 000000000..d5350b20c
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_1T_88E_TC.txt
@@ -0,0 +1,231 @@
+//Release version: RTL8188E.009.0105.2012
+//20111125
+//0x24 0x37410421		//0x24[27]=1'b0
+//20111004 Alex
+//0x24 038180f1		//reducing 80M spur
+//0x28 0xf2ffff83	//reducing 80M spur
+//0x28 0xf2ffff82	//reducing 80M spur
+//0x28 0xf2ffff83	//reducing 80M spur
+//0x40 0x00000004	//BT LO Leakage
+//0x66 0x00040000	//110315
+//=======================
+// PAGE_8 ( FPGA_PHY0 )
+//=======================
+0x800 0x80040000 
+0x804 0x00000003
+0x808 0x0000fc00 
+0x80c 0x0000000A  
+0x810 0x10005388
+0x814 0x020c3d10 
+0x818 0x0220038e	// [30:29] is DTR, Set off now. turn off RIFS: 0x00200185, turn on RIFS: 0x00200385
+0x81c 0x00000000 
+0x820 0x01000100	// 0x01000000 (SI), 0x01000100 (PI) 
+0x824 0x00390004	//88E: 0x824[9]=1'b0 
+0x828 0x00000000
+0x82c 0x00000000 
+0x830 0x00000000
+0x834 0x00000000
+0x838 0x00000000
+0x83c 0x00000000
+0x840 0x00010000	//RF to standby mode
+0x844 0x00000000   
+0x848 0x00000000
+0x84c 0x00000000
+0x850 0x00000000	// RF wakeup, TBD    
+0x854 0x00000000	// RF sleep, TBD
+0x858 0x569a11a9	//88E:R130 0x858[15:0]=16h11a9					//0x569a569a 
+0x85c 0x01000014	// AFE ctrl reg (ASIC)  RX AD3 CCA mode
+0x860 0x66f60110	//88E:R133 0x860[14:12]=3'd0					//8723E default WiFi for 1 anatenna solution
+0x864 0x061f0641	//88E:R130 0x864[15:0]=16'h0641					//0x061f0130 
+0x868 0x00000000
+0x86c 0x27272700	//0x32323200	//Path-A 11M/5.5M/2M TX AGC codeword
+0x870 0x07000760	// z2: 0x03000300, 92C RF: 0x07000700 (2 internal PA), 92S RF: 0x03000700 (one internal PA)
+0x874 0x25004000	// 0x874[27:24]=4'b0101 ADC Gain x 1	//0x22004000
+0x878 0x00000808	//88E:R130+R132 0x878[15:0]=16'h0808,0x878[31:16]=16'h0000 	// RF mode for standby & rx_low_power codeword
+0x87c 0x00000000 	// TST mode
+0x880 0xb0000c1c	// AFE ctrl reg (ASIC), 0x880[17]=1'b0 
+0x884 0x00000001	// AFE ctrl reg (ASIC), 0x884[2:1]=0 
+0x888 0x00000000	// AFE ctrl reg (ASIC) 
+0x88c 0xccc000c0	// [10:1] is r_rdy_cnt for sleep/standby mode, [27],[31] are MCS_IND
+0x890 0x00000800
+0x894 0xfffffffe 
+0x898 0x40302010 
+0x89c 0x00706050 
+//
+//=======================
+// PAGE_9 ( FPGA_PHY1 )
+//=======================
+0x900 0x00000000
+0x904 0x00000023 
+0x908 0x00000000  
+0x90c 0x81121111	// tx antenna by contorl register
+0x910 0x00000002	// 88E:RX_Status, Reg910[15:0]=16'd2
+0x914 0x00000100	// 88E:Antenna Diversity, 0x914[7:0]=0, 0x914[15:8]=1
+//
+//=======================
+// PAGE_A ( CCK_PHY0 )
+//=======================
+0xa00 0x00d047c8
+0xa04 0x80ff000c
+0xa08 0x8c838300	// MP: 0x88838300, driver: 0x8ccd8300
+0xa0c 0x2e7f120f
+0xa10 0x9500bb78 
+0xa14 0x1114D028
+0xa18 0x00881117
+0xa1c 0x89140f00
+0xa20 0x1a1b0000 
+0xa24 0x090e1317 
+0xa28 0x00000204
+0xa2c 0x00d30000
+0xa70 0x101fbf00
+0xa74 0x00000007	//88E:R124+R127 RegA76=0x00,RegA77=0x00
+0xa78 0x00000900	//88E:R124+R127 RegA78=0x00,RegA79=0x09
+0xa7c 0x22c00606	//88E:R134 RegA7C=0x06,RegA7D=0x06,RegA7E=0xc0,RegA7F=0x22
+0xa80 0x21807631	//88E: CCK LNA 2 to 3 bit mapping, 0xa80[23]=1'b1. 0xa80[7]=1'b0, CCK agc_rpt as old format
+//0xa80 0x21003210	//88E:R134 RegA80=0x10,RegA81=0x32,RegA82=0x00,RegA83=0x21
+//
+//=======================
+// PAGE_B
+//=======================
+0xb2c 0x80000000	//default LNA
+//
+//=======================
+// PAGE_C ( OFDM_PHY0 )
+//=======================
+0xc00 0x48071d40 
+0xc04 0x03a05611  
+0xc08 0x000000e4	// [8:4] is about DBG_GPIO selection 
+0xc0c 0x6c6c6c6c 
+0xc10 0x08800000 
+0xc14 0x40000100
+0xc18 0x08800000
+0xc1c 0x40000100
+0xc20 0x00000000	// DTR TH
+0xc24 0x00000000	// DTR TH
+0xc28 0x00000000	// DTR TH
+0xc2c 0x00000000	// DTR TH
+0xc30 0x69e9ac44	// PWED_TH option2=0x69e9bb44, 0x69e9ab44, 0x69e9ac44
+0xc34 0x469652af   
+0xc38 0x49795994   
+0xc3c 0x0a97971c  
+0xc40 0x1f7c403f	//88E:R122							//0x1f7c403f  
+0xc44 0x000100b7  
+0xc48 0xec020107	//[1]=1:enable L1_SBD 
+0xc4c 0x007f037f	// turn off edcca 
+0xc50 0x69553420	//88E:R122							//0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420 
+0xc54 0x43bc0094 
+0xc58 0x00003169     	// simple agc settling time    //0x00000967	//88E:R122							//0x69543420 // AAGC=1,0x68043420, AAGC=2,0x69543420   
+0xc5c 0x00250492	// switch RXHP corner	//0x00681492	//88E:R122+mantis2467 0xc5c[20:18]=3'd1, 0xc5c[23:21]=3'd1, 0xc5c[26:24]=3'd0	//0x433c0094
+0xc60 0x00000000	// DTR TH
+0xc64 0x7112848b	//L1-SBD  //31168a8b for 6M sen. 0x5116828b, 0x5116848b //by Gary
+0xc68 0x47c00bff	//L1-SBD
+0xc6c 0x00000036	//88E:R129 0xc6c[8:7]=0						//L1-SBD
+0xc70 0x2c7f000d	// disable AGC flow-1 
+0xc74 0x020610db   	// 1st and 2nd BB PW time = 400ns   //0x038610db
+0xc78 0x0000001f
+0xc7c 0x00b91612  
+0xc80 0x40000100	//0x1b00006c	//BB Swing reduce to -7.5dB 
+0xc84 0x20f60000 
+0xc88 0x40000100 
+0xc8c 0x20200000 
+0xc90 0x00121820	// TX Power Training for path-A	
+0xc94 0x00000000 	
+0xc98 0x00121820	// TX Power Training for path-B
+0xc9c 0x00007f7f	// turn off pre-cca
+0xca0 0x00000000 
+0xca4 0x000300A0	//88E: 0xca4[10:0]=0xa0, 0xca4[22:12]=0x30						//0x00000080 // reserved
+0xca8 0x00000000	// reserved
+0xcac 0x00000000	// reserved
+0xcb0 0x00000000	// reserved
+0xcb4 0x00000000	// reserved
+0xcb8 0x00000000	// reserved
+0xcbc 0x28000000
+0xcc0 0x00000000	// reserved
+0xcc4 0x00000000	// reserved
+0xcc8 0x00000000	// reserved
+0xccc 0x00000000	// reserved
+0xcd0 0x00000000	// reserved
+0xcd4 0x00000000	// reserved
+0xcd8 0x64b22427	// reserved
+0xcdc 0x00766932	// reserved
+0xce0 0x00222222  
+0xce4 0x00000000
+0xce8 0x37644302
+0xcec 0x2f97d40c
+//
+//=======================
+// PAGE_D ( OFDM_PHY1 )
+//=======================
+0xd00 0x00000740	//88E: support<mcs8						//0x00080740	
+0xd04 0x00020401  
+0xd08 0x0000907f  
+0xd0c 0x20010201 
+0xd10 0xa0633333  
+0xd14 0x3333bc43  
+0xd18 0x7a8f5b6f	//88E: R128 0xd18[2]=0
+0xd2c 0xcc979975  
+0xd30 0x00000000
+0xd34 0x80608000
+0xd38 0x00000000
+0xd3c 0x00127353	//0xd3c[8:6]=3'b101 	0x00027293//88E: R128 0xd3c[24:20]=0
+0xd40 0x00000000
+0xd44 0x00000000
+0xd48 0x00000000
+0xd4c 0x00000000
+0xd50 0x6437140a 
+0xd54 0x00000000 
+0xd58 0x00000282	//88E: R128 0xd58[11:0]=0, 0xd58[23:16]=0
+0xd5c 0x30032064 
+0xd60 0x4653de68
+0xd64 0x04518a3c	//[26]=1:enable L1-SBD//
+0xd68 0x00002101
+0xd6c 0x2a201c16	// DTR
+0xd70 0x1812362e	// DTR
+0xd74 0x322c2220	// DTR
+0xd78 0x000e3c24	// DTR
+//=======================
+// PAGE_E
+//=======================
+0xe00 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, 6M, 9M, 12M, 18M 
+0xe04 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, 24M, 36M, 48M, 54M 
+0xe08 0x0390272d	//0x03902a2a	// Path-A TX AGC codewod, MCS32, 1M 
+0xe10 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, MCS0, MCS1, MCS2, MCS3 
+0xe14 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, MCS4, MCS5, MCS6, MCS7 
+0xe18 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, MCS8, MCS9, MCS10, MCS11 
+0xe1c 0x2d2d2d2d	//0x2a2a2a2a	// Path-A TX AGC codewod, MCS12, MCS13, MCS14, MCS15 
+0xe28 0x00000000        
+0xe30 0x1000dc1f	// 0xe30~0xe60: IQK
+0xe34 0x10008c1f
+0xe38 0x02140102
+0xe3C 0x681604c2
+0xe40 0x01007c00
+0xe44 0x01004800
+0xe48 0xfb000000
+0xe4c 0x000028d1
+0xe50 0x1000dc1f
+0xe54 0x10008c1f
+0xe58 0x02140102
+0xe5C 0x28160d05
+0xe60 0x00000008
+//0xe64 0x281600a0	// Reserved in 92C/88C
+0xe68 0x001b25a4
+0xe6c 0x00c00014	// AFE ctrl reg (ASIC)  Blue-Tooth   
+0xe70 0x00c00014	// AFE ctrl reg (ASIC)  RX_WAIT_CCA 
+0xe74 0x01000014	// AFE ctrl reg (ASIC)  TX_CCK_RFON
+0xe78 0x01000014	// AFE ctrl reg (ASIC)  TX_CCK_BBON
+0xe7c 0x01000014	// AFE ctrl reg (ASIC)  TX_OFDM_RFON
+0xe80 0x01000014	// AFE ctrl reg (ASIC)  TX_OFDM_BBON
+0xe84 0x00c00014	// AFE ctrl reg (ASIC)  TX_TO_RX
+0xe88 0x01000014	// AFE ctrl reg (ASIC)  TX_TO_TX 
+0xe8c 0x00c00014	// AFE ctrl reg (ASIC)  RX_CCK 
+0xed0 0x00c00014	// AFE ctrl reg (ASIC)  RX_OFDM 
+0xed4 0x00c00014	// AFE ctrl reg (ASIC)  RX_WAIT_RIFS 
+0xed8 0x00c00014	// AFE ctrl reg (ASIC)  RX_TO_RX
+0xedc 0x00000014	// AFE ctrl reg (ASIC)  Standby 
+0xee0 0x00000014	// AFE ctrl reg (ASIC)  Sleep
+0xeec 0x01c00014	// AFE ctrl reg (ASIC)  PMPD_ANAEN 
+//
+0xf14 0x00000003	// debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG
+0xf4c 0x00000000	// Only for FPGA PMAC
+0xf00 0x00000300	// enable BBRSTB, bcz HSSI use clk_bb
+0xffff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_MP_88E.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_MP_88E.txt
new file mode 100644
index 000000000..5e73e388c
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_MP_88E.txt
@@ -0,0 +1,4 @@
+//20100311
+0xc30 0x69e9ac4a  //RX false alarm issue
+0xc3c 0x0a979718 //0xc64 0x5116848b  // L1-DC_TH for sensitivity 
+0xffff 0xffff
\ No newline at end of file
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_PG_88E.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_PG_88E.txt
new file mode 100644
index 000000000..7eaa0e0f0
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/PHY_REG_PG_88E.txt
@@ -0,0 +1,144 @@
+//=========================
+// PHY_related MAC register by channel, Wilson 091016
+// Related from willis 090406 PHY_REG_PG.txt for 92S
+//=========================
+//Offset talbe_0 for for EEPROM_0x79[bit0~2]= 0 , Table_0 (20/40MHz, all channel)
+// For Ant A
+0xe00 0xffffffff 0x0a0c0c0c // base on 0x30  //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x02040608 // base on 0x30  //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00       // base on 0x30  //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000   // base on 0x30  //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x0a0c0d0e // base on 0x30  //for MCS=03,02,01,00
+0xe14 0xffffffff 0x02040608 // base on 0x30  //for MCS=07,06,05,04
+0xe18 0xffffffff 0x0a0c0d0e // base on 0x30  //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x02040608 // base on 0x30  //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x0a0c0c0c // base on 0x32  //for 18M,12M,09M,06M
+0x834 0xffffffff 0x02040608 // base on 0x32  //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000   // base on 0x34  //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00	    // base on 0x34  //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x0a0c0d0e // base on 0x32  //for MCS=03,02,01,00
+0x848 0xffffffff 0x02040608 // base on 0x32  //for MCS=07,06,05,04
+0x84c 0xffffffff 0x0a0c0d0e // base on 0x32  //for MCS=11,10,09,08
+0x868 0xffffffff 0x02040608 // base on 0x32  //for MCS=15,14,13,12
+//=========================
+//Offset talbe_1 for EEPROM_0x79[bit0~2]= 1 Ch01-Ch03, Table _1 (20MHz, ch1~ch03)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30  //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30  //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00       // base on 0x30  //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000   // base on 0x30  //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30  //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30  //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30  //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30  //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32  //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32  //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000   // base on 0x34  //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00	    // base on 0x34  //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32  //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32  //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32  //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32  //for MCS=15,14,13,12
+//=========================
+//Offset talbe_2 for Mode  EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _2 (20MHz, ch4~ch09)
+// For Ant A
+0xe00 0xffffffff 0x04040404 // base on 0x30  //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00020204 // base on 0x30  //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00       // base on 0x30  //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000   // base on 0x30  //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x06060606 // base on 0x30  //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00020406 // base on 0x30  //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30  //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30  //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x04040404 // base on 0x32  //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00020204 // base on 0x32  //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000   // base on 0x34  //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00	    // base on 0x34  //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x06060606 // base on 0x32  //for MCS=03,02,01,00
+0x848 0xffffffff 0x00020406 // base on 0x32  //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32  //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32  //for MCS=15,14,13,12
+//=========================
+//Offset talbe_3 for Mode EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _3 (20MHz,  ch10~ch14)
+// For Ant A
+0xe00 0xffffffff 0x00000000 // base on 0x30  //for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x30  //for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00       // base on 0x30  //for CCK 1M , use 17 dB
+0x86c 0xffffff00 0x000000   // base on 0x30  //for CCK 2M, 5.5M, 11M, use 17 dB
+0xe10 0xffffffff 0x00000000 // base on 0x30  //for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x30  //for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x30  //for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x30  //for MCS=15,14,13,12
+// For Ant B
+0x830 0xffffffff 0x00000000 // base on 0x32  //for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x32  //for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000   // base on 0x34  //for CCK 1M, 2M, 5.5M, use 17dB
+0x86c 0x000000ff 0x00	    // base on 0x34  //for CCK 11M, use 17dB
+0x83c 0xffffffff 0x00000000 // base on 0x32  //for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x32  //for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x32  //for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x32  //for MCS=15,14,13,12
+//=========================
+// Offset table _4 for EERPOM_0x79[bit0~2]= 1 Ch01-Ch03, Table _4 (40MHz, ch1~ch03)
+// For Ant_A
+0xe00 0xffffffff 0x00000000 // base on 0x2a  // for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x2a  // for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00       // base on 0x2a // for CCK 1M
+0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M
+0xe10 0xffffffff 0x00000000 // base on 0x2a  // for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x2a  // for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x2a  // for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x2a  // for MCS=15,14,13,12
+// For Ant_B
+0x830 0xffffffff 0x00000000 // base on 0x2a  // for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x2a  // for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000   // base on 0x2a  // for CCK 5.5M, 2M, 1M
+0x86c 0x000000ff 0x00       // base on 0x2a // for CCK 11M
+0x83c 0xffffffff 0x00000000 // base on 0x2a  // for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x2a  // for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x2a  // for MCS=15,14,13,12
+//=========================
+// Offset table _5 for EEPROM_0x79[bit0~2]= 1 Ch04-Ch09, Table _5 (40MHz, ch4~ch09)
+// For Ant_A
+0xe00 0xffffffff 0x04040404 // base on 0x2a  // for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00020204 // base on 0x2a  // for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00       // base on 0x2a // for CCK 1M
+0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M
+0xe10 0xffffffff 0x00000000 // base on 0x2a  // for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x2a  // for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x2a  // for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x2a  //for MCS=15,14,13,12
+// For Ant_B
+0x830 0xffffffff 0x04040404 // base on 0x2a  // for 18M,12M,09M,06M
+0x834 0xffffffff 0x00020204 // base on 0x2a  // for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000   // base on 0x2a  // for CCK 5.5M, 2M, 1M
+0x86c 0x000000ff 0x00       // base on 0x2a // for CCK 11M
+0x83c 0xffffffff 0x00000000 // base on 0x2a  // for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x2a  // for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x2a  // for MCS=15,14,13,12
+//=========================
+// Offset table _6 for EEPROM_0x79[bit0~2]= 1 Ch10-Ch14, Table _6 (40MHz,  ch10~ch14)
+// For Ant_A
+0xe00 0xffffffff 0x00000000 // base on 0x2a  // for 18M,12M,09M,06M
+0xe04 0xffffffff 0x00000000 // base on 0x2a  // for 54M,48M,36M,24M
+0xe08 0x0000ff00 0x00       // base on 0x2a // for CCK 1M
+0x86c 0xffffff00 0x000000 // base on 0x2a // for CCK 11M, 5.5M, 2M
+0xe10 0xffffffff 0x00000000 // base on 0x2a  // for MCS=03,02,01,00
+0xe14 0xffffffff 0x00000000 // base on 0x2a  // for MCS=07,06,05,04
+0xe18 0xffffffff 0x00000000 // base on 0x2a  // for MCS=11,10,09,08
+0xe1c 0xffffffff 0x00000000 // base on 0x2a  // for MCS=15,14,13,12
+// For Ant_B
+0x830 0xffffffff 0x00000000 // base on 0x2a  // for 18M,12M,09M,06M
+0x834 0xffffffff 0x00000000 // base on 0x2a  // for 54M,48M,36M,24M
+0x838 0xffffff00 0x000000   // base on 0x2a  // for CCK 5.5M, 2M, 1M
+0x86c 0x000000ff 0x00       // base on 0x2a // for CCK 11M
+0x83c 0xffffffff 0x00000000 // base on 0x2a  // for MCS=03,02,01,00
+0x848 0xffffffff 0x00000000 // base on 0x2a  // for MCS=07,06,05,04
+0x84c 0xffffffff 0x00000000 // base on 0x2a // for MCS=11,10,09,08
+0x868 0xffffffff 0x00000000 // base on 0x2a  // for MCS=15,14,13,12
+0xff //end of file
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/radio_a_1T_88E.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/radio_a_1T_88E.txt
new file mode 100644
index 000000000..f1b647126
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/radio_a_1T_88E.txt
@@ -0,0 +1,153 @@
+//RLE0406 20111216 for new Tx gain table PAD-2dB
+0x00 0x30000
+0x08 0x84000  //DC leakage
+0x18 0x00407
+0x19 0x00012  //by RDC Steven 0x00C07
+//0x1A 0x00000  //by RDC Steven 0x739D0
+0x1E 0x80009
+0x1F 0x00880
+0x2F 0x1A060
+0x3F 0x00000
+0x42 0x060C0
+0x57 0xd0000  //for 80M OFDM(right) spur
+0x58 0xBE180
+0x67 0x01552
+0x83 0x00000
+0xB0 0xFF8FC
+0xB1 0x54400
+0xB2 0xcCC19
+0xB4 0x43003
+0xB6 0x4953E
+0xB7 0x1C718
+0xB8 0x060FF
+0xB9 0x80001
+0xBA 0x40000
+0xBB 0x00400
+0xBF 0xC0000
+0xC2 0x02400
+0xC3 0x00009
+0xC4 0x40C91
+0xC5 0x99999
+0xC6 0x000A3
+0xC7 0x88820
+0xC8 0x76C06
+0xC9 0x00000
+0xCA 0x80000
+//0xDF 0x00100
+//phking
+0xDF 0x00180 
+0xEF 0x001a0
+0x51 0x6b27d  //0x6b25d :spur
+
+0x52 0x7E49d
+0x53 0x00073
+0x56 0x51FF3
+0x35 0x00086
+0x35 0x00186 //CCK DY swing TX EVM
+0x35 0x00286 //OFDM
+0x36 0x01C25 
+0x36 0x09C25
+0x36 0x11C25
+0x36 0x19C25
+0xb6 0x48538
+0x18 0x00C07
+0X5A 0x4BD00 //TX IMR 4Be00
+0X19 0x739d0
+// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step
+//0X34 0x0aff4
+//0X34 0x09ff7
+//0X34 0x08fea
+//0X34 0x07fed
+//0X34 0x06fe0
+//0X34 0x05fe1
+//0X34 0x045e0
+//0X34 0x031ef
+//0X34 0x020eb
+//0X34 0x010ee
+//0X34 0x0006a
+//Tx gain PAD-2dB 3dB/step for 80M clk spur
+//0x34 0x0adf4
+//0x34 0x09df7
+//0x34 0x08dea    //0x08dea
+//0x34 0x07ded
+//0x34 0x06de0
+//0x34 0x05ced
+//0x34 0x04ce0
+//0x34 0x034e0
+//0x34 0x0246d
+//0x34 0x01460
+//0x34 0x0006f
+//For MP Chip power saving
+0x34 0xadf3
+0x34 0x9df0
+0x34 0x8ded
+0x34 0x7dea
+0x34 0x6de7
+0x34 0x54ee //0x5cea
+0x34 0x44eb //0x4ce7
+0x34 0x34e8 //0x34e7
+0x34 0x246b //0x246a
+0x34 0x1468 //0x1467
+0x34 0x006d //0x0068
+// FOR 1dB step, -5dB
+//0x34 0x0ade8
+//0x34 0x09de9
+//0x34 0x08dea
+//0x34 0x07deb
+//0x34 0x06dec
+//0x34 0x05ded
+//0x34 0x04dee
+//0x34 0x03def
+//0x34 0x02de0
+//0x34 0x01de1
+//0x34 0x00de2
+//FOR 1dB step, -10dB
+//0x34 0x0aded
+//0x34 0x09dee
+//0x34 0x08def
+//0x34 0x07de0
+//0x34 0x06de1
+//0x34 0x05de2
+//0x34 0x04de3
+//0x34 0x03de4
+//0x34 0x02de5
+//0x34 0x01de7
+//0x34 0x00de7
+//phking
+0x00 0x30159 //RX mode
+// RX setting 20111118
+0x84 0x68200
+0x86 0x000ce	// LNA switch by BB control
+0x87 0x48a00
+0x8e 0x65540
+0x8f 0x88000
+// RX gain table 20111118
+0xef 0x020A0 //Rx gaintable WE
+0x3b 0xf02b0
+0x3b 0xef7b0
+0x3b 0xd4fb0     
+0x3b 0xcf060
+0x3b 0xb0090
+0x3b 0xa0080
+0x3b 0x90080
+0x3b 0x8f780
+0x3b 0x722b0
+0x3b 0x6f7b0    // CS gain table
+0x3b 0x54fb0     
+0x3b 0x4f060    //  CS gain table
+0x3b 0x30090
+0x3b 0x20080
+0x3b 0x10080	// HG for CCK
+0x3b 0x0f780	// ULG for CCK
+0xef 0x000A0 //Rx gaintable WEb
+0x00 0x10159 //standby mode
+0x18 0x0f407  //LC calibration
+0xffe 0x0 // delay 50ms
+0xffe 0x0 // delay 50ms
+0x1f 0x80003  //RC calibration
+0xffe 0x0 // delay 50ms
+0xffe 0x0 // delay 50ms
+0x1e 0x00001
+0x1f 0x80000
+0x00 0x30159 //RX mode //pc_wang only
+0xffff 0xffff
diff --git a/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/radio_a_1T_88E_TC.txt b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/radio_a_1T_88E_TC.txt
new file mode 100644
index 000000000..178160375
--- /dev/null
+++ b/target/linux/realtek/files/drivers/net/wireless/rtl8192e/data_88e/radio_a_1T_88E_TC.txt
@@ -0,0 +1,132 @@
+//RLE0406 20111216 for new Tx gain table PAD-2dB
+0x00 0x30000
+0x08 0x84000  //DC leakage
+0x18 0x00407
+0x19 0x00012  //by RDC Steven 0x00C07
+//0x1A 0x00000  //by RDC Steven 0x739D0
+0x1E 0x80009
+0x1F 0x00880
+0x2F 0x1A060
+0x3F 0x00000
+0x42 0x060C0
+0x57 0xd0000  //for 80M OFDM(right) spur
+0x58 0xBE180
+0x67 0x01552
+0x83 0x00000
+0xB0 0xFF8FC
+0xB1 0x54400
+0xB2 0xcCC19
+0xB4 0x43003
+0xB6 0x4953E
+0xB7 0x1C718
+0xB8 0x060FF
+0xB9 0x80001
+0xBA 0x40000
+0xBB 0x00400
+0xBF 0xC0000
+0xC2 0x02400
+0xC3 0x00009
+0xC4 0x40C91
+0xC5 0x99999
+0xC6 0x000A3
+0xC7 0x88820
+0xC8 0x76C06
+0xC9 0x00000
+0xCA 0x80000
+0xDF 0x00000
+//phking
+0xDF 0x00080 
+0xEF 0x001a0
+0x51 0x6b27d  //0x6b25d :spur
+0x52 0x7E49d //APK[4:7] , PA tank[2:0] ,0x7e48d : spur
+0x53 0x00073
+0x56 0x51FF3
+0x35 0x00086
+0x35 0x00186 //CCK DY swing TX EVM
+0x35 0x00286 //OFDM
+0x36 0x01C25 
+0x36 0x09C25
+0x36 0x11C25
+0x36 0x19C25
+0xb6 0x48538
+0x18 0x00C07
+0X5A 0x4BD00 //TX IMR 4Be00
+0X19 0x739d0
+// Tx gain table 111125 for 0x880 AFE 1Vpp /3dB step
+//0X34 0x0aff4
+//0X34 0x09ff7
+//0X34 0x08fea
+//0X34 0x07fed
+//0X34 0x06fe0
+//0X34 0x05fe1
+//0X34 0x045e0
+//0X34 0x031ef
+//0X34 0x020eb
+//0X34 0x010ee
+//0X34 0x0006a
+//Tx gain PAD-2dB 3dB/step for 80M clk spur
+0x34 0x0adf3 //0x34 0x0adf4
+0x34 0x09df0 //0x34 0x09df7
+0x34 0x08ded //0x34 0x08dea    //0x08dea
+0x34 0x07dea //0x34 0x07ded
+0x34 0x06de7 //0x34 0x06de0
+0x34 0x05cea //0x34 0x05ced
+0x34 0x04ce7 //0x34 0x04ce0
+0x34 0x034e7 //0x34 0x034e0
+0x34 0x0246a //0x34 0x0246d
+0x34 0x01467 //0x34 0x01460
+0x34 0x00068 //0x34 0x0006f
+// FOR 1dB step, -5dB
+//0x34 0x0ade8
+//0x34 0x09de9
+//0x34 0x08dea
+//0x34 0x07deb
+//0x34 0x06dec
+//0x34 0x05ded
+//0x34 0x04dee
+//0x34 0x03def
+//0x34 0x02de0
+//0x34 0x01de1
+//0x34 0x00de2
+//FOR 1dB step, -10dB
+//0x34 0x0aded
+//0x34 0x09dee
+//0x34 0x08def
+//0x34 0x07de0
+//0x34 0x06de1
+//0x34 0x05de2
+//0x34 0x04de3
+//0x34 0x03de4
+//0x34 0x02de5
+//0x34 0x01de7
+//0x34 0x00de7
+//phking
+0x00 0x30159 //RX mode
+// RX setting 20111118
+0x84 0x68200
+0x86 0x000ce	// LNA switch by BB control
+0x87 0x48a00
+0x8e 0x65540
+0x8f 0x88000
+// RX gain table 20111118
+0xef 0x020A0 //Rx gaintable WE
+0x3b 0x722b0	// modified by RDC Hillo for optional LNA gain table
+0x3b 0x6f7b0    // CS gain table
+0x3b 0x54fb0     
+0x3b 0x4f060    //  CS gain table
+0x3b 0x30090
+0x3b 0x20080
+0x3b 0x10080	// HG for CCK
+0x3b 0x0f780	// ULG for CCK
+0xef 0x000A0 //Rx gaintable WEb
+0x00 0x10159 //standby mode
+0x18 0x0f407  //LC calibration
+0xffe 0x0 // delay 50ms
+0xffe 0x0 // delay 50ms
+0x1f 0x80003  //RC calibration
+0xffe 0x0 // delay 50ms
+0xffe 0x0 // delay 50ms
+0x1e 0x00001
+0x1f 0x80000
+0x00 0x30159 //RX mode //pc_wang only
+0xffff 0xffff
-- 
cgit v1.2.3